irq = 9;
}
+ PrintDebug("Raising irq %d in the PIC\n", irq);
+
if (irq <= 7) {
- state->master_irr |= 0x1 << irq;
+ state->master_irr |= 0x01 << irq;
} else if ((irq > 7) && (irq < 16)) {
- state->slave_irr |= 0x1 << (irq - 7);
+ state->slave_irr |= 0x01 << (irq - 7);
} else {
+ PrintDebug("Invalid IRQ raised (%d)\n", irq);
return -1;
}
for (i = 0; i < 16; i++) {
if (i <= 7) {
- if (((state->master_irr & ~(state->master_imr)) >> i) == 0x1) {
- return i;
+ if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
+ //state->master_isr |= (0x1 << i);
+ // reset the irr
+ //state->master_irr &= ~(0x1 << i);
+ PrintDebug("IRQ: %d, icw2: %x\n", i, state->master_icw2);
+ return i + state->master_icw2;
}
} else {
- if (((state->slave_irr & ~(state->slave_imr)) >> i) == 0x1) {
- return i;
+ if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
+ //state->slave_isr |= (0x1 << (i - 8));
+ //state->slave_irr &= ~(0x1 << (i - 8));
+ return (i - 8) + state->slave_icw2;
}
}
}
}
+
+
+
+static int pic_begin_irq(void * private_data, int irq) {
+ struct pic_internal * state = (struct pic_internal*)private_data;
+
+ if (irq <= 7) {
+ if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
+ state->master_isr |= (0x1 << irq);
+ state->master_irr &= ~(0x1 << irq);
+ }
+ } else {
+ state->slave_isr |= (0x1 << (irq - 8));
+ state->slave_irr &= ~(0x1 << (irq - 8));
+ }
+
+ return 0;
+}
+
+/*
+static int pic_end_irq(void * private_data, int irq) {
+
+ return 0;
+}
+*/
+
static struct intr_ctrl_ops intr_ops = {
.intr_pending = pic_intr_pending,
.get_intr_number = pic_get_intr_number,
- .raise_intr = pic_raise_intr
+ .raise_intr = pic_raise_intr,
+ .begin_irq = pic_begin_irq,
};
-
-
-
int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
struct pic_internal * state = (struct pic_internal*)dev->private_data;
if (length != 1) {
//error
}
- if ((state->master_ocw3 & 0x3) == 0x2) {
+ if ((state->master_ocw3 & 0x03) == 0x02) {
*(char *)dst = state->master_irr;
- } else if ((state->master_ocw3 & 0x3) == 0x3) {
+ } else if ((state->master_ocw3 & 0x03) == 0x03) {
*(char *)dst = state->master_isr;
} else {
*(char *)dst = 0;
// error
}
- if ((state->slave_ocw3 & 0x3) == 0x2) {
+ if ((state->slave_ocw3 & 0x03) == 0x02) {
*(char*)dst = state->slave_irr;
- } else if ((state->slave_ocw3 & 0x3) == 0x3) {
+ } else if ((state->slave_ocw3 & 0x03) == 0x03) {
*(char *)dst = state->slave_isr;
} else {
*(char *)dst = 0;
if (state->master_state == ICW1) {
state->master_icw1 = cw;
state->master_state = ICW2;
+
} else if (state->master_state == READY) {
if (IS_OCW2(cw)) {
+ // handle the EOI here
+ struct ocw2 * cw2 = (struct ocw2*)&cw;
+
+
+ if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
+ // specific EOI;
+ state->master_isr &= ~(0x01 << cw2->level);
+ } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
+ int i;
+ // Non-specific EOI
+ PrintDebug("Pre ISR = %x\n", state->master_isr);
+ for (i = 0; i < 8; i++) {
+ if (state->master_isr & (0x01 << i)) {
+ state->master_isr &= ~(0x01 << i);
+ break;
+ }
+ }
+ PrintDebug("Post ISR = %x\n", state->master_isr);
+ } else {
+ // error;
+ }
+
state->master_ocw2 = cw;
} else if (IS_OCW3(cw)) {
state->master_ocw3 = cw;
if (state->master_state == ICW2) {
struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
+ PrintDebug("Setting ICW2 = %x\n", cw);
state->master_icw2 = cw;
if (cw1->sngl == 0) {
state->slave_state = ICW2;
} else if (state->slave_state == READY) {
if (IS_OCW2(cw)) {
+ // handle the EOI here
+ struct ocw2 * cw2 = (struct ocw2 *)&cw;
+
+ if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
+ // specific EOI;
+ state->slave_isr &= ~(0x01 << cw2->level);
+ } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
+ int i;
+ // Non-specific EOI
+ PrintDebug("Pre ISR = %x\n", state->slave_isr);
+ for (i = 0; i < 8; i++) {
+ if (state->slave_isr & (0x01 << i)) {
+ state->slave_isr &= ~(0x01 << i);
+ break;
+ }
+ }
+ PrintDebug("Post ISR = %x\n", state->slave_isr);
+ } else {
+ // error;
+ }
+
state->slave_ocw2 = cw;
} else if (IS_OCW3(cw)) {
+ // Basically sets the IRR/ISR read flag
state->slave_ocw3 = cw;
} else {
// error
state->master_icw4 = 0;
state->master_imr = 0;
state->master_ocw2 = 0;
- state->master_ocw3 = 0x2;
+ state->master_ocw3 = 0x02;
state->master_state = ICW1;
state->slave_icw4 = 0;
state->slave_imr = 0;
state->slave_ocw2 = 0;
- state->slave_ocw3 = 0x2;
+ state->slave_ocw3 = 0x02;
state->slave_state = ICW1;
struct vm_device * create_pic() {
struct pic_internal * state = NULL;
- VMMMalloc(struct pic_internal *, state, sizeof(struct pic_internal));
+ V3_Malloc(struct pic_internal *, state, sizeof(struct pic_internal));
struct vm_device *device = create_device("8259A", &dev_ops, state);