#ifdef __V3VEE__
-#include <palacios/vm_dev.h>
+
#include <palacios/vmm_types.h>
#include <palacios/vmm_rbtree.h>
#include <devices/pci_types.h>
-typedef enum {PCI_BAR_IO, PCI_BAR_MEM16, PCI_BAR_MEM32, PCI_BAR_MEM64_LOW, PCI_BAR_MEM64_HIGH, PCI_BAR_NONE} pci_bar_type_t;
-
-typedef enum {PCI_STD_DEVICE, PCI_TO_PCI_BRIDGE, PCI_CARDBUS, PCI_MULTIFUNCTION} pci_device_type_t;
-
-typedef enum { PCI_CLASS_PRE2 = 0x00,
- PCI_CLASS_STORAGE = 0x01,
- PCI_CLASS_NETWORK = 0x02,
- PCI_CLASS_DISPLAY = 0x03,
- PCI_CLASS_MMEDIA = 0x04,
- PCI_CLASS_MEMORY = 0x05,
- PCI_CLASS_BRIDGE = 0x06,
- PCI_CLASS_COMM_CTRL = 0x07,
- PCI_CLASS_BASE_PERIPH = 0x08,
- PCI_CLASS_INPUT = 0x09,
- PCI_CLASS_DOCK = 0x0a,
- PCI_CLASS_PROC = 0x0b,
- PCI_CLASS_SERIAL = 0x0c,
- PCI_CLASS_MISC = 0xff } pci_class_t;
-
-typedef enum { PCI_STORAGE_SUBCLASS_SCSI = 0x00,
- PCI_STORAGE_SUBCLASS_IDE = 0x01,
- PCI_STORAGE_SUBCLASS_FLOPPY = 0x02,
- PCI_STORAGE_SUBCLASS_IPI = 0x03,
- PCI_STORAGE_SUBCLASS_RAID = 0x04,
- PCI_STORAGE_SUBCLASS_OTHER = 0x80 } pci_storage_subclass_t;
-
-
-
-typedef enum { PCI_NET_SUBCLASS_ETHER = 0x00,
- PCI_NET_SUBCLASS_TOKRING = 0x01,
- PCI_NET_SUBCLASS_FDDI = 0x02,
- PCI_NET_SUBCLASS_ATM = 0x03,
- PCI_NET_SUBCLASS_OTHER = 0x80 } pci_network_subclass_t;
-
-typedef enum { PCI_DISPLAY_SUBCLASS_VGA = 0x00,
- PCI_DISPLAY_SUBCLASS_XGA = 0x01,
- PCI_DISPLAY_SUBCLASS_OTHER = 0x80 } pci_display_subclass_t;
-
-typedef enum { PCI_MMEDIA_SUBCLASS_VIDEO = 0x00,
- PCI_MMEDIA_SUBCLASS_AUDIO = 0x01,
- PCI_MMEDIA_SUBCLASS_OTHER = 0x80 } pci_multimedia_subclass_t;
-
-typedef enum { PCI_MEM_SUBCLASS_RAM = 0x00,
- PCI_MEM_SUBCLASS_FLASH = 0x01,
- PCI_MEM_SUBCLASS_OTHER = 0x80 } pci_memory_subclass_t;
-
-typedef enum { PCI_BRIDGE_SUBCLASS_HOST_PCI = 0x00,
- PCI_BRIDGE_SUBCLASS_PCI_ISA = 0x01,
- PCI_BRIDGE_SUBCLASS_PCI_EISA = 0x02,
- PCI_BRIDGE_SUBCLASS_PCI_MICRO = 0x03,
- PCI_BRIDGE_SUBCLASS_PCI_PCI = 0x04,
- PCI_BRIDGE_SUBCLASS_PCI_PCMCIA = 0x05,
- PCI_BRIDGE_SUBCLASS_PCI_NUBUS = 0x06,
- PCI_BRIDGE_SUBCLASS_PCI_CARDBUS = 0x07,
- PCI_BRIDGE_SUBCLASS_PCI_OTHER = 0x80 } pci_bridge_subclass_t;
+struct vm_device;
+
+
+typedef enum { PCI_BAR_IO,
+ PCI_BAR_MEM24,
+ PCI_BAR_MEM32,
+ PCI_BAR_MEM64_LO,
+ PCI_BAR_MEM64_HI,
+ PCI_BAR_PASSTHROUGH,
+ PCI_BAR_NONE } pci_bar_type_t;
+
+typedef enum {PCI_STD_DEVICE, PCI_TO_PCI_BRIDGE, PCI_CARDBUS, PCI_MULTIFUNCTION, PCI_PASSTHROUGH} pci_device_type_t;
+
+
// For the rest of the subclass codes see:
// http://www.acm.uiuc.edu/sigops/roll_your_own/7.c.1.html
#define PCI_AUTO_DEV_NUM (-1)
+struct guest_info;
+
struct pci_device;
struct v3_pci_bar {
struct {
int num_pages;
addr_t default_base_addr;
- int (*mem_read)(addr_t guest_addr, void * dst, uint_t length, void * private_data);
- int (*mem_write)(addr_t guest_addr, void * src, uint_t length, void * private_data);
+ int (*mem_read)(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * private_data);
+ int (*mem_write)(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * private_data);
};
struct {
int num_ports;
uint16_t default_base_port;
- int (*io_read)(ushort_t port, void * dst, uint_t length, struct vm_device * dev);
- int (*io_write)(ushort_t port, void * src, uint_t length, struct vm_device * dev);
+ int (*io_read)(struct guest_info * core, uint16_t port, void * src, uint_t length, void * private_data);
+ int (*io_write)(struct guest_info * core, uint16_t port, void * src, uint_t length, void * private_data);
+ };
+
+ struct {
+ int (*bar_init)(int bar_num, uint32_t * dst, void * private_data);
+ int (*bar_write)(int bar_num, uint32_t * src, void * private_data);
};
};
+
+ void * private_data;
// Internal PCI data
uint32_t val;
};
-#define PCI_IO_BASE(bar_val) (bar_val & 0xfffffffc)
-#define PCI_MEM32_BASE(bar_val) (bar_val & 0xfffffff0)
+#define PCI_IO_MASK 0xfffffffc
+#define PCI_MEM24_MASK 0x000ffff0
+#define PCI_MEM_MASK 0xfffffff0
+#define PCI_MEM64_MASK_HI 0xffffffff
+#define PCI_MEM64_MASK_LO 0xfffffff0
+#define PCI_EXP_ROM_MASK 0xfffff800
+
+
+
+#define PCI_IO_BASE(bar_val) (bar_val & PCI_IO_MASK)
+#define PCI_MEM24_BASE(bar_val) (bar_val & PCI_MEM24_MASK)
+#define PCI_MEM32_BASE(bar_val) (bar_val & PCI_MEM_MASK)
+#define PCI_MEM64_BASE_HI(bar_val) (bar_val & PCI_MEM64_MASK_HI)
+#define PCI_MEM64_BASE_LO(bar_val) (bar_val & PCI_MEM64_MASK_LO)
+#define PCI_EXP_ROM_BASE(rom_val) (rom_val & PCI_EXP_ROM_MASK)
+
struct pci_device {
+ pci_device_type_t type;
+
union {
uint8_t config_space[256];
char name[64];
- struct vm_device * vm_dev; //the corresponding virtual device
+ int (*config_update)(uint_t reg_num, void * src, uint_t length, void * priv_data);
- int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length);
+ int (*cmd_update)(struct pci_device * pci_dev, uchar_t io_enabled, uchar_t mem_enabled);
+ int (*exp_rom_update)(struct pci_device * pci_dev, uint32_t * src, void * private_data);
- int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled);
- int (*ext_rom_update)(struct pci_device *pci_dev);
+ int (*config_write)(uint_t reg_num, void * src, uint_t length, void * private_data);
+ int (*config_read)(uint_t reg_num, void * dst, uint_t length, void * private_data);
- int ext_rom_update_flag;
+
+ int exp_rom_update_flag;
int bar_update_flag;
void * priv_data;
};
+int v3_pci_set_irq_bridge(struct vm_device * pci_bus, int bus_num,
+ int (*raise_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev),
+ int (*lower_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev),
+ struct vm_device * bridge_dev);
+
-struct vm_device * v3_create_pci();
+int v3_pci_raise_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev);
+int v3_pci_lower_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev);
struct pci_device *
v3_pci_register_device(struct vm_device * pci,
int fn_num,
const char * name,
struct v3_pci_bar * bars,
- int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length),
+ int (*config_update)(uint_t reg_num, void * src, uint_t length, void * private_data),
int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
- int (*ext_rom_update)(struct pci_device *pci_dev),
- struct vm_device * dev);
+ int (*exp_rom_update)(struct pci_device * pci_dev, uint32_t * src, void * private_data),
+ void * priv_data);
+
+
+struct pci_device *
+v3_pci_register_passthrough_device(struct vm_device * pci,
+ int bus_num,
+ int dev_num,
+ int fn_num,
+ const char * name,
+ int (*config_write)(uint_t reg_num, void * src, uint_t length, void * private_data),
+ int (*config_read)(uint_t reg_num, void * dst, uint_t length, void * private_data),
+ void * private_data);
#endif