2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Peter Dinda <pdinda@northwestern.edu>
11 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Peter Dinda <pdinda@northwestern.edu>
16 * Jack Lange <jarusl@cs.northwestern.edu>
18 * This is free software. You are permitted to use,
19 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
23 #include <palacios/vmx.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmx_handler.h>
26 #include <palacios/vmcs.h>
27 #include <palacios/vmx_lowlevel.h>
28 #include <palacios/vmm_lowlevel.h>
29 #include <palacios/vmm_ctrl_regs.h>
30 #include <palacios/vmm_config.h>
31 #include <palacios/vmm_time.h>
32 #include <palacios/vm_guest_mem.h>
33 #include <palacios/vmm_direct_paging.h>
34 #include <palacios/vmx_io.h>
35 #include <palacios/vmx_msr.h>
38 #ifndef CONFIG_DEBUG_VMX
40 #define PrintDebug(fmt, args...)
44 static addr_t host_vmcs_ptrs[CONFIG_MAX_CPUS] = { [0 ... CONFIG_MAX_CPUS - 1] = 0};
48 extern int v3_vmx_launch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
49 extern int v3_vmx_resume(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
51 static int inline check_vmcs_write(vmcs_field_t field, addr_t val) {
54 ret = vmcs_write(field,val);
56 if (ret != VMX_SUCCESS) {
57 PrintError("VMWRITE error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
64 static int inline check_vmcs_read(vmcs_field_t field, void * val) {
67 ret = vmcs_read(field, val);
69 if (ret != VMX_SUCCESS) {
70 PrintError("VMREAD error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
77 // For the 32 bit reserved bit fields
78 // MB1s are in the low 32 bits, MBZs are in the high 32 bits of the MSR
79 static uint32_t sanitize_bits1(uint32_t msr_num, uint32_t val) {
82 PrintDebug("sanitize_bits1 (MSR:%x)\n", msr_num);
84 v3_get_msr(msr_num, &mask_msr.hi, &mask_msr.lo);
86 PrintDebug("MSR %x = %x : %x \n", msr_num, mask_msr.hi, mask_msr.lo);
96 static addr_t sanitize_bits2(uint32_t msr_num0, uint32_t msr_num1, addr_t val) {
98 addr_t msr0_val, msr1_val;
100 PrintDebug("sanitize_bits2 (MSR0=%x, MSR1=%x)\n", msr_num0, msr_num1);
102 v3_get_msr(msr_num0, &msr0.hi, &msr0.lo);
103 v3_get_msr(msr_num1, &msr1.hi, &msr1.lo);
105 // This generates a mask that is the natural bit width of the CPU
106 msr0_val = msr0.value;
107 msr1_val = msr1.value;
109 PrintDebug("MSR %x = %p, %x = %p \n", msr_num0, (void*)msr0_val, msr_num1, (void*)msr1_val);
122 static addr_t allocate_vmcs() {
124 struct vmcs_data * vmcs_page = NULL;
126 PrintDebug("Allocating page\n");
128 vmcs_page = (struct vmcs_data *)V3_VAddr(V3_AllocPages(1));
129 memset(vmcs_page, 0, 4096);
131 v3_get_msr(VMX_BASIC_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
133 vmcs_page->revision = ((struct vmx_basic_msr*)&msr)->revision;
134 PrintDebug("VMX Revision: 0x%x\n",vmcs_page->revision);
136 return (addr_t)V3_PAddr((void *)vmcs_page);
142 static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state) {
145 PrintDebug("Loading VMCS\n");
146 vmx_ret = vmcs_load(vmx_state->vmcs_ptr_phys);
148 if (vmx_ret != VMX_SUCCESS) {
149 PrintError("VMPTRLD failed\n");
155 /******* Setup Host State **********/
157 /* Cache GDTR, IDTR, and TR in host struct */
162 } __attribute__((packed)) tmp_seg;
165 __asm__ __volatile__(
171 gdtr_base = tmp_seg.base;
172 vmx_state->host_state.gdtr.base = gdtr_base;
174 __asm__ __volatile__(
180 vmx_state->host_state.idtr.base = tmp_seg.base;
182 __asm__ __volatile__(
188 vmx_state->host_state.tr.selector = tmp_seg.selector;
190 /* The GDTR *index* is bits 3-15 of the selector. */
191 struct tss_descriptor * desc = NULL;
192 desc = (struct tss_descriptor *)(gdtr_base + (8 * (tmp_seg.selector >> 3)));
194 tmp_seg.base = ((desc->base1) |
195 (desc->base2 << 16) |
196 (desc->base3 << 24) |
198 ((uint64_t)desc->base4 << 32)
204 vmx_state->host_state.tr.base = tmp_seg.base;
208 /********** Setup and VMX Control Fields from MSR ***********/
212 struct v3_msr tmp_msr;
214 v3_get_msr(VMX_PINBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
216 /* Add external interrupts, NMI exiting, and virtual NMI */
217 vmx_state->pin_ctrls.value = tmp_msr.lo;
218 vmx_state->pin_ctrls.nmi_exit = 1;
219 vmx_state->pin_ctrls.ext_int_exit = 1;
221 v3_get_msr(VMX_PROCBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
223 vmx_state->pri_proc_ctrls.value = tmp_msr.lo;
224 vmx_state->pri_proc_ctrls.use_io_bitmap = 1;
225 vmx_state->pri_proc_ctrls.hlt_exit = 1;
226 vmx_state->pri_proc_ctrls.invlpg_exit = 1;
227 vmx_state->pri_proc_ctrls.use_msr_bitmap = 1;
228 vmx_state->pri_proc_ctrls.pause_exit = 1;
229 vmx_state->pri_proc_ctrls.tsc_offset = 1;
230 #ifdef CONFIG_TIME_VIRTUALIZE_TSC
231 vmx_state->pri_proc_ctrls.rdtsc_exit = 1;
234 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(info->vm_info->io_map.arch_data));
235 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR,
236 (addr_t)V3_PAddr(info->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
239 vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(info->vm_info->msr_map.arch_data));
241 v3_get_msr(VMX_EXIT_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
242 vmx_state->exit_ctrls.value = tmp_msr.lo;
243 vmx_state->exit_ctrls.host_64_on = 1;
245 if ((vmx_state->exit_ctrls.save_efer == 1) || (vmx_state->exit_ctrls.ld_efer == 1)) {
246 vmx_state->ia32e_avail = 1;
249 v3_get_msr(VMX_ENTRY_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
250 vmx_state->entry_ctrls.value = tmp_msr.lo;
253 struct vmx_exception_bitmap excp_bmap;
258 vmx_ret |= check_vmcs_write(VMCS_EXCP_BITMAP, excp_bmap.value);
260 /******* Setup VMXAssist guest state ***********/
263 info->vm_regs.rsp = 0x80000;
265 struct rflags * flags = (struct rflags *)&(info->ctrl_regs.rflags);
268 /* Print Control MSRs */
269 v3_get_msr(VMX_CR0_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
270 PrintDebug("CR0 MSR: %p\n", (void *)(addr_t)tmp_msr.value);
272 v3_get_msr(VMX_CR4_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
273 PrintDebug("CR4 MSR: %p\n", (void *)(addr_t)tmp_msr.value);
276 #define GUEST_CR0 0x80000031
277 #define GUEST_CR4 0x00002000
278 info->ctrl_regs.cr0 = GUEST_CR0;
279 info->ctrl_regs.cr4 = GUEST_CR4;
281 ((struct cr0_32 *)&(info->shdw_pg_state.guest_cr0))->pe = 1;
284 if (info->shdw_pg_mode == SHADOW_PAGING) {
285 PrintDebug("Creating initial shadow page table\n");
287 if (v3_init_passthrough_pts(info) == -1) {
288 PrintError("Could not initialize passthrough page tables\n");
292 #define CR0_PE 0x00000001
293 #define CR0_PG 0x80000000
296 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG) );
297 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE);
299 info->ctrl_regs.cr3 = info->direct_map_pt;
301 // vmx_state->pinbased_ctrls |= NMI_EXIT;
304 vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
305 vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
308 // Setup segment registers
310 struct v3_segment * seg_reg = (struct v3_segment *)&(info->segments);
314 for (i = 0; i < 10; i++) {
315 seg_reg[i].selector = 3 << 3;
316 seg_reg[i].limit = 0xffff;
317 seg_reg[i].base = 0x0;
320 info->segments.cs.selector = 2<<3;
322 /* Set only the segment registers */
323 for (i = 0; i < 6; i++) {
324 seg_reg[i].limit = 0xfffff;
325 seg_reg[i].granularity = 1;
327 seg_reg[i].system = 1;
329 seg_reg[i].present = 1;
333 info->segments.cs.type = 0xb;
335 info->segments.ldtr.selector = 0x20;
336 info->segments.ldtr.type = 2;
337 info->segments.ldtr.system = 0;
338 info->segments.ldtr.present = 1;
339 info->segments.ldtr.granularity = 0;
342 /************* Map in GDT and vmxassist *************/
344 uint64_t gdt[] __attribute__ ((aligned(32))) = {
345 0x0000000000000000ULL, /* 0x00: reserved */
346 0x0000830000000000ULL, /* 0x08: 32-bit TSS */
347 //0x0000890000000000ULL, /* 0x08: 32-bit TSS */
348 0x00CF9b000000FFFFULL, /* 0x10: CS 32-bit */
349 0x00CF93000000FFFFULL, /* 0x18: DS 32-bit */
350 0x000082000000FFFFULL, /* 0x20: LDTR 32-bit */
353 #define VMXASSIST_GDT 0x10000
354 addr_t vmxassist_gdt = 0;
356 if (v3_gpa_to_hva(info, VMXASSIST_GDT, &vmxassist_gdt) == -1) {
357 PrintError("Could not find VMXASSIST GDT destination\n");
361 memcpy((void *)vmxassist_gdt, gdt, sizeof(uint64_t) * 5);
363 info->segments.gdtr.base = VMXASSIST_GDT;
365 #define VMXASSIST_TSS 0x40000
366 uint64_t vmxassist_tss = VMXASSIST_TSS;
367 gdt[0x08 / sizeof(gdt[0])] |=
368 ((vmxassist_tss & 0xFF000000) << (56 - 24)) |
369 ((vmxassist_tss & 0x00FF0000) << (32 - 16)) |
370 ((vmxassist_tss & 0x0000FFFF) << (16)) |
373 info->segments.tr.selector = 0x08;
374 info->segments.tr.base = vmxassist_tss;
376 //info->segments.tr.type = 0x9;
377 info->segments.tr.type = 0x3;
378 info->segments.tr.system = 0;
379 info->segments.tr.present = 1;
380 info->segments.tr.granularity = 0;
385 #define VMXASSIST_START 0x000d0000
386 extern uint8_t v3_vmxassist_start[];
387 extern uint8_t v3_vmxassist_end[];
388 addr_t vmxassist_dst = 0;
390 if (v3_gpa_to_hva(info, VMXASSIST_START, &vmxassist_dst) == -1) {
391 PrintError("Could not find VMXASSIST destination\n");
395 memcpy((void *)vmxassist_dst, v3_vmxassist_start, v3_vmxassist_end - v3_vmxassist_start);
398 /*** Write all the info to the VMCS ***/
400 #define DEBUGCTL_MSR 0x1d9
401 v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
402 vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
404 info->dbg_regs.dr7 = 0x400;
407 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL);
409 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffUL);
410 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR_HIGH, (addr_t)0xffffffffUL);
413 if (v3_update_vmcs_ctrl_fields(info)) {
414 PrintError("Could not write control fields!\n");
418 if (v3_update_vmcs_host_state(info)) {
419 PrintError("Could not write host state\n");
424 vmx_state->state = VMXASSIST_DISABLED;
429 int v3_init_vmx_vmcs(struct guest_info * info, v3_vm_class_t vm_class) {
430 struct vmx_data * vmx_state = NULL;
433 vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
435 PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state);
437 PrintDebug("Allocating VMCS\n");
438 vmx_state->vmcs_ptr_phys = allocate_vmcs();
440 PrintDebug("VMCS pointer: %p\n", (void *)(vmx_state->vmcs_ptr_phys));
442 info->vmm_data = vmx_state;
444 PrintDebug("Initializing VMCS (addr=%p)\n", info->vmm_data);
446 // TODO: Fix vmcs fields so they're 32-bit
448 PrintDebug("Clearing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
449 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
451 if (vmx_ret != VMX_SUCCESS) {
452 PrintError("VMCLEAR failed\n");
456 if (vm_class == V3_PC_VM) {
457 PrintDebug("Initializing VMCS\n");
458 init_vmcs_bios(info, vmx_state);
460 PrintError("Invalid VM Class\n");
468 int v3_deinit_vmx_vmcs(struct guest_info * core) {
469 struct vmx_data * vmx_state = core->vmm_data;
471 V3_FreePages((void *)(vmx_state->vmcs_ptr_phys), 1);
479 static int update_irq_exit_state(struct guest_info * info) {
480 struct vmx_exit_idt_vec_info idt_vec_info;
482 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
484 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
485 #ifdef CONFIG_DEBUG_INTERRUPTS
486 PrintDebug("Calling v3_injecting_intr\n");
488 info->intr_core_state.irq_started = 0;
489 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
495 static int update_irq_entry_state(struct guest_info * info) {
496 struct vmx_exit_idt_vec_info idt_vec_info;
497 struct vmcs_interrupt_state intr_core_state;
498 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
500 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
501 check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state));
503 /* Check for pending exceptions to inject */
504 if (v3_excp_pending(info)) {
505 struct vmx_entry_int_info int_info;
508 // In VMX, almost every exception is hardware
509 // Software exceptions are pretty much only for breakpoint or overflow
511 int_info.vector = v3_get_excp_number(info);
513 if (info->excp_state.excp_error_code_valid) {
514 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, info->excp_state.excp_error_code);
515 int_info.error_code = 1;
517 #ifdef CONFIG_DEBUG_INTERRUPTS
518 PrintDebug("Injecting exception %d with error code %x\n",
519 int_info.vector, info->excp_state.excp_error_code);
524 #ifdef CONFIG_DEBUG_INTERRUPTS
525 PrintDebug("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip);
527 check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value);
529 v3_injecting_excp(info, int_info.vector);
531 } else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) &&
532 (intr_core_state.val == 0)) {
534 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
536 #ifdef CONFIG_DEBUG_INTERRUPTS
537 PrintDebug("IRQ pending from previous injection\n");
540 // Copy the IDT vectoring info over to reinject the old interrupt
541 if (idt_vec_info.error_code == 1) {
542 uint32_t err_code = 0;
544 check_vmcs_read(VMCS_IDT_VECTOR_ERR, &err_code);
545 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, err_code);
548 idt_vec_info.undef = 0;
549 check_vmcs_write(VMCS_ENTRY_INT_INFO, idt_vec_info.value);
552 struct vmx_entry_int_info ent_int;
555 switch (v3_intr_pending(info)) {
556 case V3_EXTERNAL_IRQ: {
557 info->intr_core_state.irq_vector = v3_get_intr(info);
558 ent_int.vector = info->intr_core_state.irq_vector;
560 ent_int.error_code = 0;
563 #ifdef CONFIG_DEBUG_INTERRUPTS
564 PrintDebug("Injecting Interrupt %d at exit %u(EIP=%p)\n",
565 info->intr_core_state.irq_vector,
566 (uint32_t)info->num_exits,
567 (void *)(addr_t)info->rip);
570 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
571 info->intr_core_state.irq_started = 1;
576 PrintDebug("Injecting NMI\n");
581 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
584 case V3_SOFTWARE_INTR:
585 PrintDebug("Injecting software interrupt\n");
589 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
593 // Not sure what to do here, Intel doesn't have virtual IRQs
594 // May be the same as external interrupts/IRQs
597 case V3_INVALID_INTR:
602 } else if ((v3_intr_pending(info)) && (vmx_info->pri_proc_ctrls.int_wndw_exit == 0)) {
603 // Enable INTR window exiting so we know when IF=1
606 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &instr_len);
608 #ifdef CONFIG_DEBUG_INTERRUPTS
609 PrintDebug("Enabling Interrupt-Window exiting: %d\n", instr_len);
612 vmx_info->pri_proc_ctrls.int_wndw_exit = 1;
613 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
622 static struct vmx_exit_info exit_log[10];
624 static void print_exit_log(struct guest_info * info) {
625 int cnt = info->num_exits % 10;
629 V3_Print("\nExit Log (%d total exits):\n", (uint32_t)info->num_exits);
631 for (i = 0; i < 10; i++) {
632 struct vmx_exit_info * tmp = &exit_log[cnt];
634 V3_Print("%d:\texit_reason = %p\n", i, (void *)(addr_t)tmp->exit_reason);
635 V3_Print("\texit_qual = %p\n", (void *)tmp->exit_qual);
636 V3_Print("\tint_info = %p\n", (void *)(addr_t)tmp->int_info);
637 V3_Print("\tint_err = %p\n", (void *)(addr_t)tmp->int_err);
638 V3_Print("\tinstr_info = %p\n", (void *)(addr_t)tmp->instr_info);
651 * CAUTION and DANGER!!!
653 * The VMCS CANNOT(!!) be accessed outside of the cli/sti calls inside this function
654 * When exectuing a symbiotic call, the VMCS WILL be overwritten, so any dependencies
655 * on its contents will cause things to break. The contents at the time of the exit WILL
656 * change before the exit handler is executed.
658 int v3_vmx_enter(struct guest_info * info) {
660 uint32_t tsc_offset_low, tsc_offset_high;
661 struct vmx_exit_info exit_info;
663 // Conditionally yield the CPU if the timeslice has expired
666 // Perform any additional yielding needed for time adjustment
667 v3_adjust_time(info);
669 // Update timer devices prior to entering VM.
670 v3_update_timers(info);
672 // disable global interrupts for vm state transition
675 v3_vmx_restore_vmcs(info);
678 #ifdef CONFIG_SYMCALL
679 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
680 update_irq_entry_state(info);
683 update_irq_entry_state(info);
688 vmcs_read(VMCS_GUEST_CR3, &guest_cr3);
689 vmcs_write(VMCS_GUEST_CR3, guest_cr3);
692 // Perform last-minute time bookkeeping prior to entering the VM
693 v3_time_enter_vm(info);
695 tsc_offset_high = (uint32_t)((v3_tsc_host_offset(&info->time_state) >> 32) & 0xffffffff);
696 tsc_offset_low = (uint32_t)(v3_tsc_host_offset(&info->time_state) & 0xffffffff);
697 check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high);
698 check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low);
700 if (info->vm_info->run_state == VM_STOPPED) {
701 info->vm_info->run_state = VM_RUNNING;
702 ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs));
704 ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs));
707 // PrintDebug("VMX Exit: ret=%d\n", ret);
709 if (ret != VMX_SUCCESS) {
712 vmcs_read(VMCS_INSTR_ERR, &error);
713 PrintError("VMENTRY Error: %d\n", error);
718 // Immediate exit from VM time bookkeeping
719 v3_time_exit_vm(info);
723 /* Update guest state */
724 v3_vmx_save_vmcs(info);
726 // info->cpl = info->segments.cs.selector & 0x3;
728 info->mem_mode = v3_get_vm_mem_mode(info);
729 info->cpu_mode = v3_get_vm_cpu_mode(info);
732 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len));
733 check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info));
734 check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason));
735 check_vmcs_read(VMCS_EXIT_QUAL, &(exit_info.exit_qual));
736 check_vmcs_read(VMCS_EXIT_INT_INFO, &(exit_info.int_info));
737 check_vmcs_read(VMCS_EXIT_INT_ERR, &(exit_info.int_err));
738 check_vmcs_read(VMCS_GUEST_LINEAR_ADDR, &(exit_info.guest_linear_addr));
740 //PrintDebug("VMX Exit taken, id-qual: %u-%lu\n", exit_info.exit_reason, exit_info.exit_qual);
742 exit_log[info->num_exits % 10] = exit_info;
745 #ifdef CONFIG_SYMCALL
746 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
747 update_irq_exit_state(info);
750 update_irq_exit_state(info);
753 // reenable global interrupts after vm exit
756 // Conditionally yield the CPU if the timeslice has expired
759 if (v3_handle_vmx_exit(info, &exit_info) == -1) {
760 PrintError("Error in VMX exit handler\n");
768 int v3_start_vmx_guest(struct guest_info * info) {
770 PrintDebug("Starting VMX core %u\n", info->cpu_id);
772 if (info->cpu_id == 0) {
773 info->core_run_state = CORE_RUNNING;
774 info->vm_info->run_state = VM_RUNNING;
777 PrintDebug("VMX core %u: Waiting for core initialization\n", info->cpu_id);
779 while (info->core_run_state == CORE_STOPPED) {
781 //PrintDebug("VMX core %u: still waiting for INIT\n",info->cpu_id);
784 PrintDebug("VMX core %u initialized\n", info->cpu_id);
788 PrintDebug("VMX core %u: I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
789 info->cpu_id, info->segments.cs.selector, (void *)(info->segments.cs.base),
790 info->segments.cs.limit, (void *)(info->rip));
793 PrintDebug("VMX core %u: Launching VMX VM\n", info->cpu_id);
799 if (info->vm_info->run_state == VM_STOPPED) {
800 info->core_run_state = CORE_STOPPED;
804 if (v3_vmx_enter(info) == -1) {
806 print_exit_log(info);
812 if (info->vm_info->run_state == VM_STOPPED) {
813 info->core_run_state = CORE_STOPPED;
817 if ((info->num_exits % 5000) == 0) {
818 V3_Print("VMX Exit number %d\n", (uint32_t)info->num_exits);
828 int v3_is_vmx_capable() {
829 v3_msr_t feature_msr;
830 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
832 v3_cpuid(0x1, &eax, &ebx, &ecx, &edx);
834 PrintDebug("ECX: 0x%x\n", ecx);
836 if (ecx & CPUID_1_ECX_VTXFLAG) {
837 v3_get_msr(VMX_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo));
839 PrintDebug("MSRREGlow: 0x%.8x\n", feature_msr.lo);
841 if ((feature_msr.lo & FEATURE_CONTROL_VALID) != FEATURE_CONTROL_VALID) {
842 PrintDebug("VMX is locked -- enable in the BIOS\n");
847 PrintDebug("VMX not supported on this cpu\n");
854 static int has_vmx_nested_paging() {
860 void v3_init_vmx_cpu(int cpu_id) {
861 extern v3_cpu_arch_t v3_cpu_types[];
862 struct v3_msr tmp_msr;
865 v3_get_msr(VMX_CR4_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
868 __asm__ __volatile__ (
870 "orq $0x00002000, %%rbx;"
877 if ((~ret & tmp_msr.value) == 0) {
878 __asm__ __volatile__ (
884 PrintError("Invalid CR4 Settings!\n");
888 __asm__ __volatile__ (
889 "movq %%cr0, %%rbx; "
890 "orq $0x00000020,%%rbx; "
897 __asm__ __volatile__ (
899 "orl $0x00002000, %%ecx;"
906 if ((~ret & tmp_msr.value) == 0) {
907 __asm__ __volatile__ (
913 PrintError("Invalid CR4 Settings!\n");
917 __asm__ __volatile__ (
918 "movl %%cr0, %%ecx; "
919 "orl $0x00000020,%%ecx; "
929 // Should check and return Error here....
932 // Setup VMXON Region
933 host_vmcs_ptrs[cpu_id] = allocate_vmcs();
935 PrintDebug("VMXON pointer: 0x%p\n", (void *)host_vmcs_ptrs[cpu_id]);
937 if (v3_enable_vmx(host_vmcs_ptrs[cpu_id]) == VMX_SUCCESS) {
938 PrintDebug("VMX Enabled\n");
940 PrintError("VMX initialization failure\n");
945 if (has_vmx_nested_paging() == 1) {
946 v3_cpu_types[cpu_id] = V3_VMX_EPT_CPU;
948 v3_cpu_types[cpu_id] = V3_VMX_CPU;
954 void v3_deinit_vmx_cpu(int cpu_id) {
955 extern v3_cpu_arch_t v3_cpu_types[];
956 v3_cpu_types[cpu_id] = V3_INVALID_CPU;
957 V3_FreePages((void *)host_vmcs_ptrs[cpu_id], 1);