2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Peter Dinda <pdinda@northwestern.edu>
11 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Peter Dinda <pdinda@northwestern.edu>
16 * Jack Lange <jarusl@cs.northwestern.edu>
18 * This is free software. You are permitted to use,
19 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
23 #include <palacios/vmx.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmx_handler.h>
26 #include <palacios/vmcs.h>
27 #include <palacios/vmx_lowlevel.h>
28 #include <palacios/vmm_lowlevel.h>
29 #include <palacios/vmm_ctrl_regs.h>
30 #include <palacios/vmm_config.h>
31 #include <palacios/vm_guest_mem.h>
32 #include <palacios/vmm_direct_paging.h>
33 #include <palacios/vmx_io.h>
34 #include <palacios/vmx_msr.h>
36 static addr_t host_vmcs_ptrs[CONFIG_MAX_CPUS] = { [0 ... CONFIG_MAX_CPUS - 1] = 0};
40 extern int v3_vmx_launch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
41 extern int v3_vmx_resume(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
43 static int inline check_vmcs_write(vmcs_field_t field, addr_t val) {
46 ret = vmcs_write(field,val);
48 if (ret != VMX_SUCCESS) {
49 PrintError("VMWRITE error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
56 static int inline check_vmcs_read(vmcs_field_t field, void * val) {
59 ret = vmcs_read(field, val);
61 if (ret != VMX_SUCCESS) {
62 PrintError("VMREAD error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
69 // For the 32 bit reserved bit fields
70 // MB1s are in the low 32 bits, MBZs are in the high 32 bits of the MSR
71 static uint32_t sanitize_bits1(uint32_t msr_num, uint32_t val) {
74 PrintDebug("sanitize_bits1 (MSR:%x)\n", msr_num);
76 v3_get_msr(msr_num, &mask_msr.hi, &mask_msr.lo);
78 PrintDebug("MSR %x = %x : %x \n", msr_num, mask_msr.hi, mask_msr.lo);
88 static addr_t sanitize_bits2(uint32_t msr_num0, uint32_t msr_num1, addr_t val) {
90 addr_t msr0_val, msr1_val;
92 PrintDebug("sanitize_bits2 (MSR0=%x, MSR1=%x)\n", msr_num0, msr_num1);
94 v3_get_msr(msr_num0, &msr0.hi, &msr0.lo);
95 v3_get_msr(msr_num1, &msr1.hi, &msr1.lo);
97 // This generates a mask that is the natural bit width of the CPU
98 msr0_val = msr0.value;
99 msr1_val = msr1.value;
101 PrintDebug("MSR %x = %p, %x = %p \n", msr_num0, (void*)msr0_val, msr_num1, (void*)msr1_val);
114 static addr_t allocate_vmcs() {
116 struct vmcs_data * vmcs_page = NULL;
118 PrintDebug("Allocating page\n");
120 vmcs_page = (struct vmcs_data *)V3_VAddr(V3_AllocPages(1));
121 memset(vmcs_page, 0, 4096);
123 v3_get_msr(VMX_BASIC_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
125 vmcs_page->revision = ((struct vmx_basic_msr*)&msr)->revision;
126 PrintDebug("VMX Revision: 0x%x\n",vmcs_page->revision);
128 return (addr_t)V3_PAddr((void *)vmcs_page);
134 static int init_vmcs_bios(struct guest_info * info, struct vmx_data * vmx_state) {
137 PrintDebug("Loading VMCS\n");
138 vmx_ret = vmcs_load(vmx_state->vmcs_ptr_phys);
140 if (vmx_ret != VMX_SUCCESS) {
141 PrintError("VMPTRLD failed\n");
147 /******* Setup Host State **********/
149 /* Cache GDTR, IDTR, and TR in host struct */
154 } __attribute__((packed)) tmp_seg;
157 __asm__ __volatile__(
163 gdtr_base = tmp_seg.base;
164 vmx_state->host_state.gdtr.base = gdtr_base;
166 __asm__ __volatile__(
172 vmx_state->host_state.idtr.base = tmp_seg.base;
174 __asm__ __volatile__(
180 vmx_state->host_state.tr.selector = tmp_seg.selector;
182 /* The GDTR *index* is bits 3-15 of the selector. */
183 struct tss_descriptor * desc = NULL;
184 desc = (struct tss_descriptor *)(gdtr_base + (8 * (tmp_seg.selector >> 3)));
186 tmp_seg.base = ((desc->base1) |
187 (desc->base2 << 16) |
188 (desc->base3 << 24) |
190 ((uint64_t)desc->base4 << 32)
196 vmx_state->host_state.tr.base = tmp_seg.base;
200 /********** Setup and VMX Control Fields from MSR ***********/
204 struct v3_msr tmp_msr;
206 v3_get_msr(VMX_PINBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
208 /* Add external interrupts, NMI exiting, and virtual NMI */
209 vmx_state->pin_ctrls.value = tmp_msr.lo;
210 vmx_state->pin_ctrls.nmi_exit = 1;
211 vmx_state->pin_ctrls.ext_int_exit = 1;
213 v3_get_msr(VMX_PROCBASED_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
215 vmx_state->pri_proc_ctrls.value = tmp_msr.lo;
216 vmx_state->pri_proc_ctrls.use_io_bitmap = 1;
217 vmx_state->pri_proc_ctrls.hlt_exit = 1;
218 vmx_state->pri_proc_ctrls.invlpg_exit = 1;
219 vmx_state->pri_proc_ctrls.use_msr_bitmap = 1;
220 vmx_state->pri_proc_ctrls.pause_exit = 1;
222 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(info->vm_info->io_map.arch_data));
223 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR,
224 (addr_t)V3_PAddr(info->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
227 vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(info->vm_info->msr_map.arch_data));
229 v3_get_msr(VMX_EXIT_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
230 vmx_state->exit_ctrls.value = tmp_msr.lo;
231 vmx_state->exit_ctrls.host_64_on = 1;
233 if ((vmx_state->exit_ctrls.save_efer == 1) || (vmx_state->exit_ctrls.ld_efer == 1)) {
234 vmx_state->ia32e_avail = 1;
237 v3_get_msr(VMX_ENTRY_CTLS_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
238 vmx_state->entry_ctrls.value = tmp_msr.lo;
241 struct vmx_exception_bitmap excp_bmap;
246 vmx_ret |= check_vmcs_write(VMCS_EXCP_BITMAP, excp_bmap.value);
248 /******* Setup VMXAssist guest state ***********/
251 info->vm_regs.rsp = 0x80000;
253 struct rflags * flags = (struct rflags *)&(info->ctrl_regs.rflags);
256 /* Print Control MSRs */
257 v3_get_msr(VMX_CR0_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
258 PrintDebug("CR0 MSR: %p\n", (void *)(addr_t)tmp_msr.value);
260 v3_get_msr(VMX_CR4_FIXED0_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
261 PrintDebug("CR4 MSR: %p\n", (void *)(addr_t)tmp_msr.value);
264 #define GUEST_CR0 0x80000031
265 #define GUEST_CR4 0x00002000
266 info->ctrl_regs.cr0 = GUEST_CR0;
267 info->ctrl_regs.cr4 = GUEST_CR4;
269 ((struct cr0_32 *)&(info->shdw_pg_state.guest_cr0))->pe = 1;
272 if (info->shdw_pg_mode == SHADOW_PAGING) {
273 PrintDebug("Creating initial shadow page table\n");
275 if (v3_init_passthrough_pts(info) == -1) {
276 PrintError("Could not initialize passthrough page tables\n");
280 #define CR0_PE 0x00000001
281 #define CR0_PG 0x80000000
284 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG) );
285 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE);
287 info->ctrl_regs.cr3 = info->direct_map_pt;
289 // vmx_state->pinbased_ctrls |= NMI_EXIT;
292 vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
293 vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
296 // Setup segment registers
298 struct v3_segment * seg_reg = (struct v3_segment *)&(info->segments);
302 for (i = 0; i < 10; i++) {
303 seg_reg[i].selector = 3 << 3;
304 seg_reg[i].limit = 0xffff;
305 seg_reg[i].base = 0x0;
308 info->segments.cs.selector = 2<<3;
310 /* Set only the segment registers */
311 for (i = 0; i < 6; i++) {
312 seg_reg[i].limit = 0xfffff;
313 seg_reg[i].granularity = 1;
315 seg_reg[i].system = 1;
317 seg_reg[i].present = 1;
321 info->segments.cs.type = 0xb;
323 info->segments.ldtr.selector = 0x20;
324 info->segments.ldtr.type = 2;
325 info->segments.ldtr.system = 0;
326 info->segments.ldtr.present = 1;
327 info->segments.ldtr.granularity = 0;
330 /************* Map in GDT and vmxassist *************/
332 uint64_t gdt[] __attribute__ ((aligned(32))) = {
333 0x0000000000000000ULL, /* 0x00: reserved */
334 0x0000830000000000ULL, /* 0x08: 32-bit TSS */
335 //0x0000890000000000ULL, /* 0x08: 32-bit TSS */
336 0x00CF9b000000FFFFULL, /* 0x10: CS 32-bit */
337 0x00CF93000000FFFFULL, /* 0x18: DS 32-bit */
338 0x000082000000FFFFULL, /* 0x20: LDTR 32-bit */
341 #define VMXASSIST_GDT 0x10000
342 addr_t vmxassist_gdt = 0;
344 if (v3_gpa_to_hva(info, VMXASSIST_GDT, &vmxassist_gdt) == -1) {
345 PrintError("Could not find VMXASSIST GDT destination\n");
349 memcpy((void *)vmxassist_gdt, gdt, sizeof(uint64_t) * 5);
351 info->segments.gdtr.base = VMXASSIST_GDT;
353 #define VMXASSIST_TSS 0x40000
354 uint64_t vmxassist_tss = VMXASSIST_TSS;
355 gdt[0x08 / sizeof(gdt[0])] |=
356 ((vmxassist_tss & 0xFF000000) << (56 - 24)) |
357 ((vmxassist_tss & 0x00FF0000) << (32 - 16)) |
358 ((vmxassist_tss & 0x0000FFFF) << (16)) |
361 info->segments.tr.selector = 0x08;
362 info->segments.tr.base = vmxassist_tss;
364 //info->segments.tr.type = 0x9;
365 info->segments.tr.type = 0x3;
366 info->segments.tr.system = 0;
367 info->segments.tr.present = 1;
368 info->segments.tr.granularity = 0;
373 #define VMXASSIST_START 0x000d0000
374 extern uint8_t v3_vmxassist_start[];
375 extern uint8_t v3_vmxassist_end[];
376 addr_t vmxassist_dst = 0;
378 if (v3_gpa_to_hva(info, VMXASSIST_START, &vmxassist_dst) == -1) {
379 PrintError("Could not find VMXASSIST destination\n");
383 memcpy((void *)vmxassist_dst, v3_vmxassist_start, v3_vmxassist_end - v3_vmxassist_start);
386 /*** Write all the info to the VMCS ***/
388 #define DEBUGCTL_MSR 0x1d9
389 v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
390 vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
392 info->dbg_regs.dr7 = 0x400;
394 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL);
397 if (v3_update_vmcs_ctrl_fields(info)) {
398 PrintError("Could not write control fields!\n");
402 if (v3_update_vmcs_host_state(info)) {
403 PrintError("Could not write host state\n");
408 vmx_state->state = VMXASSIST_DISABLED;
413 int v3_init_vmx_vmcs(struct guest_info * info, v3_vm_class_t vm_class) {
414 struct vmx_data * vmx_state = NULL;
417 vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
419 PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state);
421 PrintDebug("Allocating VMCS\n");
422 vmx_state->vmcs_ptr_phys = allocate_vmcs();
424 PrintDebug("VMCS pointer: %p\n", (void *)(vmx_state->vmcs_ptr_phys));
426 info->vmm_data = vmx_state;
428 PrintDebug("Initializing VMCS (addr=%p)\n", info->vmm_data);
430 // TODO: Fix vmcs fields so they're 32-bit
432 PrintDebug("Clearing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
433 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
435 if (vmx_ret != VMX_SUCCESS) {
436 PrintError("VMCLEAR failed\n");
440 if (vm_class == V3_PC_VM) {
441 PrintDebug("Initializing VMCS\n");
442 init_vmcs_bios(info, vmx_state);
444 PrintError("Invalid VM Class\n");
451 static int update_irq_exit_state(struct guest_info * info) {
452 struct vmx_exit_idt_vec_info idt_vec_info;
454 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
456 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
457 #ifdef CONFIG_DEBUG_INTERRUPTS
458 PrintDebug("Calling v3_injecting_intr\n");
460 info->intr_core_state.irq_started = 0;
461 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
467 static int update_irq_entry_state(struct guest_info * info) {
468 struct vmx_exit_idt_vec_info idt_vec_info;
469 struct vmcs_interrupt_state intr_core_state;
470 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
472 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
473 check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state));
475 /* Check for pending exceptions to inject */
476 if (v3_excp_pending(info)) {
477 struct vmx_entry_int_info int_info;
480 // In VMX, almost every exception is hardware
481 // Software exceptions are pretty much only for breakpoint or overflow
483 int_info.vector = v3_get_excp_number(info);
485 if (info->excp_state.excp_error_code_valid) {
486 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, info->excp_state.excp_error_code);
487 int_info.error_code = 1;
489 #ifdef CONFIG_DEBUG_INTERRUPTS
490 PrintDebug("Injecting exception %d with error code %x\n",
491 int_info.vector, info->excp_state.excp_error_code);
496 #ifdef CONFIG_DEBUG_INTERRUPTS
497 PrintDebug("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip);
499 check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value);
501 v3_injecting_excp(info, int_info.vector);
503 } else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) &&
504 (intr_core_state.val == 0)) {
506 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
508 #ifdef CONFIG_DEBUG_INTERRUPTS
509 PrintDebug("IRQ pending from previous injection\n");
512 // Copy the IDT vectoring info over to reinject the old interrupt
513 if (idt_vec_info.error_code == 1) {
514 uint32_t err_code = 0;
516 check_vmcs_read(VMCS_IDT_VECTOR_ERR, &err_code);
517 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, err_code);
520 idt_vec_info.undef = 0;
521 check_vmcs_write(VMCS_ENTRY_INT_INFO, idt_vec_info.value);
524 struct vmx_entry_int_info ent_int;
527 switch (v3_intr_pending(info)) {
528 case V3_EXTERNAL_IRQ: {
529 info->intr_core_state.irq_vector = v3_get_intr(info);
530 ent_int.vector = info->intr_core_state.irq_vector;
532 ent_int.error_code = 0;
535 #ifdef CONFIG_DEBUG_INTERRUPTS
536 PrintDebug("Injecting Interrupt %d at exit %u(EIP=%p)\n",
537 info->intr_core_state.irq_vector,
538 (uint32_t)info->num_exits,
539 (void *)(addr_t)info->rip);
542 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
543 info->intr_core_state.irq_started = 1;
548 PrintDebug("Injecting NMI\n");
553 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
556 case V3_SOFTWARE_INTR:
557 PrintDebug("Injecting software interrupt\n");
561 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
565 // Not sure what to do here, Intel doesn't have virtual IRQs
566 // May be the same as external interrupts/IRQs
569 case V3_INVALID_INTR:
574 } else if ((v3_intr_pending(info)) && (vmx_info->pri_proc_ctrls.int_wndw_exit == 0)) {
575 // Enable INTR window exiting so we know when IF=1
578 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &instr_len);
580 #ifdef CONFIG_DEBUG_INTERRUPTS
581 PrintDebug("Enabling Interrupt-Window exiting: %d\n", instr_len);
584 vmx_info->pri_proc_ctrls.int_wndw_exit = 1;
585 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
594 static struct vmx_exit_info exit_log[10];
596 static void print_exit_log(struct guest_info * info) {
597 int cnt = info->num_exits % 10;
601 V3_Print("\nExit Log (%d total exits):\n", (uint32_t)info->num_exits);
603 for (i = 0; i < 10; i++) {
604 struct vmx_exit_info * tmp = &exit_log[cnt];
606 V3_Print("%d:\texit_reason = %p\n", i, (void *)(addr_t)tmp->exit_reason);
607 V3_Print("\texit_qual = %p\n", (void *)tmp->exit_qual);
608 V3_Print("\tint_info = %p\n", (void *)(addr_t)tmp->int_info);
609 V3_Print("\tint_err = %p\n", (void *)(addr_t)tmp->int_err);
610 V3_Print("\tinstr_info = %p\n", (void *)(addr_t)tmp->instr_info);
623 * CAUTION and DANGER!!!
625 * The VMCS CANNOT(!!) be accessed outside of the cli/sti calls inside this function
626 * When exectuing a symbiotic call, the VMCS WILL be overwritten, so any dependencies
627 * on its contents will cause things to break. The contents at the time of the exit WILL
628 * change before the exit handler is executed.
630 int v3_vmx_enter(struct guest_info * info) {
632 uint64_t tmp_tsc = 0;
633 struct vmx_exit_info exit_info;
635 // Conditionally yield the CPU if the timeslice has expired
639 // v3_print_guest_state(info);
641 // disable global interrupts for vm state transition
644 v3_vmx_restore_vmcs(info);
647 #ifdef CONFIG_SYMCALL
648 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
649 update_irq_entry_state(info);
652 update_irq_entry_state(info);
657 vmcs_read(VMCS_GUEST_CR3, &guest_cr3);
658 vmcs_write(VMCS_GUEST_CR3, guest_cr3);
661 // We do timer injection here to track real host time.
663 v3_update_time(info, tmp_tsc - info->time_state.cached_host_tsc);
664 rdtscll(info->time_state.cached_host_tsc);
666 if (info->vm_info->run_state == VM_STOPPED) {
667 info->vm_info->run_state = VM_RUNNING;
668 ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs));
670 ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs));
673 // PrintDebug("VMX Exit: ret=%d\n", ret);
675 if (ret != VMX_SUCCESS) {
678 vmcs_read(VMCS_INSTR_ERR, &error);
679 PrintError("VMENTRY Error: %d\n", error);
685 // v3_update_time(info, tmp_tsc - info->time_state.cached_host_tsc);
690 /* Update guest state */
691 v3_vmx_save_vmcs(info);
693 // info->cpl = info->segments.cs.selector & 0x3;
695 info->mem_mode = v3_get_vm_mem_mode(info);
696 info->cpu_mode = v3_get_vm_cpu_mode(info);
699 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len));
700 check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info));
701 check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason));
702 check_vmcs_read(VMCS_EXIT_QUAL, &(exit_info.exit_qual));
703 check_vmcs_read(VMCS_EXIT_INT_INFO, &(exit_info.int_info));
704 check_vmcs_read(VMCS_EXIT_INT_ERR, &(exit_info.int_err));
705 check_vmcs_read(VMCS_GUEST_LINEAR_ADDR, &(exit_info.guest_linear_addr));
707 //PrintDebug("VMX Exit taken, id-qual: %u-%lu\n", exit_info.exit_reason, exit_info.exit_qual);
709 exit_log[info->num_exits % 10] = exit_info;
712 #ifdef CONFIG_SYMCALL
713 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
714 update_irq_exit_state(info);
717 update_irq_exit_state(info);
720 // reenable global interrupts after vm exit
723 // Conditionally yield the CPU if the timeslice has expired
726 if (v3_handle_vmx_exit(info, &exit_info) == -1) {
727 PrintError("Error in VMX exit handler\n");
735 int v3_start_vmx_guest(struct guest_info* info) {
738 PrintDebug("Launching VMX guest\n");
740 rdtscll(info->time_state.cached_host_tsc);
744 if (v3_vmx_enter(info) == -1) {
746 print_exit_log(info);
751 if ((info->num_exits % 5000) == 0) {
752 V3_Print("VMX Exit number %d\n", (uint32_t)info->num_exits);
762 int v3_is_vmx_capable() {
763 v3_msr_t feature_msr;
764 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
766 v3_cpuid(0x1, &eax, &ebx, &ecx, &edx);
768 PrintDebug("ECX: 0x%x\n", ecx);
770 if (ecx & CPUID_1_ECX_VTXFLAG) {
771 v3_get_msr(VMX_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo));
773 PrintDebug("MSRREGlow: 0x%.8x\n", feature_msr.lo);
775 if ((feature_msr.lo & FEATURE_CONTROL_VALID) != FEATURE_CONTROL_VALID) {
776 PrintDebug("VMX is locked -- enable in the BIOS\n");
781 PrintDebug("VMX not supported on this cpu\n");
788 static int has_vmx_nested_paging() {
794 void v3_init_vmx_cpu(int cpu_id) {
795 extern v3_cpu_arch_t v3_cpu_types[];
796 struct v3_msr tmp_msr;
799 v3_get_msr(VMX_CR4_FIXED0_MSR,&(tmp_msr.hi),&(tmp_msr.lo));
801 __asm__ __volatile__ (
803 "orq $0x00002000, %%rbx;"
810 if ((~ret & tmp_msr.value) == 0) {
811 __asm__ __volatile__ (
817 PrintError("Invalid CR4 Settings!\n");
821 __asm__ __volatile__ (
822 "movq %%cr0, %%rbx; "
823 "orq $0x00000020,%%rbx; "
830 __asm__ __volatile__ (
832 "orl $0x00002000, %%ecx;"
839 if ((~ret & tmp_msr.value) == 0) {
840 __asm__ __volatile__ (
846 PrintError("Invalid CR4 Settings!\n");
850 __asm__ __volatile__ (
851 "movl %%cr0, %%ecx; "
852 "orl $0x00000020,%%ecx; "
862 // Should check and return Error here....
865 // Setup VMXON Region
866 host_vmcs_ptrs[cpu_id] = allocate_vmcs();
868 PrintDebug("VMXON pointer: 0x%p\n", (void *)host_vmcs_ptrs[cpu_id]);
870 if (v3_enable_vmx(host_vmcs_ptrs[cpu_id]) == VMX_SUCCESS) {
871 PrintDebug("VMX Enabled\n");
873 PrintError("VMX initialization failure\n");
878 if (has_vmx_nested_paging() == 1) {
879 v3_cpu_types[cpu_id] = V3_VMX_EPT_CPU;
881 v3_cpu_types[cpu_id] = V3_VMX_CPU;