2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2011, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2011, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/vmx.h>
22 #include <palacios/vmm.h>
23 #include <palacios/vmx_handler.h>
24 #include <palacios/vmcs.h>
25 #include <palacios/vmx_lowlevel.h>
26 #include <palacios/vmm_lowlevel.h>
27 #include <palacios/vmm_ctrl_regs.h>
28 #include <palacios/vmm_config.h>
29 #include <palacios/vmm_time.h>
30 #include <palacios/vm_guest_mem.h>
31 #include <palacios/vmm_direct_paging.h>
32 #include <palacios/vmx_io.h>
33 #include <palacios/vmx_msr.h>
34 #include <palacios/vmm_decoder.h>
35 #include <palacios/vmm_barrier.h>
36 #include <palacios/vmm_timeout.h>
38 #ifdef V3_CONFIG_CHECKPOINT
39 #include <palacios/vmm_checkpoint.h>
42 #include <palacios/vmx_ept.h>
43 #include <palacios/vmx_assist.h>
44 #include <palacios/vmx_hw_info.h>
46 #ifndef V3_CONFIG_DEBUG_VMX
48 #define PrintDebug(fmt, args...)
52 /* These fields contain the hardware feature sets supported by the local CPU */
53 static struct vmx_hw_info hw_info;
55 extern v3_cpu_arch_t v3_cpu_types[];
57 static addr_t host_vmcs_ptrs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0};
59 extern int v3_vmx_launch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
60 extern int v3_vmx_resume(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
62 static int inline check_vmcs_write(vmcs_field_t field, addr_t val) {
65 ret = vmcs_write(field, val);
67 if (ret != VMX_SUCCESS) {
68 PrintError("VMWRITE error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
78 static int inline check_vmcs_read(vmcs_field_t field, void * val) {
81 ret = vmcs_read(field, val);
83 if (ret != VMX_SUCCESS) {
84 PrintError("VMREAD error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
93 static addr_t allocate_vmcs() {
94 struct vmcs_data * vmcs_page = NULL;
96 PrintDebug("Allocating page\n");
98 vmcs_page = (struct vmcs_data *)V3_VAddr(V3_AllocPages(1));
99 memset(vmcs_page, 0, 4096);
101 vmcs_page->revision = hw_info.basic_info.revision;
102 PrintDebug("VMX Revision: 0x%x\n", vmcs_page->revision);
104 return (addr_t)V3_PAddr((void *)vmcs_page);
109 static int debug_efer_read(struct guest_info * core, uint_t msr, struct v3_msr * src, void * priv_data) {
110 struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer);
111 V3_Print("\n\nEFER READ\n");
113 v3_print_guest_state(core);
115 src->value = efer->value;
119 static int debug_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) {
120 struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer);
121 V3_Print("\n\nEFER WRITE\n");
123 v3_print_guest_state(core);
125 efer->value = src.value;
128 struct vmx_data * vmx_state = core->vmm_data;
130 V3_Print("Trapping page faults and GPFs\n");
131 vmx_state->excp_bmap.pf = 1;
132 vmx_state->excp_bmap.gp = 1;
134 check_vmcs_write(VMCS_EXCP_BITMAP, vmx_state->excp_bmap.value);
142 static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) {
145 /* Get Available features */
146 struct vmx_pin_ctrls avail_pin_ctrls;
147 avail_pin_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.pin_ctrls));
151 // disable global interrupts for vm state initialization
154 PrintDebug("Loading VMCS\n");
155 vmx_ret = vmcs_load(vmx_state->vmcs_ptr_phys);
156 vmx_state->state = VMX_UNLAUNCHED;
158 if (vmx_ret != VMX_SUCCESS) {
159 PrintError("VMPTRLD failed\n");
164 /*** Setup default state from HW ***/
166 vmx_state->pin_ctrls.value = hw_info.pin_ctrls.def_val;
167 vmx_state->pri_proc_ctrls.value = hw_info.proc_ctrls.def_val;
168 vmx_state->exit_ctrls.value = hw_info.exit_ctrls.def_val;
169 vmx_state->entry_ctrls.value = hw_info.entry_ctrls.def_val;
170 vmx_state->sec_proc_ctrls.value = hw_info.sec_proc_ctrls.def_val;
172 /* Print Control MSRs */
173 PrintDebug("CR0 MSR: %p\n", (void *)(addr_t)hw_info.cr0.value);
174 PrintDebug("CR4 MSR: %p\n", (void *)(addr_t)hw_info.cr4.value);
178 /******* Setup Host State **********/
180 /* Cache GDTR, IDTR, and TR in host struct */
183 /********** Setup VMX Control Fields ***********/
185 /* Add external interrupts, NMI exiting, and virtual NMI */
186 vmx_state->pin_ctrls.nmi_exit = 1;
187 vmx_state->pin_ctrls.ext_int_exit = 1;
190 /* We enable the preemption timer by default to measure accurate guest time */
191 if (avail_pin_ctrls.active_preempt_timer) {
192 V3_Print("VMX Preemption Timer is available\n");
193 vmx_state->pin_ctrls.active_preempt_timer = 1;
194 vmx_state->exit_ctrls.save_preempt_timer = 1;
197 vmx_state->pri_proc_ctrls.hlt_exit = 1;
200 vmx_state->pri_proc_ctrls.pause_exit = 0;
201 vmx_state->pri_proc_ctrls.tsc_offset = 1;
202 #ifdef V3_CONFIG_TIME_VIRTUALIZE_TSC
203 vmx_state->pri_proc_ctrls.rdtsc_exit = 1;
207 vmx_state->pri_proc_ctrls.use_io_bitmap = 1;
208 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(core->vm_info->io_map.arch_data));
209 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR,
210 (addr_t)V3_PAddr(core->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
213 vmx_state->pri_proc_ctrls.use_msr_bitmap = 1;
214 vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data));
219 // Ensure host runs in 64-bit mode at each VM EXIT
220 vmx_state->exit_ctrls.host_64_on = 1;
225 // Restore host's EFER register on each VM EXIT
226 vmx_state->exit_ctrls.ld_efer = 1;
228 // Save/restore guest's EFER register to/from VMCS on VM EXIT/ENTRY
229 vmx_state->exit_ctrls.save_efer = 1;
230 vmx_state->entry_ctrls.ld_efer = 1;
232 vmx_state->exit_ctrls.save_pat = 1;
233 vmx_state->exit_ctrls.ld_pat = 1;
234 vmx_state->entry_ctrls.ld_pat = 1;
236 /* Temporary GPF trap */
237 // vmx_state->excp_bmap.gp = 1;
239 // Setup Guests initial PAT field
240 vmx_ret |= check_vmcs_write(VMCS_GUEST_PAT, 0x0007040600070406LL);
243 if (core->shdw_pg_mode == SHADOW_PAGING) {
244 PrintDebug("Creating initial shadow page table\n");
246 if (v3_init_passthrough_pts(core) == -1) {
247 PrintError("Could not initialize passthrough page tables\n");
251 #define CR0_PE 0x00000001
252 #define CR0_PG 0x80000000
253 #define CR0_WP 0x00010000 // To ensure mem hooks work
254 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP));
257 // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written
258 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE);
260 core->ctrl_regs.cr3 = core->direct_map_pt;
262 // vmx_state->pinbased_ctrls |= NMI_EXIT;
265 vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
266 vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
268 vmx_state->pri_proc_ctrls.invlpg_exit = 1;
270 /* Add page fault exits */
271 vmx_state->excp_bmap.pf = 1;
274 v3_vmxassist_init(core, vmx_state);
276 // Hook all accesses to EFER register
277 v3_hook_msr(core->vm_info, EFER_MSR,
278 &v3_handle_efer_read,
279 &v3_handle_efer_write,
282 } else if ((core->shdw_pg_mode == NESTED_PAGING) &&
283 (v3_cpu_types[core->pcpu_id] == V3_VMX_EPT_CPU)) {
285 #define CR0_PE 0x00000001
286 #define CR0_PG 0x80000000
287 #define CR0_WP 0x00010000 // To ensure mem hooks work
288 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP));
290 // vmx_state->pinbased_ctrls |= NMI_EXIT;
292 // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written
293 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE);
295 /* Disable CR exits */
296 vmx_state->pri_proc_ctrls.cr3_ld_exit = 0;
297 vmx_state->pri_proc_ctrls.cr3_str_exit = 0;
299 vmx_state->pri_proc_ctrls.invlpg_exit = 0;
301 /* Add page fault exits */
302 // vmx_state->excp_bmap.pf = 1; // This should never happen..., enabled to catch bugs
305 v3_vmxassist_init(core, vmx_state);
308 vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls
309 vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging
313 if (v3_init_ept(core, &hw_info) == -1) {
314 PrintError("Error initializing EPT\n");
318 // Hook all accesses to EFER register
319 v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL);
321 } else if ((core->shdw_pg_mode == NESTED_PAGING) &&
322 (v3_cpu_types[core->pcpu_id] == V3_VMX_EPT_UG_CPU)) {
324 // For now we will assume that unrestricted guest mode is assured w/ EPT
327 core->vm_regs.rsp = 0x00;
329 core->vm_regs.rdx = 0x00000f00;
330 core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1
331 core->ctrl_regs.cr0 = 0x00000030;
332 core->ctrl_regs.cr4 = 0x00002010; // Enable VMX and PSE flag
335 core->segments.cs.selector = 0xf000;
336 core->segments.cs.limit = 0xffff;
337 core->segments.cs.base = 0x0000000f0000LL;
339 // (raw attributes = 0xf3)
340 core->segments.cs.type = 0xb;
341 core->segments.cs.system = 0x1;
342 core->segments.cs.dpl = 0x0;
343 core->segments.cs.present = 1;
347 struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds),
348 &(core->segments.es), &(core->segments.fs),
349 &(core->segments.gs), NULL};
351 for ( i = 0; segregs[i] != NULL; i++) {
352 struct v3_segment * seg = segregs[i];
354 seg->selector = 0x0000;
355 // seg->base = seg->selector << 4;
356 seg->base = 0x00000000;
364 // seg->granularity = 1;
369 core->segments.gdtr.limit = 0x0000ffff;
370 core->segments.gdtr.base = 0x0000000000000000LL;
372 core->segments.idtr.limit = 0x0000ffff;
373 core->segments.idtr.base = 0x0000000000000000LL;
375 core->segments.ldtr.selector = 0x0000;
376 core->segments.ldtr.limit = 0x0000ffff;
377 core->segments.ldtr.base = 0x0000000000000000LL;
378 core->segments.ldtr.type = 0x2;
379 core->segments.ldtr.present = 1;
381 core->segments.tr.selector = 0x0000;
382 core->segments.tr.limit = 0x0000ffff;
383 core->segments.tr.base = 0x0000000000000000LL;
384 core->segments.tr.type = 0xb;
385 core->segments.tr.present = 1;
387 // core->dbg_regs.dr6 = 0x00000000ffff0ff0LL;
388 core->dbg_regs.dr7 = 0x0000000000000400LL;
391 vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls
392 vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging
393 vmx_state->sec_proc_ctrls.unrstrct_guest = 1; // enable unrestricted guest operation
396 /* Disable shadow paging stuff */
397 vmx_state->pri_proc_ctrls.cr3_ld_exit = 0;
398 vmx_state->pri_proc_ctrls.cr3_str_exit = 0;
400 vmx_state->pri_proc_ctrls.invlpg_exit = 0;
403 // Cause VM_EXIT whenever the CR4.VMXE bit is set
404 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE);
407 if (v3_init_ept(core, &hw_info) == -1) {
408 PrintError("Error initializing EPT\n");
412 // Hook all accesses to EFER register
413 //v3_hook_msr(core->vm_info, EFER_MSR, &debug_efer_read, &debug_efer_write, core);
414 v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL);
416 PrintError("Invalid Virtual paging mode\n");
423 // Setup SYSCALL/SYSENTER MSRs in load/store area
425 // save STAR, LSTAR, FMASK, KERNEL_GS_BASE MSRs in MSR load/store area
428 struct vmcs_msr_save_area * msr_entries = NULL;
429 int max_msrs = (hw_info.misc_info.max_msr_cache_size + 1) * 4;
432 V3_Print("Setting up MSR load/store areas (max_msr_count=%d)\n", max_msrs);
435 PrintError("Max MSR cache size is too small (%d)\n", max_msrs);
439 vmx_state->msr_area_paddr = (addr_t)V3_AllocPages(1);
441 if (vmx_state->msr_area_paddr == (addr_t)NULL) {
442 PrintError("could not allocate msr load/store area\n");
446 msr_entries = (struct vmcs_msr_save_area *)V3_VAddr((void *)(vmx_state->msr_area_paddr));
447 vmx_state->msr_area = msr_entries; // cache in vmx_info
449 memset(msr_entries, 0, PAGE_SIZE);
451 msr_entries->guest_star.index = IA32_STAR_MSR;
452 msr_entries->guest_lstar.index = IA32_LSTAR_MSR;
453 msr_entries->guest_fmask.index = IA32_FMASK_MSR;
454 msr_entries->guest_kern_gs.index = IA32_KERN_GS_BASE_MSR;
456 msr_entries->host_star.index = IA32_STAR_MSR;
457 msr_entries->host_lstar.index = IA32_LSTAR_MSR;
458 msr_entries->host_fmask.index = IA32_FMASK_MSR;
459 msr_entries->host_kern_gs.index = IA32_KERN_GS_BASE_MSR;
461 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_CNT, 4);
462 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_CNT, 4);
463 msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_CNT, 4);
465 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs));
466 msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs));
467 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->host_msrs));
470 msr_ret |= v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL);
471 msr_ret |= v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL);
472 msr_ret |= v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL);
473 msr_ret |= v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL);
476 // IMPORTANT: These MSRs appear to be cached by the hardware....
477 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL);
478 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL);
479 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL);
481 msr_ret |= v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL);
482 msr_ret |= v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL);
484 msr_ret |= v3_hook_msr(core->vm_info, IA32_PAT_MSR, NULL, NULL, NULL);
486 // Not sure what to do about this... Does not appear to be an explicit hardware cache version...
487 msr_ret |= v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL);
490 PrintError("Error configuring MSR save/restore area\n");
497 /* Sanity check ctrl/reg fields against hw_defaults */
502 /*** Write all the info to the VMCS ***/
506 // IS THIS NECESSARY???
507 #define DEBUGCTL_MSR 0x1d9
508 struct v3_msr tmp_msr;
509 v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
510 vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
511 core->dbg_regs.dr7 = 0x400;
516 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL);
518 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffUL);
519 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR_HIGH, (addr_t)0xffffffffUL);
525 if (v3_update_vmcs_ctrl_fields(core)) {
526 PrintError("Could not write control fields!\n");
531 if (v3_update_vmcs_host_state(core)) {
532 PrintError("Could not write host state\n");
537 // reenable global interrupts for vm state initialization now
538 // that the vm state is initialized. If another VM kicks us off,
539 // it'll update our vmx state so that we know to reload ourself
545 int v3_init_vmx_vmcs(struct guest_info * core, v3_vm_class_t vm_class) {
546 struct vmx_data * vmx_state = NULL;
549 vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
550 memset(vmx_state, 0, sizeof(struct vmx_data));
552 PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state);
554 PrintDebug("Allocating VMCS\n");
555 vmx_state->vmcs_ptr_phys = allocate_vmcs();
557 PrintDebug("VMCS pointer: %p\n", (void *)(vmx_state->vmcs_ptr_phys));
559 core->vmm_data = vmx_state;
560 vmx_state->state = VMX_UNLAUNCHED;
562 PrintDebug("Initializing VMCS (addr=%p)\n", core->vmm_data);
564 // TODO: Fix vmcs fields so they're 32-bit
566 PrintDebug("Clearing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
567 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
569 if (vmx_ret != VMX_SUCCESS) {
570 PrintError("VMCLEAR failed\n");
574 if (vm_class == V3_PC_VM) {
575 PrintDebug("Initializing VMCS\n");
576 if (init_vmcs_bios(core, vmx_state) == -1) {
577 PrintError("Error initializing VMCS to BIOS state\n");
581 PrintError("Invalid VM Class\n");
585 PrintDebug("Serializing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
586 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
592 int v3_deinit_vmx_vmcs(struct guest_info * core) {
593 struct vmx_data * vmx_state = core->vmm_data;
595 V3_FreePages((void *)(vmx_state->vmcs_ptr_phys), 1);
596 V3_FreePages(V3_PAddr(vmx_state->msr_area), 1);
605 #ifdef V3_CONFIG_CHECKPOINT
607 * JRL: This is broken
609 int v3_vmx_save_core(struct guest_info * core, void * ctx){
610 uint64_t vmcs_ptr = vmcs_store();
612 v3_chkpt_save(ctx, "vmcs_data", PAGE_SIZE, (void *)vmcs_ptr);
617 int v3_vmx_load_core(struct guest_info * core, void * ctx){
618 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
619 struct cr0_32 * shadow_cr0;
620 char vmcs[PAGE_SIZE_4KB];
622 v3_chkpt_load(ctx, "vmcs_data", PAGE_SIZE_4KB, vmcs);
624 vmcs_clear(vmx_info->vmcs_ptr_phys);
625 vmcs_load((addr_t)vmcs);
627 v3_vmx_save_vmcs(core);
629 shadow_cr0 = (struct cr0_32 *)&(core->ctrl_regs.cr0);
632 /* Get the CPU mode to set the guest_ia32e entry ctrl */
634 if (core->shdw_pg_mode == SHADOW_PAGING) {
635 if (v3_get_vm_mem_mode(core) == VIRTUAL_MEM) {
636 if (v3_activate_shadow_pt(core) == -1) {
637 PrintError("Failed to activate shadow page tables\n");
641 if (v3_activate_passthrough_pt(core) == -1) {
642 PrintError("Failed to activate passthrough page tables\n");
653 void v3_flush_vmx_vm_core(struct guest_info * core) {
654 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
655 vmcs_clear(vmx_info->vmcs_ptr_phys);
656 vmx_info->state = VMX_UNLAUNCHED;
661 static int update_irq_exit_state(struct guest_info * info) {
662 struct vmx_exit_idt_vec_info idt_vec_info;
664 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
666 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
667 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
668 V3_Print("Calling v3_injecting_intr\n");
670 info->intr_core_state.irq_started = 0;
671 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
677 static int update_irq_entry_state(struct guest_info * info) {
678 struct vmx_exit_idt_vec_info idt_vec_info;
679 struct vmcs_interrupt_state intr_core_state;
680 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
682 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
683 check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state));
685 /* Check for pending exceptions to inject */
686 if (v3_excp_pending(info)) {
687 struct vmx_entry_int_info int_info;
690 // In VMX, almost every exception is hardware
691 // Software exceptions are pretty much only for breakpoint or overflow
693 int_info.vector = v3_get_excp_number(info);
695 if (info->excp_state.excp_error_code_valid) {
696 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, info->excp_state.excp_error_code);
697 int_info.error_code = 1;
699 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
700 V3_Print("Injecting exception %d with error code %x\n",
701 int_info.vector, info->excp_state.excp_error_code);
706 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
707 V3_Print("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip);
709 check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value);
711 v3_injecting_excp(info, int_info.vector);
713 } else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) &&
714 (intr_core_state.val == 0)) {
716 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
718 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
719 V3_Print("IRQ pending from previous injection\n");
722 // Copy the IDT vectoring info over to reinject the old interrupt
723 if (idt_vec_info.error_code == 1) {
724 uint32_t err_code = 0;
726 check_vmcs_read(VMCS_IDT_VECTOR_ERR, &err_code);
727 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, err_code);
730 idt_vec_info.undef = 0;
731 check_vmcs_write(VMCS_ENTRY_INT_INFO, idt_vec_info.value);
734 struct vmx_entry_int_info ent_int;
737 switch (v3_intr_pending(info)) {
738 case V3_EXTERNAL_IRQ: {
739 info->intr_core_state.irq_vector = v3_get_intr(info);
740 ent_int.vector = info->intr_core_state.irq_vector;
742 ent_int.error_code = 0;
745 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
746 V3_Print("Injecting Interrupt %d at exit %u(EIP=%p)\n",
747 info->intr_core_state.irq_vector,
748 (uint32_t)info->num_exits,
749 (void *)(addr_t)info->rip);
752 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
753 info->intr_core_state.irq_started = 1;
758 PrintDebug("Injecting NMI\n");
763 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
766 case V3_SOFTWARE_INTR:
767 PrintDebug("Injecting software interrupt\n");
771 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
775 // Not sure what to do here, Intel doesn't have virtual IRQs
776 // May be the same as external interrupts/IRQs
779 case V3_INVALID_INTR:
784 } else if ((v3_intr_pending(info)) && (vmx_info->pri_proc_ctrls.int_wndw_exit == 0)) {
785 // Enable INTR window exiting so we know when IF=1
788 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &instr_len);
790 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
791 V3_Print("Enabling Interrupt-Window exiting: %d\n", instr_len);
794 vmx_info->pri_proc_ctrls.int_wndw_exit = 1;
795 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
804 static struct vmx_exit_info exit_log[10];
805 static uint64_t rip_log[10];
809 static void print_exit_log(struct guest_info * info) {
810 int cnt = info->num_exits % 10;
814 V3_Print("\nExit Log (%d total exits):\n", (uint32_t)info->num_exits);
816 for (i = 0; i < 10; i++) {
817 struct vmx_exit_info * tmp = &exit_log[cnt];
819 V3_Print("%d:\texit_reason = %p\n", i, (void *)(addr_t)tmp->exit_reason);
820 V3_Print("\texit_qual = %p\n", (void *)tmp->exit_qual);
821 V3_Print("\tint_info = %p\n", (void *)(addr_t)tmp->int_info);
822 V3_Print("\tint_err = %p\n", (void *)(addr_t)tmp->int_err);
823 V3_Print("\tinstr_info = %p\n", (void *)(addr_t)tmp->instr_info);
824 V3_Print("\tguest_linear_addr= %p\n", (void *)(addr_t)tmp->guest_linear_addr);
825 V3_Print("\tRIP = %p\n", (void *)rip_log[cnt]);
839 v3_vmx_config_tsc_virtualization(struct guest_info * info) {
840 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
842 if (info->time_state.time_flags & V3_TIME_TRAP_RDTSC) {
843 if (!vmx_info->pri_proc_ctrls.rdtsc_exit) {
844 vmx_info->pri_proc_ctrls.rdtsc_exit = 1;
845 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
849 uint32_t tsc_offset_low, tsc_offset_high;
851 if (vmx_info->pri_proc_ctrls.rdtsc_exit) {
852 vmx_info->pri_proc_ctrls.rdtsc_exit = 0;
853 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
856 tsc_offset = v3_tsc_host_offset(&info->time_state);
857 tsc_offset_high = (uint32_t)(( tsc_offset >> 32) & 0xffffffff);
858 tsc_offset_low = (uint32_t)(tsc_offset & 0xffffffff);
860 check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high);
861 check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low);
867 * CAUTION and DANGER!!!
869 * The VMCS CANNOT(!!) be accessed outside of the cli/sti calls inside this function
870 * When exectuing a symbiotic call, the VMCS WILL be overwritten, so any dependencies
871 * on its contents will cause things to break. The contents at the time of the exit WILL
872 * change before the exit handler is executed.
874 int v3_vmx_enter(struct guest_info * info) {
876 struct vmx_exit_info exit_info;
877 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
878 uint64_t guest_cycles = 0;
880 // Conditionally yield the CPU if the timeslice has expired
883 // disable global interrupts for vm state transition
886 // Update timer devices late after being in the VM so that as much
887 // of the time in the VM is accounted for as possible. Also do it before
888 // updating IRQ entry state so that any interrupts the timers raise get
889 // handled on the next VM entry. Must be done with interrupts disabled.
890 v3_advance_time(info);
891 v3_update_timers(info);
893 if (vmcs_store() != vmx_info->vmcs_ptr_phys) {
894 vmcs_clear(vmx_info->vmcs_ptr_phys);
895 vmcs_load(vmx_info->vmcs_ptr_phys);
896 vmx_info->state = VMX_UNLAUNCHED;
899 v3_vmx_restore_vmcs(info);
902 #ifdef V3_CONFIG_SYMCALL
903 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
904 update_irq_entry_state(info);
907 update_irq_entry_state(info);
912 vmcs_read(VMCS_GUEST_CR3, &guest_cr3);
913 vmcs_write(VMCS_GUEST_CR3, guest_cr3);
917 // Perform last-minute time bookkeeping prior to entering the VM
918 v3_time_enter_vm(info);
919 v3_vmx_config_tsc_virtualization(info);
923 if (v3_update_vmcs_host_state(info)) {
925 PrintError("Could not write host state\n");
929 if (vmx_info->pin_ctrls.active_preempt_timer) {
930 /* Preemption timer is active */
931 uint32_t preempt_window = 0xffffffff;
933 if (info->timeouts.timeout_active) {
934 preempt_window = info->timeouts.next_timeout;
937 check_vmcs_write(VMCS_PREEMPT_TIMER, preempt_window);
942 uint64_t entry_tsc = 0;
943 uint64_t exit_tsc = 0;
945 if (vmx_info->state == VMX_UNLAUNCHED) {
946 vmx_info->state = VMX_LAUNCHED;
948 ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs));
952 V3_ASSERT(vmx_info->state != VMX_UNLAUNCHED);
954 ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs));
958 guest_cycles = exit_tsc - entry_tsc;
961 // PrintDebug("VMX Exit: ret=%d\n", ret);
963 if (ret != VMX_SUCCESS) {
965 vmcs_read(VMCS_INSTR_ERR, &error);
969 PrintError("VMENTRY Error: %d (launch_ret = %d)\n", error, ret);
976 /* If we have the preemption time, then use it to get more accurate guest time */
977 if (vmx_info->pin_ctrls.active_preempt_timer) {
978 uint32_t cycles_left = 0;
979 check_vmcs_read(VMCS_PREEMPT_TIMER, &(cycles_left));
981 if (info->timeouts.timeout_active) {
982 guest_cycles = info->timeouts.next_timeout - cycles_left;
984 guest_cycles = 0xffffffff - cycles_left;
988 // Immediate exit from VM time bookkeeping
989 v3_time_exit_vm(info, &guest_cycles);
992 /* Update guest state */
993 v3_vmx_save_vmcs(info);
995 // info->cpl = info->segments.cs.selector & 0x3;
997 info->mem_mode = v3_get_vm_mem_mode(info);
998 info->cpu_mode = v3_get_vm_cpu_mode(info);
1002 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len));
1003 check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info));
1004 check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason));
1005 check_vmcs_read(VMCS_EXIT_QUAL, &(exit_info.exit_qual));
1006 check_vmcs_read(VMCS_EXIT_INT_INFO, &(exit_info.int_info));
1007 check_vmcs_read(VMCS_EXIT_INT_ERR, &(exit_info.int_err));
1008 check_vmcs_read(VMCS_GUEST_LINEAR_ADDR, &(exit_info.guest_linear_addr));
1010 if (info->shdw_pg_mode == NESTED_PAGING) {
1011 check_vmcs_read(VMCS_GUEST_PHYS_ADDR, &(exit_info.ept_fault_addr));
1014 //PrintDebug("VMX Exit taken, id-qual: %u-%lu\n", exit_info.exit_reason, exit_info.exit_qual);
1016 exit_log[info->num_exits % 10] = exit_info;
1017 rip_log[info->num_exits % 10] = get_addr_linear(info, info->rip, &(info->segments.cs));
1019 #ifdef V3_CONFIG_SYMCALL
1020 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
1021 update_irq_exit_state(info);
1024 update_irq_exit_state(info);
1027 if (exit_info.exit_reason == VMEXIT_INTR_WINDOW) {
1028 // This is a special case whose only job is to inject an interrupt
1029 vmcs_read(VMCS_PROC_CTRLS, &(vmx_info->pri_proc_ctrls.value));
1030 vmx_info->pri_proc_ctrls.int_wndw_exit = 0;
1031 vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
1033 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
1034 V3_Print("Interrupts available again! (RIP=%llx)\n", info->rip);
1038 // reenable global interrupts after vm exit
1041 // Conditionally yield the CPU if the timeslice has expired
1042 v3_yield_cond(info);
1044 if (v3_handle_vmx_exit(info, &exit_info) == -1) {
1045 PrintError("Error in VMX exit handler (Exit reason=%x)\n", exit_info.exit_reason);
1049 if (info->timeouts.timeout_active) {
1050 /* Check to see if any timeouts have expired */
1051 v3_handle_timeouts(info, guest_cycles);
1058 int v3_start_vmx_guest(struct guest_info * info) {
1060 PrintDebug("Starting VMX core %u\n", info->vcpu_id);
1062 if (info->vcpu_id == 0) {
1063 info->core_run_state = CORE_RUNNING;
1066 PrintDebug("VMX core %u: Waiting for core initialization\n", info->vcpu_id);
1068 while (info->core_run_state == CORE_STOPPED) {
1070 if (info->vm_info->run_state == VM_STOPPED) {
1071 // The VM was stopped before this core was initialized.
1076 //PrintDebug("VMX core %u: still waiting for INIT\n",info->vcpu_id);
1079 PrintDebug("VMX core %u initialized\n", info->vcpu_id);
1081 // We'll be paranoid about race conditions here
1082 v3_wait_at_barrier(info);
1086 PrintDebug("VMX core %u: I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
1087 info->vcpu_id, info->segments.cs.selector, (void *)(info->segments.cs.base),
1088 info->segments.cs.limit, (void *)(info->rip));
1091 PrintDebug("VMX core %u: Launching VMX VM on logical core %u\n", info->vcpu_id, info->pcpu_id);
1093 v3_start_time(info);
1097 if (info->vm_info->run_state == VM_STOPPED) {
1098 info->core_run_state = CORE_STOPPED;
1102 if (v3_vmx_enter(info) == -1) {
1105 addr_t linear_addr = 0;
1107 info->vm_info->run_state = VM_ERROR;
1109 V3_Print("VMX core %u: VMX ERROR!!\n", info->vcpu_id);
1111 v3_print_guest_state(info);
1113 V3_Print("VMX core %u\n", info->vcpu_id);
1115 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
1117 if (info->mem_mode == PHYSICAL_MEM) {
1118 v3_gpa_to_hva(info, linear_addr, &host_addr);
1119 } else if (info->mem_mode == VIRTUAL_MEM) {
1120 v3_gva_to_hva(info, linear_addr, &host_addr);
1123 V3_Print("VMX core %u: Host Address of rip = 0x%p\n", info->vcpu_id, (void *)host_addr);
1125 V3_Print("VMX core %u: Instr (15 bytes) at %p:\n", info->vcpu_id, (void *)host_addr);
1126 v3_dump_mem((uint8_t *)host_addr, 15);
1128 v3_print_stack(info);
1132 print_exit_log(info);
1136 v3_wait_at_barrier(info);
1139 if (info->vm_info->run_state == VM_STOPPED) {
1140 info->core_run_state = CORE_STOPPED;
1144 if ((info->num_exits % 5000) == 0) {
1145 V3_Print("VMX Exit number %d\n", (uint32_t)info->num_exits);
1157 #define VMX_FEATURE_CONTROL_MSR 0x0000003a
1158 #define CPUID_VMX_FEATURES 0x00000005 /* LOCK and VMXON */
1159 #define CPUID_1_ECX_VTXFLAG 0x00000020
1161 int v3_is_vmx_capable() {
1162 v3_msr_t feature_msr;
1163 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1165 v3_cpuid(0x1, &eax, &ebx, &ecx, &edx);
1167 PrintDebug("ECX: 0x%x\n", ecx);
1169 if (ecx & CPUID_1_ECX_VTXFLAG) {
1170 v3_get_msr(VMX_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo));
1172 PrintDebug("MSRREGlow: 0x%.8x\n", feature_msr.lo);
1174 if ((feature_msr.lo & CPUID_VMX_FEATURES) != CPUID_VMX_FEATURES) {
1175 PrintDebug("VMX is locked -- enable in the BIOS\n");
1180 PrintDebug("VMX not supported on this cpu\n");
1188 int v3_reset_vmx_vm_core(struct guest_info * core, addr_t rip) {
1191 if ((core->shdw_pg_mode == NESTED_PAGING) &&
1192 (v3_cpu_types[core->pcpu_id] == V3_VMX_EPT_UG_CPU)) {
1195 core->segments.cs.selector = rip << 8;
1196 core->segments.cs.limit = 0xffff;
1197 core->segments.cs.base = rip << 12;
1199 core->vm_regs.rdx = core->vcpu_id;
1200 core->vm_regs.rbx = rip;
1208 void v3_init_vmx_cpu(int cpu_id) {
1209 addr_t vmx_on_region = 0;
1210 extern v3_cpu_arch_t v3_mach_type;
1212 if (v3_mach_type == V3_INVALID_CPU) {
1213 if (v3_init_vmx_hw(&hw_info) == -1) {
1214 PrintError("Could not initialize VMX hardware features on cpu %d\n", cpu_id);
1222 // Setup VMXON Region
1223 vmx_on_region = allocate_vmcs();
1226 if (vmx_on(vmx_on_region) == VMX_SUCCESS) {
1227 V3_Print("VMX Enabled\n");
1228 host_vmcs_ptrs[cpu_id] = vmx_on_region;
1230 V3_Print("VMX already enabled\n");
1231 V3_FreePages((void *)vmx_on_region, 1);
1234 PrintDebug("VMXON pointer: 0x%p\n", (void *)host_vmcs_ptrs[cpu_id]);
1237 struct vmx_sec_proc_ctrls sec_proc_ctrls;
1238 sec_proc_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.sec_proc_ctrls));
1240 if (sec_proc_ctrls.enable_ept == 0) {
1241 V3_Print("VMX EPT (Nested) Paging not supported\n");
1242 v3_cpu_types[cpu_id] = V3_VMX_CPU;
1243 } else if (sec_proc_ctrls.unrstrct_guest == 0) {
1244 V3_Print("VMX EPT (Nested) Paging supported\n");
1245 v3_cpu_types[cpu_id] = V3_VMX_EPT_CPU;
1247 V3_Print("VMX EPT (Nested) Paging + Unrestricted guest supported\n");
1248 v3_cpu_types[cpu_id] = V3_VMX_EPT_UG_CPU;
1255 void v3_deinit_vmx_cpu(int cpu_id) {
1256 extern v3_cpu_arch_t v3_cpu_types[];
1257 v3_cpu_types[cpu_id] = V3_INVALID_CPU;
1259 if (host_vmcs_ptrs[cpu_id] != 0) {
1260 V3_Print("Disabling VMX\n");
1262 if (vmx_off() != VMX_SUCCESS) {
1263 PrintError("Error executing VMXOFF\n");
1266 V3_FreePages((void *)host_vmcs_ptrs[cpu_id], 1);
1268 host_vmcs_ptrs[cpu_id] = 0;