2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2011, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2011, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/vmx.h>
22 #include <palacios/vmm.h>
23 #include <palacios/vmx_handler.h>
24 #include <palacios/vmcs.h>
25 #include <palacios/vmx_lowlevel.h>
26 #include <palacios/vmm_lowlevel.h>
27 #include <palacios/vmm_ctrl_regs.h>
28 #include <palacios/vmm_config.h>
29 #include <palacios/vmm_time.h>
30 #include <palacios/vm_guest_mem.h>
31 #include <palacios/vmm_direct_paging.h>
32 #include <palacios/vmx_io.h>
33 #include <palacios/vmx_msr.h>
34 #include <palacios/vmm_decoder.h>
35 #include <palacios/vmm_barrier.h>
36 #include <palacios/vmm_timeout.h>
38 #ifdef V3_CONFIG_CHECKPOINT
39 #include <palacios/vmm_checkpoint.h>
42 #include <palacios/vmx_ept.h>
43 #include <palacios/vmx_assist.h>
44 #include <palacios/vmx_hw_info.h>
46 #ifndef V3_CONFIG_DEBUG_VMX
48 #define PrintDebug(fmt, args...)
52 /* These fields contain the hardware feature sets supported by the local CPU */
53 static struct vmx_hw_info hw_info;
55 extern v3_cpu_arch_t v3_mach_type;
57 static addr_t host_vmcs_ptrs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0};
59 extern int v3_vmx_launch(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
60 extern int v3_vmx_resume(struct v3_gprs * vm_regs, struct guest_info * info, struct v3_ctrl_regs * ctrl_regs);
62 static int inline check_vmcs_write(vmcs_field_t field, addr_t val) {
65 ret = vmcs_write(field, val);
67 if (ret != VMX_SUCCESS) {
68 PrintError("VMWRITE error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
78 static int inline check_vmcs_read(vmcs_field_t field, void * val) {
81 ret = vmcs_read(field, val);
83 if (ret != VMX_SUCCESS) {
84 PrintError("VMREAD error on %s!: %d\n", v3_vmcs_field_to_str(field), ret);
93 static addr_t allocate_vmcs() {
94 struct vmcs_data * vmcs_page = NULL;
96 PrintDebug("Allocating page\n");
98 vmcs_page = (struct vmcs_data *)V3_VAddr(V3_AllocPages(1));
99 memset(vmcs_page, 0, 4096);
101 vmcs_page->revision = hw_info.basic_info.revision;
102 PrintDebug("VMX Revision: 0x%x\n", vmcs_page->revision);
104 return (addr_t)V3_PAddr((void *)vmcs_page);
109 static int debug_efer_read(struct guest_info * core, uint_t msr, struct v3_msr * src, void * priv_data) {
110 struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer);
111 V3_Print("\n\nEFER READ (val = %p)\n", (void *)efer->value);
113 v3_print_guest_state(core);
117 src->value = efer->value;
121 static int debug_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data) {
122 struct v3_msr * efer = (struct v3_msr *)&(core->ctrl_regs.efer);
123 V3_Print("\n\nEFER WRITE (old_val = %p) (new_val = %p)\n", (void *)efer->value, (void *)src.value);
125 v3_print_guest_state(core);
128 efer->value = src.value;
135 static int init_vmcs_bios(struct guest_info * core, struct vmx_data * vmx_state) {
138 /* Get Available features */
139 struct vmx_pin_ctrls avail_pin_ctrls;
140 avail_pin_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.pin_ctrls));
144 // disable global interrupts for vm state initialization
147 PrintDebug("Loading VMCS\n");
148 vmx_ret = vmcs_load(vmx_state->vmcs_ptr_phys);
149 vmx_state->state = VMX_UNLAUNCHED;
151 if (vmx_ret != VMX_SUCCESS) {
152 PrintError("VMPTRLD failed\n");
157 /*** Setup default state from HW ***/
159 vmx_state->pin_ctrls.value = hw_info.pin_ctrls.def_val;
160 vmx_state->pri_proc_ctrls.value = hw_info.proc_ctrls.def_val;
161 vmx_state->exit_ctrls.value = hw_info.exit_ctrls.def_val;
162 vmx_state->entry_ctrls.value = hw_info.entry_ctrls.def_val;
163 vmx_state->sec_proc_ctrls.value = hw_info.sec_proc_ctrls.def_val;
165 /* Print Control MSRs */
166 V3_Print("CR0 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr0.req_val, (void *)(addr_t)hw_info.cr0.req_mask);
167 V3_Print("CR4 MSR: req_val=%p, req_mask=%p\n", (void *)(addr_t)hw_info.cr4.req_val, (void *)(addr_t)hw_info.cr4.req_mask);
171 /******* Setup Host State **********/
173 /* Cache GDTR, IDTR, and TR in host struct */
176 /********** Setup VMX Control Fields ***********/
178 /* Add external interrupts, NMI exiting, and virtual NMI */
179 vmx_state->pin_ctrls.nmi_exit = 1;
180 vmx_state->pin_ctrls.ext_int_exit = 1;
183 /* We enable the preemption timer by default to measure accurate guest time */
184 if (avail_pin_ctrls.active_preempt_timer) {
185 V3_Print("VMX Preemption Timer is available\n");
186 vmx_state->pin_ctrls.active_preempt_timer = 1;
187 vmx_state->exit_ctrls.save_preempt_timer = 1;
190 vmx_state->pri_proc_ctrls.hlt_exit = 1;
193 vmx_state->pri_proc_ctrls.pause_exit = 0;
194 vmx_state->pri_proc_ctrls.tsc_offset = 1;
195 #ifdef V3_CONFIG_TIME_VIRTUALIZE_TSC
196 vmx_state->pri_proc_ctrls.rdtsc_exit = 1;
200 vmx_state->pri_proc_ctrls.use_io_bitmap = 1;
201 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_A_ADDR, (addr_t)V3_PAddr(core->vm_info->io_map.arch_data));
202 vmx_ret |= check_vmcs_write(VMCS_IO_BITMAP_B_ADDR,
203 (addr_t)V3_PAddr(core->vm_info->io_map.arch_data) + PAGE_SIZE_4KB);
206 vmx_state->pri_proc_ctrls.use_msr_bitmap = 1;
207 vmx_ret |= check_vmcs_write(VMCS_MSR_BITMAP, (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data));
212 // Ensure host runs in 64-bit mode at each VM EXIT
213 vmx_state->exit_ctrls.host_64_on = 1;
218 // Restore host's EFER register on each VM EXIT
219 vmx_state->exit_ctrls.ld_efer = 1;
221 // Save/restore guest's EFER register to/from VMCS on VM EXIT/ENTRY
222 vmx_state->exit_ctrls.save_efer = 1;
223 vmx_state->entry_ctrls.ld_efer = 1;
225 vmx_state->exit_ctrls.save_pat = 1;
226 vmx_state->exit_ctrls.ld_pat = 1;
227 vmx_state->entry_ctrls.ld_pat = 1;
229 /* Temporary GPF trap */
230 // vmx_state->excp_bmap.gp = 1;
232 // Setup Guests initial PAT field
233 vmx_ret |= check_vmcs_write(VMCS_GUEST_PAT, 0x0007040600070406LL);
236 if (core->shdw_pg_mode == SHADOW_PAGING) {
237 PrintDebug("Creating initial shadow page table\n");
239 if (v3_init_passthrough_pts(core) == -1) {
240 PrintError("Could not initialize passthrough page tables\n");
244 #define CR0_PE 0x00000001
245 #define CR0_PG 0x80000000
246 #define CR0_WP 0x00010000 // To ensure mem hooks work
247 #define CR0_NE 0x00000020
248 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE));
251 // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written
252 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE);
254 core->ctrl_regs.cr3 = core->direct_map_pt;
256 // vmx_state->pinbased_ctrls |= NMI_EXIT;
259 vmx_state->pri_proc_ctrls.cr3_ld_exit = 1;
260 vmx_state->pri_proc_ctrls.cr3_str_exit = 1;
262 vmx_state->pri_proc_ctrls.invlpg_exit = 1;
264 /* Add page fault exits */
265 vmx_state->excp_bmap.pf = 1;
268 v3_vmxassist_init(core, vmx_state);
270 // Hook all accesses to EFER register
271 v3_hook_msr(core->vm_info, EFER_MSR,
272 &v3_handle_efer_read,
273 &v3_handle_efer_write,
276 } else if ((core->shdw_pg_mode == NESTED_PAGING) &&
277 (v3_mach_type == V3_VMX_EPT_CPU)) {
279 #define CR0_PE 0x00000001
280 #define CR0_PG 0x80000000
281 #define CR0_WP 0x00010000 // To ensure mem hooks work
282 #define CR0_NE 0x00000020
283 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, (CR0_PE | CR0_PG | CR0_WP | CR0_NE));
285 // vmx_state->pinbased_ctrls |= NMI_EXIT;
287 // Cause VM_EXIT whenever CR4.VMXE or CR4.PAE bits are written
288 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE | CR4_PAE);
290 /* Disable CR exits */
291 vmx_state->pri_proc_ctrls.cr3_ld_exit = 0;
292 vmx_state->pri_proc_ctrls.cr3_str_exit = 0;
294 vmx_state->pri_proc_ctrls.invlpg_exit = 0;
296 /* Add page fault exits */
297 // vmx_state->excp_bmap.pf = 1; // This should never happen..., enabled to catch bugs
300 v3_vmxassist_init(core, vmx_state);
303 vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls
304 vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging
308 if (v3_init_ept(core, &hw_info) == -1) {
309 PrintError("Error initializing EPT\n");
313 // Hook all accesses to EFER register
314 v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL);
316 } else if ((core->shdw_pg_mode == NESTED_PAGING) &&
317 (v3_mach_type == V3_VMX_EPT_UG_CPU)) {
319 // For now we will assume that unrestricted guest mode is assured w/ EPT
322 core->vm_regs.rsp = 0x00;
324 core->vm_regs.rdx = 0x00000f00;
325 core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1
326 core->ctrl_regs.cr0 = 0x60010030;
327 core->ctrl_regs.cr4 = 0x00002010; // Enable VMX and PSE flag
330 core->segments.cs.selector = 0xf000;
331 core->segments.cs.limit = 0xffff;
332 core->segments.cs.base = 0x0000000f0000LL;
334 // (raw attributes = 0xf3)
335 core->segments.cs.type = 0xb;
336 core->segments.cs.system = 0x1;
337 core->segments.cs.dpl = 0x0;
338 core->segments.cs.present = 1;
342 struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds),
343 &(core->segments.es), &(core->segments.fs),
344 &(core->segments.gs), NULL};
346 for ( i = 0; segregs[i] != NULL; i++) {
347 struct v3_segment * seg = segregs[i];
349 seg->selector = 0x0000;
350 // seg->base = seg->selector << 4;
351 seg->base = 0x00000000;
359 // seg->granularity = 1;
364 core->segments.gdtr.limit = 0x0000ffff;
365 core->segments.gdtr.base = 0x0000000000000000LL;
367 core->segments.idtr.limit = 0x0000ffff;
368 core->segments.idtr.base = 0x0000000000000000LL;
370 core->segments.ldtr.selector = 0x0000;
371 core->segments.ldtr.limit = 0x0000ffff;
372 core->segments.ldtr.base = 0x0000000000000000LL;
373 core->segments.ldtr.type = 0x2;
374 core->segments.ldtr.present = 1;
376 core->segments.tr.selector = 0x0000;
377 core->segments.tr.limit = 0x0000ffff;
378 core->segments.tr.base = 0x0000000000000000LL;
379 core->segments.tr.type = 0xb;
380 core->segments.tr.present = 1;
382 // core->dbg_regs.dr6 = 0x00000000ffff0ff0LL;
383 core->dbg_regs.dr7 = 0x0000000000000400LL;
386 vmx_state->pri_proc_ctrls.sec_ctrls = 1; // Enable secondary proc controls
387 vmx_state->sec_proc_ctrls.enable_ept = 1; // enable EPT paging
388 vmx_state->sec_proc_ctrls.unrstrct_guest = 1; // enable unrestricted guest operation
391 /* Disable shadow paging stuff */
392 vmx_state->pri_proc_ctrls.cr3_ld_exit = 0;
393 vmx_state->pri_proc_ctrls.cr3_str_exit = 0;
395 vmx_state->pri_proc_ctrls.invlpg_exit = 0;
398 // Cause VM_EXIT whenever the CR4.VMXE bit is set
399 vmx_ret |= check_vmcs_write(VMCS_CR4_MASK, CR4_VMXE);
400 #define CR0_NE 0x00000020
401 vmx_ret |= check_vmcs_write(VMCS_CR0_MASK, CR0_NE);
402 //((struct cr0_32 *)&(core->shdw_pg_state.guest_cr0))->ne = 1;
404 if (v3_init_ept(core, &hw_info) == -1) {
405 PrintError("Error initializing EPT\n");
409 // Hook all accesses to EFER register
410 // v3_hook_msr(core->vm_info, EFER_MSR, &debug_efer_read, &debug_efer_write, core);
411 v3_hook_msr(core->vm_info, EFER_MSR, NULL, NULL, NULL);
413 PrintError("Invalid Virtual paging mode (pg_mode=%d) (mach_type=%d)\n", core->shdw_pg_mode, v3_mach_type);
420 // Setup SYSCALL/SYSENTER MSRs in load/store area
422 // save STAR, LSTAR, FMASK, KERNEL_GS_BASE MSRs in MSR load/store area
425 struct vmcs_msr_save_area * msr_entries = NULL;
426 int max_msrs = (hw_info.misc_info.max_msr_cache_size + 1) * 4;
429 V3_Print("Setting up MSR load/store areas (max_msr_count=%d)\n", max_msrs);
432 PrintError("Max MSR cache size is too small (%d)\n", max_msrs);
436 vmx_state->msr_area_paddr = (addr_t)V3_AllocPages(1);
438 if (vmx_state->msr_area_paddr == (addr_t)NULL) {
439 PrintError("could not allocate msr load/store area\n");
443 msr_entries = (struct vmcs_msr_save_area *)V3_VAddr((void *)(vmx_state->msr_area_paddr));
444 vmx_state->msr_area = msr_entries; // cache in vmx_info
446 memset(msr_entries, 0, PAGE_SIZE);
448 msr_entries->guest_star.index = IA32_STAR_MSR;
449 msr_entries->guest_lstar.index = IA32_LSTAR_MSR;
450 msr_entries->guest_fmask.index = IA32_FMASK_MSR;
451 msr_entries->guest_kern_gs.index = IA32_KERN_GS_BASE_MSR;
453 msr_entries->host_star.index = IA32_STAR_MSR;
454 msr_entries->host_lstar.index = IA32_LSTAR_MSR;
455 msr_entries->host_fmask.index = IA32_FMASK_MSR;
456 msr_entries->host_kern_gs.index = IA32_KERN_GS_BASE_MSR;
458 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_CNT, 4);
459 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_CNT, 4);
460 msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_CNT, 4);
462 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_STORE_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs));
463 msr_ret |= check_vmcs_write(VMCS_ENTRY_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->guest_msrs));
464 msr_ret |= check_vmcs_write(VMCS_EXIT_MSR_LOAD_ADDR, (addr_t)V3_PAddr(msr_entries->host_msrs));
467 msr_ret |= v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL);
468 msr_ret |= v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL);
469 msr_ret |= v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL);
470 msr_ret |= v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL);
473 // IMPORTANT: These MSRs appear to be cached by the hardware....
474 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL);
475 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL);
476 msr_ret |= v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL);
478 msr_ret |= v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL);
479 msr_ret |= v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL);
481 msr_ret |= v3_hook_msr(core->vm_info, IA32_PAT_MSR, NULL, NULL, NULL);
483 // Not sure what to do about this... Does not appear to be an explicit hardware cache version...
484 msr_ret |= v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL);
487 PrintError("Error configuring MSR save/restore area\n");
494 /* Sanity check ctrl/reg fields against hw_defaults */
499 /*** Write all the info to the VMCS ***/
503 // IS THIS NECESSARY???
504 #define DEBUGCTL_MSR 0x1d9
505 struct v3_msr tmp_msr;
506 v3_get_msr(DEBUGCTL_MSR, &(tmp_msr.hi), &(tmp_msr.lo));
507 vmx_ret |= check_vmcs_write(VMCS_GUEST_DBG_CTL, tmp_msr.value);
508 core->dbg_regs.dr7 = 0x400;
513 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffffffffffULL);
515 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR, (addr_t)0xffffffffUL);
516 vmx_ret |= check_vmcs_write(VMCS_LINK_PTR_HIGH, (addr_t)0xffffffffUL);
522 if (v3_update_vmcs_ctrl_fields(core)) {
523 PrintError("Could not write control fields!\n");
528 if (v3_update_vmcs_host_state(core)) {
529 PrintError("Could not write host state\n");
534 // reenable global interrupts for vm state initialization now
535 // that the vm state is initialized. If another VM kicks us off,
536 // it'll update our vmx state so that we know to reload ourself
543 static void __init_vmx_vmcs(void * arg) {
544 struct guest_info * core = arg;
545 struct vmx_data * vmx_state = NULL;
548 vmx_state = (struct vmx_data *)V3_Malloc(sizeof(struct vmx_data));
549 memset(vmx_state, 0, sizeof(struct vmx_data));
551 PrintDebug("vmx_data pointer: %p\n", (void *)vmx_state);
553 PrintDebug("Allocating VMCS\n");
554 vmx_state->vmcs_ptr_phys = allocate_vmcs();
556 PrintDebug("VMCS pointer: %p\n", (void *)(vmx_state->vmcs_ptr_phys));
558 core->vmm_data = vmx_state;
559 vmx_state->state = VMX_UNLAUNCHED;
561 PrintDebug("Initializing VMCS (addr=%p)\n", core->vmm_data);
563 // TODO: Fix vmcs fields so they're 32-bit
565 PrintDebug("Clearing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
566 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
568 if (vmx_ret != VMX_SUCCESS) {
569 PrintError("VMCLEAR failed\n");
573 if (core->vm_info->vm_class == V3_PC_VM) {
574 PrintDebug("Initializing VMCS\n");
575 if (init_vmcs_bios(core, vmx_state) == -1) {
576 PrintError("Error initializing VMCS to BIOS state\n");
580 PrintError("Invalid VM Class\n");
584 PrintDebug("Serializing VMCS: %p\n", (void *)vmx_state->vmcs_ptr_phys);
585 vmx_ret = vmcs_clear(vmx_state->vmcs_ptr_phys);
587 core->core_run_state = CORE_STOPPED;
593 int v3_init_vmx_vmcs(struct guest_info * core, v3_vm_class_t vm_class) {
594 extern v3_cpu_arch_t v3_cpu_types[];
596 if (v3_cpu_types[V3_Get_CPU()] == V3_INVALID_CPU) {
599 for (i = 0; i < V3_CONFIG_MAX_CPUS; i++) {
600 if (v3_cpu_types[i] != V3_INVALID_CPU) {
605 if (i == V3_CONFIG_MAX_CPUS) {
606 PrintError("Could not find VALID CPU for VMX guest initialization\n");
610 V3_Call_On_CPU(i, __init_vmx_vmcs, core);
613 __init_vmx_vmcs(core);
616 if (core->core_run_state != CORE_STOPPED) {
617 PrintError("Error initializing VMX Core\n");
625 int v3_deinit_vmx_vmcs(struct guest_info * core) {
626 struct vmx_data * vmx_state = core->vmm_data;
628 V3_FreePages((void *)(vmx_state->vmcs_ptr_phys), 1);
629 V3_FreePages(V3_PAddr(vmx_state->msr_area), 1);
638 #ifdef V3_CONFIG_CHECKPOINT
640 * JRL: This is broken
642 int v3_vmx_save_core(struct guest_info * core, void * ctx){
643 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
645 // note that the vmcs pointer is an HPA, but we need an HVA
646 if (v3_chkpt_save(ctx, "vmcs_data", PAGE_SIZE_4KB,
647 V3_VAddr((void*) (vmx_info->vmcs_ptr_phys))) ==-1) {
648 PrintError("Could not save vmcs data for VMX\n");
655 int v3_vmx_load_core(struct guest_info * core, void * ctx){
656 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
657 struct cr0_32 * shadow_cr0;
658 addr_t vmcs_page_paddr; //HPA
660 vmcs_page_paddr = (addr_t) V3_AllocPages(1);
662 if (!vmcs_page_paddr) {
663 PrintError("Could not allocate space for a vmcs in VMX\n");
667 if (v3_chkpt_load(ctx, "vmcs_data", PAGE_SIZE_4KB,
668 V3_VAddr((void *)vmcs_page_paddr)) == -1) {
669 PrintError("Could not load vmcs data for VMX\n");
673 vmcs_clear(vmx_info->vmcs_ptr_phys);
675 // Probably need to delete the old one...
676 V3_FreePages((void*)(vmx_info->vmcs_ptr_phys),1);
678 vmcs_load(vmcs_page_paddr);
680 v3_vmx_save_vmcs(core);
682 shadow_cr0 = (struct cr0_32 *)&(core->ctrl_regs.cr0);
685 /* Get the CPU mode to set the guest_ia32e entry ctrl */
687 if (core->shdw_pg_mode == SHADOW_PAGING) {
688 if (v3_get_vm_mem_mode(core) == VIRTUAL_MEM) {
689 if (v3_activate_shadow_pt(core) == -1) {
690 PrintError("Failed to activate shadow page tables\n");
694 if (v3_activate_passthrough_pt(core) == -1) {
695 PrintError("Failed to activate passthrough page tables\n");
706 void v3_flush_vmx_vm_core(struct guest_info * core) {
707 struct vmx_data * vmx_info = (struct vmx_data *)(core->vmm_data);
708 vmcs_clear(vmx_info->vmcs_ptr_phys);
709 vmx_info->state = VMX_UNLAUNCHED;
714 static int update_irq_exit_state(struct guest_info * info) {
715 struct vmx_exit_idt_vec_info idt_vec_info;
717 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
719 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 0)) {
720 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
721 V3_Print("Calling v3_injecting_intr\n");
723 info->intr_core_state.irq_started = 0;
724 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
730 static int update_irq_entry_state(struct guest_info * info) {
731 struct vmx_exit_idt_vec_info idt_vec_info;
732 struct vmcs_interrupt_state intr_core_state;
733 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
735 check_vmcs_read(VMCS_IDT_VECTOR_INFO, &(idt_vec_info.value));
736 check_vmcs_read(VMCS_GUEST_INT_STATE, &(intr_core_state));
738 /* Check for pending exceptions to inject */
739 if (v3_excp_pending(info)) {
740 struct vmx_entry_int_info int_info;
743 // In VMX, almost every exception is hardware
744 // Software exceptions are pretty much only for breakpoint or overflow
746 int_info.vector = v3_get_excp_number(info);
748 if (info->excp_state.excp_error_code_valid) {
749 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, info->excp_state.excp_error_code);
750 int_info.error_code = 1;
752 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
753 V3_Print("Injecting exception %d with error code %x\n",
754 int_info.vector, info->excp_state.excp_error_code);
759 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
760 V3_Print("Injecting exception %d (EIP=%p)\n", int_info.vector, (void *)(addr_t)info->rip);
762 check_vmcs_write(VMCS_ENTRY_INT_INFO, int_info.value);
764 v3_injecting_excp(info, int_info.vector);
766 } else if ((((struct rflags *)&(info->ctrl_regs.rflags))->intr == 1) &&
767 (intr_core_state.val == 0)) {
769 if ((info->intr_core_state.irq_started == 1) && (idt_vec_info.valid == 1)) {
771 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
772 V3_Print("IRQ pending from previous injection\n");
775 // Copy the IDT vectoring info over to reinject the old interrupt
776 if (idt_vec_info.error_code == 1) {
777 uint32_t err_code = 0;
779 check_vmcs_read(VMCS_IDT_VECTOR_ERR, &err_code);
780 check_vmcs_write(VMCS_ENTRY_EXCP_ERR, err_code);
783 idt_vec_info.undef = 0;
784 check_vmcs_write(VMCS_ENTRY_INT_INFO, idt_vec_info.value);
787 struct vmx_entry_int_info ent_int;
790 switch (v3_intr_pending(info)) {
791 case V3_EXTERNAL_IRQ: {
792 info->intr_core_state.irq_vector = v3_get_intr(info);
793 ent_int.vector = info->intr_core_state.irq_vector;
795 ent_int.error_code = 0;
798 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
799 V3_Print("Injecting Interrupt %d at exit %u(EIP=%p)\n",
800 info->intr_core_state.irq_vector,
801 (uint32_t)info->num_exits,
802 (void *)(addr_t)info->rip);
805 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
806 info->intr_core_state.irq_started = 1;
811 PrintDebug("Injecting NMI\n");
816 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
819 case V3_SOFTWARE_INTR:
820 PrintDebug("Injecting software interrupt\n");
824 check_vmcs_write(VMCS_ENTRY_INT_INFO, ent_int.value);
828 // Not sure what to do here, Intel doesn't have virtual IRQs
829 // May be the same as external interrupts/IRQs
832 case V3_INVALID_INTR:
837 } else if ((v3_intr_pending(info)) && (vmx_info->pri_proc_ctrls.int_wndw_exit == 0)) {
838 // Enable INTR window exiting so we know when IF=1
841 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &instr_len);
843 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
844 V3_Print("Enabling Interrupt-Window exiting: %d\n", instr_len);
847 vmx_info->pri_proc_ctrls.int_wndw_exit = 1;
848 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
857 static struct vmx_exit_info exit_log[10];
858 static uint64_t rip_log[10];
862 static void print_exit_log(struct guest_info * info) {
863 int cnt = info->num_exits % 10;
867 V3_Print("\nExit Log (%d total exits):\n", (uint32_t)info->num_exits);
869 for (i = 0; i < 10; i++) {
870 struct vmx_exit_info * tmp = &exit_log[cnt];
872 V3_Print("%d:\texit_reason = %p\n", i, (void *)(addr_t)tmp->exit_reason);
873 V3_Print("\texit_qual = %p\n", (void *)tmp->exit_qual);
874 V3_Print("\tint_info = %p\n", (void *)(addr_t)tmp->int_info);
875 V3_Print("\tint_err = %p\n", (void *)(addr_t)tmp->int_err);
876 V3_Print("\tinstr_info = %p\n", (void *)(addr_t)tmp->instr_info);
877 V3_Print("\tguest_linear_addr= %p\n", (void *)(addr_t)tmp->guest_linear_addr);
878 V3_Print("\tRIP = %p\n", (void *)rip_log[cnt]);
892 v3_vmx_config_tsc_virtualization(struct guest_info * info) {
893 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
895 if (info->time_state.flags & VM_TIME_TRAP_RDTSC) {
896 if (!vmx_info->pri_proc_ctrls.rdtsc_exit) {
897 vmx_info->pri_proc_ctrls.rdtsc_exit = 1;
898 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
902 uint32_t tsc_offset_low, tsc_offset_high;
904 if (vmx_info->pri_proc_ctrls.rdtsc_exit) {
905 vmx_info->pri_proc_ctrls.rdtsc_exit = 0;
906 check_vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
909 if (info->time_state.flags & VM_TIME_TSC_PASSTHROUGH) {
912 tsc_offset = v3_tsc_host_offset(&info->time_state);
914 tsc_offset_high = (uint32_t)(( tsc_offset >> 32) & 0xffffffff);
915 tsc_offset_low = (uint32_t)(tsc_offset & 0xffffffff);
917 check_vmcs_write(VMCS_TSC_OFFSET_HIGH, tsc_offset_high);
918 check_vmcs_write(VMCS_TSC_OFFSET, tsc_offset_low);
924 * CAUTION and DANGER!!!
926 * The VMCS CANNOT(!!) be accessed outside of the cli/sti calls inside this function
927 * When exectuing a symbiotic call, the VMCS WILL be overwritten, so any dependencies
928 * on its contents will cause things to break. The contents at the time of the exit WILL
929 * change before the exit handler is executed.
931 int v3_vmx_enter(struct guest_info * info) {
933 struct vmx_exit_info exit_info;
934 struct vmx_data * vmx_info = (struct vmx_data *)(info->vmm_data);
935 uint64_t guest_cycles = 0;
937 // Conditionally yield the CPU if the timeslice has expired
940 // Update timer devices late after being in the VM so that as much
941 // of the time in the VM is accounted for as possible. Also do it before
942 // updating IRQ entry state so that any interrupts the timers raise get
943 // handled on the next VM entry.
944 v3_advance_time(info, NULL);
945 v3_update_timers(info);
947 // disable global interrupts for vm state transition
950 if (vmcs_store() != vmx_info->vmcs_ptr_phys) {
951 vmcs_clear(vmx_info->vmcs_ptr_phys);
952 vmcs_load(vmx_info->vmcs_ptr_phys);
953 vmx_info->state = VMX_UNLAUNCHED;
956 v3_vmx_restore_vmcs(info);
959 #ifdef V3_CONFIG_SYMCALL
960 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
961 update_irq_entry_state(info);
964 update_irq_entry_state(info);
969 vmcs_read(VMCS_GUEST_CR3, &guest_cr3);
970 vmcs_write(VMCS_GUEST_CR3, guest_cr3);
974 // Perform last-minute time setup prior to entering the VM
975 v3_vmx_config_tsc_virtualization(info);
977 if (v3_update_vmcs_host_state(info)) {
979 PrintError("Could not write host state\n");
983 if (vmx_info->pin_ctrls.active_preempt_timer) {
984 /* Preemption timer is active */
985 uint32_t preempt_window = 0xffffffff;
987 if (info->timeouts.timeout_active) {
988 preempt_window = info->timeouts.next_timeout;
991 check_vmcs_write(VMCS_PREEMPT_TIMER, preempt_window);
996 uint64_t entry_tsc = 0;
997 uint64_t exit_tsc = 0;
999 if (vmx_info->state == VMX_UNLAUNCHED) {
1000 vmx_info->state = VMX_LAUNCHED;
1002 ret = v3_vmx_launch(&(info->vm_regs), info, &(info->ctrl_regs));
1006 V3_ASSERT(vmx_info->state != VMX_UNLAUNCHED);
1008 ret = v3_vmx_resume(&(info->vm_regs), info, &(info->ctrl_regs));
1012 guest_cycles = exit_tsc - entry_tsc;
1015 // PrintDebug("VMX Exit: ret=%d\n", ret);
1017 if (ret != VMX_SUCCESS) {
1019 vmcs_read(VMCS_INSTR_ERR, &error);
1023 PrintError("VMENTRY Error: %d (launch_ret = %d)\n", error, ret);
1030 /* If we have the preemption time, then use it to get more accurate guest time */
1031 if (vmx_info->pin_ctrls.active_preempt_timer) {
1032 uint32_t cycles_left = 0;
1033 check_vmcs_read(VMCS_PREEMPT_TIMER, &(cycles_left));
1035 if (info->timeouts.timeout_active) {
1036 guest_cycles = info->timeouts.next_timeout - cycles_left;
1038 guest_cycles = 0xffffffff - cycles_left;
1042 // Immediate exit from VM time bookkeeping
1043 v3_advance_time(info, &guest_cycles);
1045 /* Update guest state */
1046 v3_vmx_save_vmcs(info);
1048 // info->cpl = info->segments.cs.selector & 0x3;
1050 info->mem_mode = v3_get_vm_mem_mode(info);
1051 info->cpu_mode = v3_get_vm_cpu_mode(info);
1055 check_vmcs_read(VMCS_EXIT_INSTR_LEN, &(exit_info.instr_len));
1056 check_vmcs_read(VMCS_EXIT_INSTR_INFO, &(exit_info.instr_info));
1057 check_vmcs_read(VMCS_EXIT_REASON, &(exit_info.exit_reason));
1058 check_vmcs_read(VMCS_EXIT_QUAL, &(exit_info.exit_qual));
1059 check_vmcs_read(VMCS_EXIT_INT_INFO, &(exit_info.int_info));
1060 check_vmcs_read(VMCS_EXIT_INT_ERR, &(exit_info.int_err));
1061 check_vmcs_read(VMCS_GUEST_LINEAR_ADDR, &(exit_info.guest_linear_addr));
1063 if (info->shdw_pg_mode == NESTED_PAGING) {
1064 check_vmcs_read(VMCS_GUEST_PHYS_ADDR, &(exit_info.ept_fault_addr));
1067 //PrintDebug("VMX Exit taken, id-qual: %u-%lu\n", exit_info.exit_reason, exit_info.exit_qual);
1069 exit_log[info->num_exits % 10] = exit_info;
1070 rip_log[info->num_exits % 10] = get_addr_linear(info, info->rip, &(info->segments.cs));
1072 #ifdef V3_CONFIG_SYMCALL
1073 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
1074 update_irq_exit_state(info);
1077 update_irq_exit_state(info);
1080 if (exit_info.exit_reason == VMX_EXIT_INTR_WINDOW) {
1081 // This is a special case whose only job is to inject an interrupt
1082 vmcs_read(VMCS_PROC_CTRLS, &(vmx_info->pri_proc_ctrls.value));
1083 vmx_info->pri_proc_ctrls.int_wndw_exit = 0;
1084 vmcs_write(VMCS_PROC_CTRLS, vmx_info->pri_proc_ctrls.value);
1086 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
1087 V3_Print("Interrupts available again! (RIP=%llx)\n", info->rip);
1091 // reenable global interrupts after vm exit
1094 // Conditionally yield the CPU if the timeslice has expired
1095 v3_yield_cond(info);
1096 v3_advance_time(info, NULL);
1097 v3_update_timers(info);
1099 if (v3_handle_vmx_exit(info, &exit_info) == -1) {
1100 PrintError("Error in VMX exit handler (Exit reason=%x)\n", exit_info.exit_reason);
1104 if (info->timeouts.timeout_active) {
1105 /* Check to see if any timeouts have expired */
1106 v3_handle_timeouts(info, guest_cycles);
1113 int v3_start_vmx_guest(struct guest_info * info) {
1115 PrintDebug("Starting VMX core %u\n", info->vcpu_id);
1117 if (info->vcpu_id == 0) {
1118 info->core_run_state = CORE_RUNNING;
1121 PrintDebug("VMX core %u: Waiting for core initialization\n", info->vcpu_id);
1123 while (info->core_run_state == CORE_STOPPED) {
1125 if (info->vm_info->run_state == VM_STOPPED) {
1126 // The VM was stopped before this core was initialized.
1131 //PrintDebug("VMX core %u: still waiting for INIT\n",info->vcpu_id);
1134 PrintDebug("VMX core %u initialized\n", info->vcpu_id);
1136 // We'll be paranoid about race conditions here
1137 v3_wait_at_barrier(info);
1141 PrintDebug("VMX core %u: I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
1142 info->vcpu_id, info->segments.cs.selector, (void *)(info->segments.cs.base),
1143 info->segments.cs.limit, (void *)(info->rip));
1146 PrintDebug("VMX core %u: Launching VMX VM on logical core %u\n", info->vcpu_id, info->pcpu_id);
1148 v3_start_time(info);
1152 if (info->vm_info->run_state == VM_STOPPED) {
1153 info->core_run_state = CORE_STOPPED;
1157 if (v3_vmx_enter(info) == -1) {
1160 addr_t linear_addr = 0;
1162 info->vm_info->run_state = VM_ERROR;
1164 V3_Print("VMX core %u: VMX ERROR!!\n", info->vcpu_id);
1166 v3_print_guest_state(info);
1168 V3_Print("VMX core %u\n", info->vcpu_id);
1170 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
1172 if (info->mem_mode == PHYSICAL_MEM) {
1173 v3_gpa_to_hva(info, linear_addr, &host_addr);
1174 } else if (info->mem_mode == VIRTUAL_MEM) {
1175 v3_gva_to_hva(info, linear_addr, &host_addr);
1178 V3_Print("VMX core %u: Host Address of rip = 0x%p\n", info->vcpu_id, (void *)host_addr);
1180 V3_Print("VMX core %u: Instr (15 bytes) at %p:\n", info->vcpu_id, (void *)host_addr);
1181 v3_dump_mem((uint8_t *)host_addr, 15);
1183 v3_print_stack(info);
1187 print_exit_log(info);
1191 v3_wait_at_barrier(info);
1194 if (info->vm_info->run_state == VM_STOPPED) {
1195 info->core_run_state = CORE_STOPPED;
1199 if ((info->num_exits % 5000) == 0) {
1200 V3_Print("VMX Exit number %d\n", (uint32_t)info->num_exits);
1212 #define VMX_FEATURE_CONTROL_MSR 0x0000003a
1213 #define CPUID_VMX_FEATURES 0x00000005 /* LOCK and VMXON */
1214 #define CPUID_1_ECX_VTXFLAG 0x00000020
1216 int v3_is_vmx_capable() {
1217 v3_msr_t feature_msr;
1218 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1220 v3_cpuid(0x1, &eax, &ebx, &ecx, &edx);
1222 PrintDebug("ECX: 0x%x\n", ecx);
1224 if (ecx & CPUID_1_ECX_VTXFLAG) {
1225 v3_get_msr(VMX_FEATURE_CONTROL_MSR, &(feature_msr.hi), &(feature_msr.lo));
1227 PrintDebug("MSRREGlow: 0x%.8x\n", feature_msr.lo);
1229 if ((feature_msr.lo & CPUID_VMX_FEATURES) != CPUID_VMX_FEATURES) {
1230 PrintDebug("VMX is locked -- enable in the BIOS\n");
1235 PrintDebug("VMX not supported on this cpu\n");
1243 int v3_reset_vmx_vm_core(struct guest_info * core, addr_t rip) {
1246 if ((core->shdw_pg_mode == NESTED_PAGING) &&
1247 (v3_mach_type == V3_VMX_EPT_UG_CPU)) {
1250 core->segments.cs.selector = rip << 8;
1251 core->segments.cs.limit = 0xffff;
1252 core->segments.cs.base = rip << 12;
1254 core->vm_regs.rdx = core->vcpu_id;
1255 core->vm_regs.rbx = rip;
1263 void v3_init_vmx_cpu(int cpu_id) {
1264 addr_t vmx_on_region = 0;
1265 extern v3_cpu_arch_t v3_mach_type;
1266 extern v3_cpu_arch_t v3_cpu_types[];
1268 if (v3_mach_type == V3_INVALID_CPU) {
1269 if (v3_init_vmx_hw(&hw_info) == -1) {
1270 PrintError("Could not initialize VMX hardware features on cpu %d\n", cpu_id);
1278 // Setup VMXON Region
1279 vmx_on_region = allocate_vmcs();
1282 if (vmx_on(vmx_on_region) == VMX_SUCCESS) {
1283 V3_Print("VMX Enabled\n");
1284 host_vmcs_ptrs[cpu_id] = vmx_on_region;
1286 V3_Print("VMX already enabled\n");
1287 V3_FreePages((void *)vmx_on_region, 1);
1290 PrintDebug("VMXON pointer: 0x%p\n", (void *)host_vmcs_ptrs[cpu_id]);
1293 struct vmx_sec_proc_ctrls sec_proc_ctrls;
1294 sec_proc_ctrls.value = v3_vmx_get_ctrl_features(&(hw_info.sec_proc_ctrls));
1296 if (sec_proc_ctrls.enable_ept == 0) {
1297 V3_Print("VMX EPT (Nested) Paging not supported\n");
1298 v3_cpu_types[cpu_id] = V3_VMX_CPU;
1299 } else if (sec_proc_ctrls.unrstrct_guest == 0) {
1300 V3_Print("VMX EPT (Nested) Paging supported\n");
1301 v3_cpu_types[cpu_id] = V3_VMX_EPT_CPU;
1303 V3_Print("VMX EPT (Nested) Paging + Unrestricted guest supported\n");
1304 v3_cpu_types[cpu_id] = V3_VMX_EPT_UG_CPU;
1311 void v3_deinit_vmx_cpu(int cpu_id) {
1312 extern v3_cpu_arch_t v3_cpu_types[];
1313 v3_cpu_types[cpu_id] = V3_INVALID_CPU;
1315 if (host_vmcs_ptrs[cpu_id] != 0) {
1316 V3_Print("Disabling VMX\n");
1318 if (vmx_off() != VMX_SUCCESS) {
1319 PrintError("Error executing VMXOFF\n");
1322 V3_FreePages((void *)host_vmcs_ptrs[cpu_id], 1);
1324 host_vmcs_ptrs[cpu_id] = 0;