2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #ifdef __DECODER_TEST__
21 #include "vmm_decoder.h"
23 #include <xed/xed-interface.h>
29 #include <palacios/vmm_decoder.h>
30 #include <palacios/vmm_xed.h>
31 #include <xed/xed-interface.h>
32 #include <palacios/vm_guest.h>
33 #include <palacios/vmm.h>
38 #ifndef CONFIG_DEBUG_DECODER
40 #define PrintDebug(fmt, args...)
46 static uint_t tables_inited = 0;
49 #define GPR_REGISTER 0
50 #define SEGMENT_REGISTER 1
51 #define CTRL_REGISTER 2
52 #define DEBUG_REGISTER 3
56 /* Disgusting mask hack...
57 I can't think right now, so we'll do it this way...
59 static const ullong_t mask_1 = 0x00000000000000ffLL;
60 static const ullong_t mask_2 = 0x000000000000ffffLL;
61 static const ullong_t mask_4 = 0x00000000ffffffffLL;
62 static const ullong_t mask_8 = 0xffffffffffffffffLL;
65 #define MASK(val, length) ({ \
66 ullong_t mask = 0x0LL; \
84 struct memory_operand {
92 uint_t displacement_size;
93 ullong_t displacement;
99 static v3_op_type_t get_opcode(xed_iform_enum_t iform);
101 static int xed_reg_to_v3_reg(struct guest_info * info, xed_reg_enum_t xed_reg, addr_t * v3_reg, uint_t * reg_len);
102 static int get_memory_operand(struct guest_info * info, xed_decoded_inst_t * xed_instr, uint_t index, struct x86_operand * operand);
104 static int set_decoder_mode(struct guest_info * info, xed_state_t * state) {
105 switch (v3_get_vm_cpu_mode(info)) {
107 if (state->mmode != XED_MACHINE_MODE_LEGACY_16) {
108 xed_state_init(state,
109 XED_MACHINE_MODE_LEGACY_16,
110 XED_ADDRESS_WIDTH_16b,
111 XED_ADDRESS_WIDTH_16b);
116 if (state->mmode != XED_MACHINE_MODE_LEGACY_32) {
117 xed_state_init(state,
118 XED_MACHINE_MODE_LEGACY_32,
119 XED_ADDRESS_WIDTH_32b,
120 XED_ADDRESS_WIDTH_32b);
124 if (state->mmode != XED_MACHINE_MODE_LONG_COMPAT_32) {
125 xed_state_init(state,
126 XED_MACHINE_MODE_LONG_COMPAT_32,
127 XED_ADDRESS_WIDTH_32b,
128 XED_ADDRESS_WIDTH_32b);
132 if (state->mmode != XED_MACHINE_MODE_LONG_64) {
133 PrintDebug("Setting decoder to long mode\n");
134 // state->mmode = XED_MACHINE_MODE_LONG_64;
135 //xed_state_set_machine_mode(state, XED_MACHINE_MODE_LONG_64);
136 xed_state_init(state,
137 XED_MACHINE_MODE_LONG_64,
138 XED_ADDRESS_WIDTH_64b,
139 XED_ADDRESS_WIDTH_64b);
143 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
150 static int is_flags_reg(xed_reg_enum_t xed_reg) {
162 int v3_init_decoder(struct guest_info * info) {
163 // Global library initialization, only do it once
164 if (tables_inited == 0) {
169 xed_state_t * decoder_state = (xed_state_t *)V3_Malloc(sizeof(xed_state_t));
170 xed_state_zero(decoder_state);
171 xed_state_init(decoder_state,
172 XED_MACHINE_MODE_LEGACY_32,
173 XED_ADDRESS_WIDTH_32b,
174 XED_ADDRESS_WIDTH_32b);
176 info->decoder_state = decoder_state;
183 int v3_deinit_decoder(struct guest_info * core) {
184 V3_Free(core->decoder_state);
192 static int decode_string_op(struct guest_info * info,
193 xed_decoded_inst_t * xed_instr, const xed_inst_t * xi,
194 struct x86_instr * instr) {
196 PrintDebug("String operation\n");
198 if (instr->op_type == V3_OP_MOVS) {
199 instr->num_operands = 2;
201 if (get_memory_operand(info, xed_instr, 0, &(instr->dst_operand)) == -1) {
202 PrintError("Could not get Destination memory operand\n");
207 if (get_memory_operand(info, xed_instr, 1, &(instr->src_operand)) == -1) {
208 PrintError("Could not get Source memory operand\n");
212 instr->dst_operand.write = 1;
213 instr->src_operand.read = 1;
215 if (instr->prefixes.rep == 1) {
217 uint_t reg_length = 0;
219 xed_reg_to_v3_reg(info, xed_decoded_inst_get_reg(xed_instr, XED_OPERAND_REG0), ®_addr, ®_length);
220 instr->str_op_length = MASK(*(addr_t *)reg_addr, reg_length);
222 instr->str_op_length = 1;
225 } else if (instr->op_type == V3_OP_STOS) {
226 instr->num_operands = 2;
228 if (get_memory_operand(info, xed_instr, 0, &(instr->dst_operand)) == -1) {
229 PrintError("Could not get Destination memory operand\n");
233 // STOS reads from rax
234 xed_reg_to_v3_reg(info, xed_decoded_inst_get_reg(xed_instr, XED_OPERAND_REG0),
235 &(instr->src_operand.operand),
236 &(instr->src_operand.size));
237 instr->src_operand.type = REG_OPERAND;
239 instr->src_operand.read = 1;
240 instr->dst_operand.write = 1;
242 if (instr->prefixes.rep == 1) {
244 uint_t reg_length = 0;
246 xed_reg_to_v3_reg(info, xed_decoded_inst_get_reg(xed_instr, XED_OPERAND_REG1),
247 ®_addr, ®_length);
248 instr->str_op_length = MASK(*(addr_t *)reg_addr, reg_length);
250 instr->str_op_length = 1;
254 PrintError("Unhandled String OP\n");
263 int v3_disasm(struct guest_info * info, void *instr_ptr, addr_t * rip, int mark) {
267 xed_decoded_inst_t xed_instr;
268 xed_error_enum_t xed_error;
270 /* disassemble the specified instruction */
271 if (set_decoder_mode(info, info->decoder_state) == -1) {
272 PrintError("Could not set decoder mode\n");
276 xed_decoded_inst_zero_set_mode(&xed_instr, info->decoder_state);
278 xed_error = xed_decode(&xed_instr,
279 REINTERPRET_CAST(const xed_uint8_t *, instr_ptr),
280 XED_MAX_INSTRUCTION_BYTES);
282 if (xed_error != XED_ERROR_NONE) {
283 PrintError("Xed error: %s\n", xed_error_enum_t2str(xed_error));
287 /* obtain string representation in AT&T syntax */
288 if (!xed_format_att(&xed_instr, buffer, sizeof(buffer), *rip)) {
289 PrintError("Xed error: cannot disaaemble\n");
293 /* print address, opcode bytes and the disassembled instruction */
294 length = xed_decoded_inst_get_length(&xed_instr);
295 V3_Print("0x%p %c ", (void *) *rip, mark ? '*' : ' ');
296 for (i = 0; i < length; i++) {
297 unsigned char b = ((unsigned char *) instr_ptr)[i];
298 V3_Print("%x%x ", b >> 4, b & 0xf);
303 V3_Print("%s\n", buffer);
305 /* move on to next instruction */
312 int v3_decode(struct guest_info * info, addr_t instr_ptr, struct x86_instr * instr) {
313 xed_decoded_inst_t xed_instr;
314 xed_error_enum_t xed_error;
317 v3_get_prefixes((uchar_t *)instr_ptr, &(instr->prefixes));
319 if (set_decoder_mode(info, info->decoder_state) == -1) {
320 PrintError("Could not set decoder mode\n");
324 xed_decoded_inst_zero_set_mode(&xed_instr, info->decoder_state);
326 xed_error = xed_decode(&xed_instr,
327 REINTERPRET_CAST(const xed_uint8_t *, instr_ptr),
328 XED_MAX_INSTRUCTION_BYTES);
331 if (xed_error != XED_ERROR_NONE) {
332 PrintError("Xed error: %s\n", xed_error_enum_t2str(xed_error));
336 const xed_inst_t * xi = xed_decoded_inst_inst(&xed_instr);
338 instr->instr_length = xed_decoded_inst_get_length(&xed_instr);
341 xed_iform_enum_t iform = xed_decoded_inst_get_iform_enum(&xed_instr);
343 #ifdef CONFIG_DEBUG_DECODER
344 xed_iclass_enum_t iclass = xed_decoded_inst_get_iclass(&xed_instr);
346 PrintDebug("iform=%s, iclass=%s\n", xed_iform_enum_t2str(iform), xed_iclass_enum_t2str(iclass));
350 if ((instr->op_type = get_opcode(iform)) == V3_INVALID_OP) {
351 PrintError("Could not get opcode. (iform=%s)\n", xed_iform_enum_t2str(iform));
356 // We special case the string operations...
357 if (xed_decoded_inst_get_category(&xed_instr) == XED_CATEGORY_STRINGOP) {
358 instr->is_str_op = 1;
359 return decode_string_op(info, &xed_instr, xi, instr);
361 instr->is_str_op = 0;
362 instr->str_op_length = 0;
365 instr->num_operands = xed_decoded_inst_noperands(&xed_instr);
368 if (instr->num_operands > 3) {
369 PrintDebug("Special Case Not Handled (more than 3 operands) (iform=%s)\n", xed_iform_enum_t2str(iform)
372 } else if (instr->num_operands == 3) {
373 const xed_operand_t * op = xed_inst_operand(xi, 2);
374 xed_operand_enum_t op_enum = xed_operand_name(op);
376 if ((!xed_operand_is_register(op_enum)) ||
377 (!is_flags_reg(xed_decoded_inst_get_reg(&xed_instr, op_enum)))) {
379 PrintError("Special Case not handled (iform=%s)\n", xed_iform_enum_t2str(iform));
385 //PrintDebug("Number of operands: %d\n", instr->num_operands);
386 //PrintDebug("INSTR length: %d\n", instr->instr_length);
389 if (instr->num_operands >= 1) {
390 const xed_operand_t * op = xed_inst_operand(xi, 0);
391 xed_operand_enum_t op_enum = xed_operand_name(op);
393 struct x86_operand * v3_op = NULL;
396 if (xed_operand_written(op)) {
397 v3_op = &(instr->dst_operand);
399 v3_op = &(instr->src_operand);
403 v3_op = &(instr->dst_operand);
405 if (xed_operand_is_register(op_enum)) {
406 xed_reg_enum_t xed_reg = xed_decoded_inst_get_reg(&xed_instr, op_enum);
407 int v3_reg_type = xed_reg_to_v3_reg(info,
412 if (v3_reg_type == -1) {
413 PrintError("First operand is an Unhandled Operand: %s\n", xed_reg_enum_t2str(xed_reg));
414 v3_op->type = INVALID_OPERAND;
416 } else if (v3_reg_type == SEGMENT_REGISTER) {
417 struct v3_segment * seg_reg = (struct v3_segment *)(v3_op->operand);
418 v3_op->operand = (addr_t)&(seg_reg->selector);
421 v3_op->type = REG_OPERAND;
426 case XED_OPERAND_MEM0:
428 PrintDebug("Memory operand (1)\n");
429 if (get_memory_operand(info, &xed_instr, 0, v3_op) == -1) {
430 PrintError("Could not get first memory operand\n");
436 case XED_OPERAND_MEM1:
437 case XED_OPERAND_IMM1:
439 PrintError("Illegal Operand Order\n");
443 case XED_OPERAND_IMM0:
444 case XED_OPERAND_AGEN:
445 case XED_OPERAND_PTR:
446 case XED_OPERAND_RELBR:
448 PrintError("Unhandled Operand Type\n");
453 V3_Print("Operand 0 mode: %s\n", xed_operand_action_enum_t2str(xed_operand_rw(op)));
456 if (xed_operand_read(op)) {
460 if (xed_operand_written(op)) {
466 // set second operand
467 if (instr->num_operands >= 2) {
468 const xed_operand_t * op = xed_inst_operand(xi, 1);
469 // xed_operand_type_enum_t op_type = xed_operand_type(op);
470 xed_operand_enum_t op_enum = xed_operand_name(op);
472 struct x86_operand * v3_op;
475 if (xed_operand_written(op)) {
476 v3_op = &(instr->dst_operand);
478 v3_op = &(instr->src_operand);
481 v3_op = &(instr->src_operand);
484 if (xed_operand_is_register(op_enum)) {
485 xed_reg_enum_t xed_reg = xed_decoded_inst_get_reg(&xed_instr, op_enum);
486 int v3_reg_type = xed_reg_to_v3_reg(info,
490 if (v3_reg_type == -1) {
491 PrintError("Second operand is an Unhandled Operand: %s\n", xed_reg_enum_t2str(xed_reg));
492 v3_op->type = INVALID_OPERAND;
494 } else if (v3_reg_type == SEGMENT_REGISTER) {
495 struct v3_segment * seg_reg = (struct v3_segment *)(v3_op->operand);
496 v3_op->operand = (addr_t)&(seg_reg->selector);
499 v3_op->type = REG_OPERAND;
503 case XED_OPERAND_MEM0:
505 PrintDebug("Memory operand (2)\n");
506 if (get_memory_operand(info, &xed_instr, 0, v3_op) == -1) {
507 PrintError("Could not get first memory operand\n");
513 case XED_OPERAND_IMM0:
515 instr->src_operand.size = xed_decoded_inst_get_immediate_width(&xed_instr);
517 if (instr->src_operand.size > 4) {
518 PrintError("Unhandled 64 bit immediates\n");
521 instr->src_operand.operand = xed_decoded_inst_get_unsigned_immediate(&xed_instr);
523 instr->src_operand.type = IMM_OPERAND;
528 case XED_OPERAND_MEM1:
529 case XED_OPERAND_IMM1:
531 PrintError("Illegal Operand Order\n");
534 case XED_OPERAND_AGEN:
535 case XED_OPERAND_PTR:
536 case XED_OPERAND_RELBR:
538 PrintError("Unhandled Operand Type\n");
543 V3_Print("Operand 1 mode: %s\n", xed_operand_action_enum_t2str(xed_operand_rw(op)));
545 if (xed_operand_read(op)) {
549 if (xed_operand_written(op)) {
556 if (instr->num_operands >= 3) {
557 const xed_operand_t * op = xed_inst_operand(xi, 2);
558 xed_operand_type_enum_t op_type = xed_operand_type(op);
559 xed_operand_enum_t op_enum = xed_operand_name(op);
563 if (xed_operand_is_register(op_enum)) {
564 xed_reg_enum_t xed_reg = xed_decoded_inst_get_reg(&xed_instr, op_enum);
565 int v3_reg_type = xed_reg_to_v3_reg(info,
567 &(instr->third_operand.operand),
568 &(instr->third_operand.size));
570 if (v3_reg_type == -1) {
571 PrintError("Third operand is an Unhandled Operand: %s\n", xed_reg_enum_t2str(xed_reg));
572 instr->third_operand.type = INVALID_OPERAND;
574 } else if (v3_reg_type == SEGMENT_REGISTER) {
575 struct v3_segment * seg_reg = (struct v3_segment *)(instr->third_operand.operand);
576 instr->third_operand.operand = (addr_t)&(seg_reg->selector);
580 instr->third_operand.type = REG_OPERAND;
582 PrintDebug("Operand 3 mode: %s\n", xed_operand_action_enum_t2str(xed_operand_rw(op)));
585 if (xed_operand_read(op)) {
586 instr->third_operand.read = 1;
589 if (xed_operand_written(op)) {
590 instr->third_operand.write = 1;
594 PrintError("Unhandled third operand type %s\n", xed_operand_type_enum_t2str(op_type));
595 instr->num_operands = 2;
603 int v3_encode(struct guest_info * info, struct x86_instr * instr, uint8_t * instr_buf) {
612 static int get_memory_operand(struct guest_info * info, xed_decoded_inst_t * xed_instr, uint_t op_index, struct x86_operand * operand) {
613 struct memory_operand mem_op;
619 ullong_t displacement;
620 int addr_width = v3_get_addr_width(info);
621 v3_cpu_mode_t cpu_mode = v3_get_vm_cpu_mode(info);
622 // struct v3_segment * seg_reg;
624 PrintDebug("Xed mode = %s\n", xed_machine_mode_enum_t2str(xed_state_get_machine_mode(info->decoder_state)));
625 PrintDebug("Address width: %s\n",
626 xed_address_width_enum_t2str(xed_state_get_address_width(info->decoder_state)));
627 PrintDebug("Stack Address width: %s\n",
628 xed_address_width_enum_t2str(xed_state_get_stack_address_width(info->decoder_state)));
632 memset((void*)&mem_op, '\0', sizeof(struct memory_operand));
634 xed_reg_enum_t xed_seg = xed_decoded_inst_get_seg_reg(xed_instr, op_index);
635 if (xed_seg != XED_REG_INVALID) {
636 struct v3_segment *tmp_segment;
637 if (xed_reg_to_v3_reg(info, xed_seg, (addr_t *)&tmp_segment, &(mem_op.segment_size)) == -1) {
638 PrintError("Unhandled Segment Register\n");
641 mem_op.segment = tmp_segment->base;
644 xed_reg_enum_t xed_base = xed_decoded_inst_get_base_reg(xed_instr, op_index);
645 if (xed_base != XED_REG_INVALID) {
647 if (xed_reg_to_v3_reg(info, xed_base, &base_reg, &(mem_op.base_size)) == -1) {
648 PrintError("Unhandled Base register\n");
651 mem_op.base = *(addr_t *)base_reg;
656 xed_reg_enum_t xed_idx = xed_decoded_inst_get_index_reg(xed_instr, op_index);
657 if ((op_index == 0) && (xed_idx != XED_REG_INVALID)) {
660 if (xed_reg_to_v3_reg(info, xed_idx, &index_reg, &(mem_op.index_size)) == -1) {
661 PrintError("Unhandled Index Register\n");
665 mem_op.index= *(addr_t *)index_reg;
667 xed_uint_t xed_scale = xed_decoded_inst_get_scale(xed_instr, op_index);
668 if (xed_scale != 0) {
669 mem_op.scale = xed_scale;
674 xed_uint_t disp_bits = xed_decoded_inst_get_memory_displacement_width(xed_instr, op_index);
676 xed_int64_t xed_disp = xed_decoded_inst_get_memory_displacement(xed_instr, op_index);
678 mem_op.displacement_size = disp_bits;
679 mem_op.displacement = xed_disp;
682 operand->type = MEM_OPERAND;
683 operand->size = xed_decoded_inst_get_memory_operand_length(xed_instr, op_index);
687 PrintDebug("Struct: Seg=%p (size=%d), base=%p, index=%p, scale=%p, displacement=%p (size=%d)\n",
688 (void *)mem_op.segment, mem_op.segment_size, (void*)mem_op.base, (void *)mem_op.index,
689 (void *)mem_op.scale, (void *)(addr_t)mem_op.displacement, mem_op.displacement_size);
692 PrintDebug("operand size: %d\n", operand->size);
694 seg = MASK(mem_op.segment, mem_op.segment_size);
695 base = MASK(mem_op.base, mem_op.base_size);
696 index = MASK(mem_op.index, mem_op.index_size);
697 scale = mem_op.scale;
699 // XED returns the displacement as a 2s complement signed number, but it can
700 // have different sizes, depending on the instruction encoding.
701 // we put that into a 64 bit unsigned (the unsigned doesn't matter since
702 // we only ever do 2s complement arithmetic on it. However, this means we
703 // need to sign-extend what XED provides through 64 bits.
704 displacement = mem_op.displacement;
705 displacement <<= 64 - mem_op.displacement_size * 8;
706 displacement = ((sllong_t)displacement) >> (64 - mem_op.displacement_size * 8);
709 PrintDebug("Seg=%p, base=%p, index=%p, scale=%p, displacement=%p\n",
710 (void *)seg, (void *)base, (void *)index, (void *)scale, (void *)(addr_t)displacement);
712 if (cpu_mode == REAL) {
713 operand->operand = seg + MASK((base + (scale * index) + displacement), addr_width);
715 operand->operand = MASK((seg + base + (scale * index) + displacement), addr_width);
722 static int xed_reg_to_v3_reg(struct guest_info * info, xed_reg_enum_t xed_reg,
723 addr_t * v3_reg, uint_t * reg_len) {
725 PrintDebug("Xed Register: %s\n", xed_reg_enum_t2str(xed_reg));
728 case XED_REG_INVALID:
737 *v3_reg = (addr_t)&(info->vm_regs.rax);
741 *v3_reg = (addr_t)&(info->vm_regs.rax);
745 *v3_reg = (addr_t)&(info->vm_regs.rax);
749 *v3_reg = (addr_t)(&(info->vm_regs.rax)) + 1;
753 *v3_reg = (addr_t)&(info->vm_regs.rax);
758 *v3_reg = (addr_t)&(info->vm_regs.rcx);
762 *v3_reg = (addr_t)&(info->vm_regs.rcx);
766 *v3_reg = (addr_t)&(info->vm_regs.rcx);
770 *v3_reg = (addr_t)(&(info->vm_regs.rcx)) + 1;
774 *v3_reg = (addr_t)&(info->vm_regs.rcx);
779 *v3_reg = (addr_t)&(info->vm_regs.rdx);
783 *v3_reg = (addr_t)&(info->vm_regs.rdx);
787 *v3_reg = (addr_t)&(info->vm_regs.rdx);
791 *v3_reg = (addr_t)(&(info->vm_regs.rdx)) + 1;
795 *v3_reg = (addr_t)&(info->vm_regs.rdx);
800 *v3_reg = (addr_t)&(info->vm_regs.rbx);
804 *v3_reg = (addr_t)&(info->vm_regs.rbx);
808 *v3_reg = (addr_t)&(info->vm_regs.rbx);
812 *v3_reg = (addr_t)(&(info->vm_regs.rbx)) + 1;
816 *v3_reg = (addr_t)&(info->vm_regs.rbx);
822 *v3_reg = (addr_t)&(info->vm_regs.rsp);
826 *v3_reg = (addr_t)&(info->vm_regs.rsp);
830 *v3_reg = (addr_t)&(info->vm_regs.rsp);
834 *v3_reg = (addr_t)&(info->vm_regs.rsp);
839 *v3_reg = (addr_t)&(info->vm_regs.rbp);
843 *v3_reg = (addr_t)&(info->vm_regs.rbp);
847 *v3_reg = (addr_t)&(info->vm_regs.rbp);
851 *v3_reg = (addr_t)&(info->vm_regs.rbp);
858 *v3_reg = (addr_t)&(info->vm_regs.rsi);
862 *v3_reg = (addr_t)&(info->vm_regs.rsi);
866 *v3_reg = (addr_t)&(info->vm_regs.rsi);
870 *v3_reg = (addr_t)&(info->vm_regs.rsi);
876 *v3_reg = (addr_t)&(info->vm_regs.rdi);
880 *v3_reg = (addr_t)&(info->vm_regs.rdi);
884 *v3_reg = (addr_t)&(info->vm_regs.rdi);
888 *v3_reg = (addr_t)&(info->vm_regs.rdi);
897 *v3_reg = (addr_t)&(info->vm_regs.r8);
901 *v3_reg = (addr_t)&(info->vm_regs.r8);
905 *v3_reg = (addr_t)&(info->vm_regs.r8);
909 *v3_reg = (addr_t)&(info->vm_regs.r8);
914 *v3_reg = (addr_t)&(info->vm_regs.r9);
918 *v3_reg = (addr_t)&(info->vm_regs.r9);
922 *v3_reg = (addr_t)&(info->vm_regs.r9);
926 *v3_reg = (addr_t)&(info->vm_regs.r9);
931 *v3_reg = (addr_t)&(info->vm_regs.r10);
935 *v3_reg = (addr_t)&(info->vm_regs.r10);
939 *v3_reg = (addr_t)&(info->vm_regs.r10);
943 *v3_reg = (addr_t)&(info->vm_regs.r10);
948 *v3_reg = (addr_t)&(info->vm_regs.r11);
952 *v3_reg = (addr_t)&(info->vm_regs.r11);
956 *v3_reg = (addr_t)&(info->vm_regs.r11);
960 *v3_reg = (addr_t)&(info->vm_regs.r11);
965 *v3_reg = (addr_t)&(info->vm_regs.r12);
969 *v3_reg = (addr_t)&(info->vm_regs.r12);
973 *v3_reg = (addr_t)&(info->vm_regs.r12);
977 *v3_reg = (addr_t)&(info->vm_regs.r12);
982 *v3_reg = (addr_t)&(info->vm_regs.r13);
986 *v3_reg = (addr_t)&(info->vm_regs.r13);
990 *v3_reg = (addr_t)&(info->vm_regs.r13);
994 *v3_reg = (addr_t)&(info->vm_regs.r13);
999 *v3_reg = (addr_t)&(info->vm_regs.r14);
1001 return GPR_REGISTER;
1003 *v3_reg = (addr_t)&(info->vm_regs.r14);
1005 return GPR_REGISTER;
1007 *v3_reg = (addr_t)&(info->vm_regs.r14);
1009 return GPR_REGISTER;
1011 *v3_reg = (addr_t)&(info->vm_regs.r14);
1013 return GPR_REGISTER;
1016 *v3_reg = (addr_t)&(info->vm_regs.r15);
1018 return GPR_REGISTER;
1020 *v3_reg = (addr_t)&(info->vm_regs.r15);
1022 return GPR_REGISTER;
1024 *v3_reg = (addr_t)&(info->vm_regs.r15);
1026 return GPR_REGISTER;
1028 *v3_reg = (addr_t)&(info->vm_regs.r15);
1030 return GPR_REGISTER;
1037 *v3_reg = (addr_t)&(info->rip);
1039 return CTRL_REGISTER;
1041 *v3_reg = (addr_t)&(info->rip);
1043 return CTRL_REGISTER;
1045 *v3_reg = (addr_t)&(info->rip);
1047 return CTRL_REGISTER;
1050 *v3_reg = (addr_t)&(info->ctrl_regs.rflags);
1052 return CTRL_REGISTER;
1053 case XED_REG_EFLAGS:
1054 *v3_reg = (addr_t)&(info->ctrl_regs.rflags);
1056 return CTRL_REGISTER;
1057 case XED_REG_RFLAGS:
1058 *v3_reg = (addr_t)&(info->ctrl_regs.rflags);
1060 return CTRL_REGISTER;
1063 *v3_reg = (addr_t)&(info->ctrl_regs.cr0);
1065 return CTRL_REGISTER;
1067 *v3_reg = (addr_t)&(info->ctrl_regs.cr2);
1069 return CTRL_REGISTER;
1071 *v3_reg = (addr_t)&(info->ctrl_regs.cr3);
1073 return CTRL_REGISTER;
1075 *v3_reg = (addr_t)&(info->ctrl_regs.cr4);
1077 return CTRL_REGISTER;
1079 *v3_reg = (addr_t)&(info->ctrl_regs.cr8);
1081 return CTRL_REGISTER;
1103 *v3_reg = (addr_t)&(info->segments.cs);
1105 return SEGMENT_REGISTER;
1107 *v3_reg = (addr_t)&(info->segments.ds);
1109 return SEGMENT_REGISTER;
1111 *v3_reg = (addr_t)&(info->segments.es);
1113 return SEGMENT_REGISTER;
1115 *v3_reg = (addr_t)&(info->segments.ss);
1117 return SEGMENT_REGISTER;
1119 *v3_reg = (addr_t)&(info->segments.fs);
1121 return SEGMENT_REGISTER;
1123 *v3_reg = (addr_t)&(info->segments.gs);
1125 return SEGMENT_REGISTER;
1132 PrintError("Segment selector operand... Don't know how to handle this...\n");
1197 case XED_REG_STACKPUSH:
1198 case XED_REG_STACKPOP:
1201 case XED_REG_TSCAUX:
1204 case XED_REG_X87CONTROL:
1205 case XED_REG_X87STATUS:
1206 case XED_REG_X87TOP:
1207 case XED_REG_X87TAG:
1208 case XED_REG_X87PUSH:
1209 case XED_REG_X87POP:
1210 case XED_REG_X87POP2:
1245 static v3_op_type_t get_opcode(xed_iform_enum_t iform) {
1249 /* Control Instructions */
1251 case XED_IFORM_MOV_CR_GPR64_CR:
1252 case XED_IFORM_MOV_CR_GPR32_CR:
1253 return V3_OP_MOVCR2;
1255 case XED_IFORM_MOV_CR_CR_GPR64:
1256 case XED_IFORM_MOV_CR_CR_GPR32:
1257 return V3_OP_MOV2CR;
1259 case XED_IFORM_SMSW_GPRv:
1262 case XED_IFORM_LMSW_GPR16:
1265 case XED_IFORM_CLTS:
1268 case XED_IFORM_INVLPG_MEMb:
1269 return V3_OP_INVLPG;
1272 /* Data Instructions */
1275 case XED_IFORM_ADC_MEMv_GPRv:
1276 case XED_IFORM_ADC_MEMv_IMM:
1277 case XED_IFORM_ADC_MEMb_GPR8:
1278 case XED_IFORM_ADC_MEMb_IMM:
1280 case XED_IFORM_ADC_GPRv_MEMv:
1281 case XED_IFORM_ADC_GPR8_MEMb:
1285 case XED_IFORM_ADD_MEMv_GPRv:
1286 case XED_IFORM_ADD_MEMb_IMM:
1287 case XED_IFORM_ADD_MEMb_GPR8:
1288 case XED_IFORM_ADD_MEMv_IMM:
1290 case XED_IFORM_ADD_GPRv_MEMv:
1291 case XED_IFORM_ADD_GPR8_MEMb:
1295 case XED_IFORM_AND_MEMv_IMM:
1296 case XED_IFORM_AND_MEMb_GPR8:
1297 case XED_IFORM_AND_MEMv_GPRv:
1298 case XED_IFORM_AND_MEMb_IMM:
1300 case XED_IFORM_AND_GPR8_MEMb:
1301 case XED_IFORM_AND_GPRv_MEMv:
1305 case XED_IFORM_SUB_MEMv_IMM:
1306 case XED_IFORM_SUB_MEMb_GPR8:
1307 case XED_IFORM_SUB_MEMb_IMM:
1308 case XED_IFORM_SUB_MEMv_GPRv:
1310 case XED_IFORM_SUB_GPR8_MEMb:
1311 case XED_IFORM_SUB_GPRv_MEMv:
1315 case XED_IFORM_MOV_MEMv_GPRv:
1316 case XED_IFORM_MOV_MEMb_GPR8:
1317 case XED_IFORM_MOV_MEMv_OrAX:
1318 case XED_IFORM_MOV_MEMb_AL:
1319 case XED_IFORM_MOV_MEMv_IMM:
1320 case XED_IFORM_MOV_MEMb_IMM:
1322 case XED_IFORM_MOV_GPRv_MEMv:
1323 case XED_IFORM_MOV_GPR8_MEMb:
1324 case XED_IFORM_MOV_OrAX_MEMv:
1325 case XED_IFORM_MOV_AL_MEMb:
1330 case XED_IFORM_MOVZX_GPRv_MEMb:
1331 case XED_IFORM_MOVZX_GPRv_MEMw:
1335 case XED_IFORM_MOVSX_GPRv_MEMb:
1336 case XED_IFORM_MOVSX_GPRv_MEMw:
1341 case XED_IFORM_DEC_MEMv:
1342 case XED_IFORM_DEC_MEMb:
1345 case XED_IFORM_INC_MEMb:
1346 case XED_IFORM_INC_MEMv:
1350 case XED_IFORM_OR_MEMv_IMM:
1351 case XED_IFORM_OR_MEMb_IMM:
1352 case XED_IFORM_OR_MEMv_GPRv:
1353 case XED_IFORM_OR_MEMb_GPR8:
1355 case XED_IFORM_OR_GPRv_MEMv:
1356 case XED_IFORM_OR_GPR8_MEMb:
1360 case XED_IFORM_XOR_MEMv_GPRv:
1361 case XED_IFORM_XOR_MEMb_IMM:
1362 case XED_IFORM_XOR_MEMb_GPR8:
1363 case XED_IFORM_XOR_MEMv_IMM:
1365 case XED_IFORM_XOR_GPRv_MEMv:
1366 case XED_IFORM_XOR_GPR8_MEMb:
1369 case XED_IFORM_NEG_MEMb:
1370 case XED_IFORM_NEG_MEMv:
1373 case XED_IFORM_NOT_MEMv:
1374 case XED_IFORM_NOT_MEMb:
1377 case XED_IFORM_XCHG_MEMv_GPRv:
1378 case XED_IFORM_XCHG_MEMb_GPR8:
1381 case XED_IFORM_SETB_MEMb:
1384 case XED_IFORM_SETBE_MEMb:
1387 case XED_IFORM_SETL_MEMb:
1390 case XED_IFORM_SETLE_MEMb:
1393 case XED_IFORM_SETNB_MEMb:
1396 case XED_IFORM_SETNBE_MEMb:
1397 return V3_OP_SETNBE;
1399 case XED_IFORM_SETNL_MEMb:
1402 case XED_IFORM_SETNLE_MEMb:
1403 return V3_OP_SETNLE;
1405 case XED_IFORM_SETNO_MEMb:
1408 case XED_IFORM_SETNP_MEMb:
1411 case XED_IFORM_SETNS_MEMb:
1414 case XED_IFORM_SETNZ_MEMb:
1417 case XED_IFORM_SETO_MEMb:
1420 case XED_IFORM_SETP_MEMb:
1423 case XED_IFORM_SETS_MEMb:
1426 case XED_IFORM_SETZ_MEMb:
1429 case XED_IFORM_MOVSB:
1430 case XED_IFORM_MOVSW:
1431 case XED_IFORM_MOVSD:
1432 case XED_IFORM_MOVSQ:
1435 case XED_IFORM_STOSB:
1436 case XED_IFORM_STOSW:
1437 case XED_IFORM_STOSD:
1438 case XED_IFORM_STOSQ:
1443 return V3_INVALID_OP;