2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #ifdef __DECODER_TEST__
21 #include "vmm_decoder.h"
23 #include <xed/xed-interface.h>
29 #include <palacios/vmm_decoder.h>
30 #include <palacios/vmm_xed.h>
31 #include <xed/xed-interface.h>
32 #include <palacios/vm_guest.h>
33 #include <palacios/vmm.h>
38 #ifndef CONFIG_DEBUG_XED
40 #define PrintDebug(fmt, args...)
46 static uint_t tables_inited = 0;
49 #define GPR_REGISTER 0
50 #define SEGMENT_REGISTER 1
51 #define CTRL_REGISTER 2
52 #define DEBUG_REGISTER 3
56 /* Disgusting mask hack...
57 I can't think right now, so we'll do it this way...
59 static const ullong_t mask_1 = 0x00000000000000ffLL;
60 static const ullong_t mask_2 = 0x000000000000ffffLL;
61 static const ullong_t mask_4 = 0x00000000ffffffffLL;
62 static const ullong_t mask_8 = 0xffffffffffffffffLL;
65 #define MASK(val, length) ({ \
66 ullong_t mask = 0x0LL; \
84 struct memory_operand {
92 uint_t displacement_size;
93 ullong_t displacement;
99 static v3_op_type_t get_opcode(xed_iform_enum_t iform);
101 static int xed_reg_to_v3_reg(struct guest_info * info, xed_reg_enum_t xed_reg, addr_t * v3_reg, uint_t * reg_len);
102 static int get_memory_operand(struct guest_info * info, xed_decoded_inst_t * xed_instr, uint_t index, struct x86_operand * operand);
104 static int set_decoder_mode(struct guest_info * info, xed_state_t * state) {
105 switch (v3_get_vm_cpu_mode(info)) {
107 if (state->mmode != XED_MACHINE_MODE_LEGACY_16) {
108 xed_state_init(state,
109 XED_MACHINE_MODE_LEGACY_16,
110 XED_ADDRESS_WIDTH_16b,
111 XED_ADDRESS_WIDTH_16b);
116 if (state->mmode != XED_MACHINE_MODE_LEGACY_32) {
117 xed_state_init(state,
118 XED_MACHINE_MODE_LEGACY_32,
119 XED_ADDRESS_WIDTH_32b,
120 XED_ADDRESS_WIDTH_32b);
124 if (state->mmode != XED_MACHINE_MODE_LONG_COMPAT_32) {
125 xed_state_init(state,
126 XED_MACHINE_MODE_LONG_COMPAT_32,
127 XED_ADDRESS_WIDTH_32b,
128 XED_ADDRESS_WIDTH_32b);
132 if (state->mmode != XED_MACHINE_MODE_LONG_64) {
133 PrintDebug("Setting decoder to long mode\n");
134 // state->mmode = XED_MACHINE_MODE_LONG_64;
135 //xed_state_set_machine_mode(state, XED_MACHINE_MODE_LONG_64);
136 xed_state_init(state,
137 XED_MACHINE_MODE_LONG_64,
138 XED_ADDRESS_WIDTH_64b,
139 XED_ADDRESS_WIDTH_64b);
143 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
150 static int is_flags_reg(xed_reg_enum_t xed_reg) {
162 int v3_init_decoder(struct guest_info * info) {
163 // Global library initialization, only do it once
164 if (tables_inited == 0) {
169 xed_state_t * decoder_state = (xed_state_t *)V3_Malloc(sizeof(xed_state_t));
170 xed_state_zero(decoder_state);
171 xed_state_init(decoder_state,
172 XED_MACHINE_MODE_LEGACY_32,
173 XED_ADDRESS_WIDTH_32b,
174 XED_ADDRESS_WIDTH_32b);
176 info->decoder_state = decoder_state;
183 int v3_deinit_decoder(struct guest_info * core) {
184 V3_Free(core->decoder_state);
190 int v3_basic_mem_decode(struct guest_info * info, addr_t instr_ptr, struct basic_instr_info * instr_info) {
191 xed_decoded_inst_t xed_instr;
192 xed_error_enum_t xed_error;
195 if (set_decoder_mode(info, info->decoder_state) == -1) {
196 PrintError("Could not set decoder mode\n");
201 xed_decoded_inst_zero_set_mode(&xed_instr, info->decoder_state);
203 xed_error = xed_decode(&xed_instr,
204 REINTERPRET_CAST(const xed_uint8_t *, instr_ptr),
205 XED_MAX_INSTRUCTION_BYTES);
207 if (xed_error != XED_ERROR_NONE) {
208 PrintError("Xed error: %s\n", xed_error_enum_t2str(xed_error));
212 instr_info->instr_length = xed_decoded_inst_get_length(&xed_instr);
215 if (xed_decoded_inst_number_of_memory_operands(&xed_instr) == 0) {
216 PrintError("Tried to decode memory operation with no memory operands\n");
220 instr_info->op_size = xed_decoded_inst_get_memory_operand_length(&xed_instr, 0);
223 xed_category_enum_t cat = xed_decoded_inst_get_category(&xed_instr);
224 if (cat == XED_CATEGORY_STRINGOP) {
225 instr_info->str_op = 1;
227 instr_info->str_op = 0;
230 xed_operand_values_t * operands = xed_decoded_inst_operands(&xed_instr);
231 if (xed_operand_values_has_real_rep(operands)) {
232 instr_info->has_rep = 1;
234 instr_info->has_rep = 0;
241 static int decode_string_op(struct guest_info * info,
242 xed_decoded_inst_t * xed_instr, const xed_inst_t * xi,
243 struct x86_instr * instr) {
245 PrintDebug("String operation\n");
247 if (instr->op_type == V3_OP_MOVS) {
248 instr->num_operands = 2;
250 if (get_memory_operand(info, xed_instr, 0, &(instr->dst_operand)) == -1) {
251 PrintError("Could not get Destination memory operand\n");
255 if (get_memory_operand(info, xed_instr, 1, &(instr->src_operand)) == -1) {
256 PrintError("Could not get Source memory operand\n");
260 if (instr->prefixes.rep == 1) {
262 uint_t reg_length = 0;
264 xed_reg_to_v3_reg(info, xed_decoded_inst_get_reg(xed_instr, XED_OPERAND_REG0), ®_addr, ®_length);
265 instr->str_op_length = MASK(*(addr_t *)reg_addr, reg_length);
267 instr->str_op_length = 1;
270 } else if (instr->op_type == V3_OP_STOS) {
271 instr->num_operands = 2;
273 if (get_memory_operand(info, xed_instr, 0, &(instr->dst_operand)) == -1) {
274 PrintError("Could not get Destination memory operand\n");
278 // STOS reads from rax
279 xed_reg_to_v3_reg(info, xed_decoded_inst_get_reg(xed_instr, XED_OPERAND_REG0),
280 &(instr->src_operand.operand),
281 &(instr->src_operand.size));
282 instr->src_operand.type = REG_OPERAND;
284 if (instr->prefixes.rep == 1) {
286 uint_t reg_length = 0;
288 xed_reg_to_v3_reg(info, xed_decoded_inst_get_reg(xed_instr, XED_OPERAND_REG1), ®_addr, ®_length);
289 instr->str_op_length = MASK(*(addr_t *)reg_addr, reg_length);
291 instr->str_op_length = 1;
295 PrintError("Unhandled String OP\n");
304 int v3_disasm(struct guest_info * info, void *instr_ptr, addr_t * rip, int mark) {
308 xed_decoded_inst_t xed_instr;
309 xed_error_enum_t xed_error;
311 /* disassemble the specified instruction */
312 if (set_decoder_mode(info, info->decoder_state) == -1) {
313 PrintError("Could not set decoder mode\n");
317 xed_decoded_inst_zero_set_mode(&xed_instr, info->decoder_state);
319 xed_error = xed_decode(&xed_instr,
320 REINTERPRET_CAST(const xed_uint8_t *, instr_ptr),
321 XED_MAX_INSTRUCTION_BYTES);
323 if (xed_error != XED_ERROR_NONE) {
324 PrintError("Xed error: %s\n", xed_error_enum_t2str(xed_error));
328 /* obtain string representation in AT&T syntax */
329 if (!xed_format_att(&xed_instr, buffer, sizeof(buffer), *rip)) {
330 PrintError("Xed error: cannot disaaemble\n");
334 /* print address, opcode bytes and the disassembled instruction */
335 length = xed_decoded_inst_get_length(&xed_instr);
336 V3_Print("0x%p %c ", (void *) *rip, mark ? '*' : ' ');
337 for (i = 0; i < length; i++) {
338 unsigned char b = ((unsigned char *) instr_ptr)[i];
339 V3_Print("%x%x ", b >> 4, b & 0xf);
344 V3_Print("%s\n", buffer);
346 /* move on to next instruction */
353 int v3_decode(struct guest_info * info, addr_t instr_ptr, struct x86_instr * instr) {
354 xed_decoded_inst_t xed_instr;
355 xed_error_enum_t xed_error;
358 v3_get_prefixes((uchar_t *)instr_ptr, &(instr->prefixes));
360 if (set_decoder_mode(info, info->decoder_state) == -1) {
361 PrintError("Could not set decoder mode\n");
365 xed_decoded_inst_zero_set_mode(&xed_instr, info->decoder_state);
367 xed_error = xed_decode(&xed_instr,
368 REINTERPRET_CAST(const xed_uint8_t *, instr_ptr),
369 XED_MAX_INSTRUCTION_BYTES);
372 if (xed_error != XED_ERROR_NONE) {
373 PrintError("Xed error: %s\n", xed_error_enum_t2str(xed_error));
377 const xed_inst_t * xi = xed_decoded_inst_inst(&xed_instr);
379 instr->instr_length = xed_decoded_inst_get_length(&xed_instr);
382 xed_iform_enum_t iform = xed_decoded_inst_get_iform_enum(&xed_instr);
384 #ifdef CONFIG_DEBUG_XED
385 xed_iclass_enum_t iclass = xed_decoded_inst_get_iclass(&xed_instr);
387 PrintDebug("iform=%s, iclass=%s\n", xed_iform_enum_t2str(iform), xed_iclass_enum_t2str(iclass));
391 if ((instr->op_type = get_opcode(iform)) == V3_INVALID_OP) {
392 PrintError("Could not get opcode. (iform=%s)\n", xed_iform_enum_t2str(iform));
397 // We special case the string operations...
398 if (xed_decoded_inst_get_category(&xed_instr) == XED_CATEGORY_STRINGOP) {
399 instr->is_str_op = 1;
400 return decode_string_op(info, &xed_instr, xi, instr);
402 instr->is_str_op = 0;
403 instr->str_op_length = 0;
406 instr->num_operands = xed_decoded_inst_noperands(&xed_instr);
409 if (instr->num_operands > 3) {
410 PrintDebug("Special Case Not Handled (more than 3 operands) (iform=%s)\n", xed_iform_enum_t2str(iform)
413 } else if (instr->num_operands == 3) {
414 const xed_operand_t * op = xed_inst_operand(xi, 2);
415 xed_operand_enum_t op_enum = xed_operand_name(op);
417 if ((!xed_operand_is_register(op_enum)) ||
418 (!is_flags_reg(xed_decoded_inst_get_reg(&xed_instr, op_enum)))) {
420 PrintError("Special Case not handled (iform=%s)\n", xed_iform_enum_t2str(iform));
426 //PrintDebug("Number of operands: %d\n", instr->num_operands);
427 //PrintDebug("INSTR length: %d\n", instr->instr_length);
430 if (instr->num_operands >= 1) {
431 const xed_operand_t * op = xed_inst_operand(xi, 0);
432 xed_operand_enum_t op_enum = xed_operand_name(op);
434 struct x86_operand * v3_op = NULL;
437 if (xed_operand_written(op)) {
438 v3_op = &(instr->dst_operand);
440 v3_op = &(instr->src_operand);
444 v3_op = &(instr->dst_operand);
446 if (xed_operand_is_register(op_enum)) {
447 xed_reg_enum_t xed_reg = xed_decoded_inst_get_reg(&xed_instr, op_enum);
448 int v3_reg_type = xed_reg_to_v3_reg(info,
453 if (v3_reg_type == -1) {
454 PrintError("First operand is an Unhandled Operand: %s\n", xed_reg_enum_t2str(xed_reg));
455 v3_op->type = INVALID_OPERAND;
457 } else if (v3_reg_type == SEGMENT_REGISTER) {
458 struct v3_segment * seg_reg = (struct v3_segment *)(v3_op->operand);
459 v3_op->operand = (addr_t)&(seg_reg->selector);
462 v3_op->type = REG_OPERAND;
467 case XED_OPERAND_MEM0:
469 PrintDebug("Memory operand (1)\n");
470 if (get_memory_operand(info, &xed_instr, 0, v3_op) == -1) {
471 PrintError("Could not get first memory operand\n");
477 case XED_OPERAND_MEM1:
478 case XED_OPERAND_IMM1:
480 PrintError("Illegal Operand Order\n");
484 case XED_OPERAND_IMM0:
485 case XED_OPERAND_AGEN:
486 case XED_OPERAND_PTR:
487 case XED_OPERAND_RELBR:
489 PrintError("Unhandled Operand Type\n");
495 // set second operand
496 if (instr->num_operands >= 2) {
497 const xed_operand_t * op = xed_inst_operand(xi, 1);
498 // xed_operand_type_enum_t op_type = xed_operand_type(op);
499 xed_operand_enum_t op_enum = xed_operand_name(op);
501 struct x86_operand * v3_op;
504 if (xed_operand_written(op)) {
505 v3_op = &(instr->dst_operand);
507 v3_op = &(instr->src_operand);
510 v3_op = &(instr->src_operand);
512 if (xed_operand_is_register(op_enum)) {
513 xed_reg_enum_t xed_reg = xed_decoded_inst_get_reg(&xed_instr, op_enum);
514 int v3_reg_type = xed_reg_to_v3_reg(info,
518 if (v3_reg_type == -1) {
519 PrintError("Second operand is an Unhandled Operand: %s\n", xed_reg_enum_t2str(xed_reg));
520 v3_op->type = INVALID_OPERAND;
522 } else if (v3_reg_type == SEGMENT_REGISTER) {
523 struct v3_segment * seg_reg = (struct v3_segment *)(v3_op->operand);
524 v3_op->operand = (addr_t)&(seg_reg->selector);
527 v3_op->type = REG_OPERAND;
531 case XED_OPERAND_MEM0:
533 PrintDebug("Memory operand (2)\n");
534 if (get_memory_operand(info, &xed_instr, 0, v3_op) == -1) {
535 PrintError("Could not get first memory operand\n");
541 case XED_OPERAND_IMM0:
543 instr->src_operand.size = xed_decoded_inst_get_immediate_width(&xed_instr);
545 if (instr->src_operand.size > 4) {
546 PrintError("Unhandled 64 bit immediates\n");
549 instr->src_operand.operand = xed_decoded_inst_get_unsigned_immediate(&xed_instr);
551 instr->src_operand.type = IMM_OPERAND;
556 case XED_OPERAND_MEM1:
557 case XED_OPERAND_IMM1:
559 PrintError("Illegal Operand Order\n");
562 case XED_OPERAND_AGEN:
563 case XED_OPERAND_PTR:
564 case XED_OPERAND_RELBR:
566 PrintError("Unhandled Operand Type\n");
573 if (instr->num_operands >= 3) {
574 const xed_operand_t * op = xed_inst_operand(xi, 2);
575 xed_operand_type_enum_t op_type = xed_operand_type(op);
576 xed_operand_enum_t op_enum = xed_operand_name(op);
578 if (xed_operand_is_register(op_enum)) {
579 xed_reg_enum_t xed_reg = xed_decoded_inst_get_reg(&xed_instr, op_enum);
580 int v3_reg_type = xed_reg_to_v3_reg(info,
582 &(instr->third_operand.operand),
583 &(instr->third_operand.size));
585 if (v3_reg_type == -1) {
586 PrintError("Third operand is an Unhandled Operand: %s\n", xed_reg_enum_t2str(xed_reg));
587 instr->third_operand.type = INVALID_OPERAND;
589 } else if (v3_reg_type == SEGMENT_REGISTER) {
590 struct v3_segment * seg_reg = (struct v3_segment *)(instr->third_operand.operand);
591 instr->third_operand.operand = (addr_t)&(seg_reg->selector);
595 instr->third_operand.type = REG_OPERAND;
598 PrintError("Unhandled third operand type %s\n", xed_operand_type_enum_t2str(op_type));
599 instr->num_operands = 2;
607 int v3_encode(struct guest_info * info, struct x86_instr * instr, char * instr_buf) {
616 static int get_memory_operand(struct guest_info * info, xed_decoded_inst_t * xed_instr, uint_t op_index, struct x86_operand * operand) {
617 struct memory_operand mem_op;
623 ullong_t displacement;
624 int addr_width = v3_get_addr_width(info);
625 v3_cpu_mode_t cpu_mode = v3_get_vm_cpu_mode(info);
626 // struct v3_segment * seg_reg;
628 PrintDebug("Xed mode = %s\n", xed_machine_mode_enum_t2str(xed_state_get_machine_mode(info->decoder_state)));
629 PrintDebug("Address width: %s\n",
630 xed_address_width_enum_t2str(xed_state_get_address_width(info->decoder_state)));
631 PrintDebug("Stack Address width: %s\n",
632 xed_address_width_enum_t2str(xed_state_get_stack_address_width(info->decoder_state)));
636 memset((void*)&mem_op, '\0', sizeof(struct memory_operand));
638 xed_reg_enum_t xed_seg = xed_decoded_inst_get_seg_reg(xed_instr, op_index);
639 if (xed_seg != XED_REG_INVALID) {
640 struct v3_segment *tmp_segment;
641 if (xed_reg_to_v3_reg(info, xed_seg, (addr_t *)&tmp_segment, &(mem_op.segment_size)) == -1) {
642 PrintError("Unhandled Segment Register\n");
645 mem_op.segment = tmp_segment->base;
648 xed_reg_enum_t xed_base = xed_decoded_inst_get_base_reg(xed_instr, op_index);
649 if (xed_base != XED_REG_INVALID) {
651 if (xed_reg_to_v3_reg(info, xed_base, &base_reg, &(mem_op.base_size)) == -1) {
652 PrintError("Unhandled Base register\n");
655 mem_op.base = *(addr_t *)base_reg;
660 xed_reg_enum_t xed_idx = xed_decoded_inst_get_index_reg(xed_instr, op_index);
661 if ((op_index == 0) && (xed_idx != XED_REG_INVALID)) {
664 if (xed_reg_to_v3_reg(info, xed_idx, &index_reg, &(mem_op.index_size)) == -1) {
665 PrintError("Unhandled Index Register\n");
669 mem_op.index= *(addr_t *)index_reg;
671 xed_uint_t xed_scale = xed_decoded_inst_get_scale(xed_instr, op_index);
672 if (xed_scale != 0) {
673 mem_op.scale = xed_scale;
678 xed_uint_t disp_bits = xed_decoded_inst_get_memory_displacement_width(xed_instr, op_index);
680 xed_int64_t xed_disp = xed_decoded_inst_get_memory_displacement(xed_instr, op_index);
682 mem_op.displacement_size = disp_bits;
683 mem_op.displacement = xed_disp;
686 operand->type = MEM_OPERAND;
687 operand->size = xed_decoded_inst_get_memory_operand_length(xed_instr, op_index);
691 PrintDebug("Struct: Seg=%p (size=%d), base=%p, index=%p, scale=%p, displacement=%p (size=%d)\n",
692 (void *)mem_op.segment, mem_op.segment_size, (void*)mem_op.base, (void *)mem_op.index,
693 (void *)mem_op.scale, (void *)(addr_t)mem_op.displacement, mem_op.displacement_size);
696 PrintDebug("operand size: %d\n", operand->size);
698 seg = MASK(mem_op.segment, mem_op.segment_size);
699 base = MASK(mem_op.base, mem_op.base_size);
700 index = MASK(mem_op.index, mem_op.index_size);
701 scale = mem_op.scale;
703 // XED returns the displacement as a 2s complement signed number, but it can
704 // have different sizes, depending on the instruction encoding.
705 // we put that into a 64 bit unsigned (the unsigned doesn't matter since
706 // we only ever do 2s complement arithmetic on it. However, this means we
707 // need to sign-extend what XED provides through 64 bits.
708 displacement = mem_op.displacement;
709 displacement <<= 64 - mem_op.displacement_size * 8;
710 displacement = ((sllong_t)displacement) >> (64 - mem_op.displacement_size * 8);
713 PrintDebug("Seg=%p, base=%p, index=%p, scale=%p, displacement=%p\n",
714 (void *)seg, (void *)base, (void *)index, (void *)scale, (void *)(addr_t)displacement);
716 if (cpu_mode == REAL) {
717 operand->operand = seg + MASK((base + (scale * index) + displacement), addr_width);
719 operand->operand = MASK((seg + base + (scale * index) + displacement), addr_width);
726 static int xed_reg_to_v3_reg(struct guest_info * info, xed_reg_enum_t xed_reg, addr_t * v3_reg, uint_t * reg_len) {
728 PrintDebug("Xed Register: %s\n", xed_reg_enum_t2str(xed_reg));
731 case XED_REG_INVALID:
740 *v3_reg = (addr_t)&(info->vm_regs.rax);
744 *v3_reg = (addr_t)&(info->vm_regs.rax);
748 *v3_reg = (addr_t)&(info->vm_regs.rax);
752 *v3_reg = (addr_t)(&(info->vm_regs.rax)) + 1;
756 *v3_reg = (addr_t)&(info->vm_regs.rax);
761 *v3_reg = (addr_t)&(info->vm_regs.rcx);
765 *v3_reg = (addr_t)&(info->vm_regs.rcx);
769 *v3_reg = (addr_t)&(info->vm_regs.rcx);
773 *v3_reg = (addr_t)(&(info->vm_regs.rcx)) + 1;
777 *v3_reg = (addr_t)&(info->vm_regs.rcx);
782 *v3_reg = (addr_t)&(info->vm_regs.rdx);
786 *v3_reg = (addr_t)&(info->vm_regs.rdx);
790 *v3_reg = (addr_t)&(info->vm_regs.rdx);
794 *v3_reg = (addr_t)(&(info->vm_regs.rdx)) + 1;
798 *v3_reg = (addr_t)&(info->vm_regs.rdx);
803 *v3_reg = (addr_t)&(info->vm_regs.rbx);
807 *v3_reg = (addr_t)&(info->vm_regs.rbx);
811 *v3_reg = (addr_t)&(info->vm_regs.rbx);
815 *v3_reg = (addr_t)(&(info->vm_regs.rbx)) + 1;
819 *v3_reg = (addr_t)&(info->vm_regs.rbx);
825 *v3_reg = (addr_t)&(info->vm_regs.rsp);
829 *v3_reg = (addr_t)&(info->vm_regs.rsp);
833 *v3_reg = (addr_t)&(info->vm_regs.rsp);
837 *v3_reg = (addr_t)&(info->vm_regs.rsp);
842 *v3_reg = (addr_t)&(info->vm_regs.rbp);
846 *v3_reg = (addr_t)&(info->vm_regs.rbp);
850 *v3_reg = (addr_t)&(info->vm_regs.rbp);
854 *v3_reg = (addr_t)&(info->vm_regs.rbp);
861 *v3_reg = (addr_t)&(info->vm_regs.rsi);
865 *v3_reg = (addr_t)&(info->vm_regs.rsi);
869 *v3_reg = (addr_t)&(info->vm_regs.rsi);
873 *v3_reg = (addr_t)&(info->vm_regs.rsi);
879 *v3_reg = (addr_t)&(info->vm_regs.rdi);
883 *v3_reg = (addr_t)&(info->vm_regs.rdi);
887 *v3_reg = (addr_t)&(info->vm_regs.rdi);
891 *v3_reg = (addr_t)&(info->vm_regs.rdi);
900 *v3_reg = (addr_t)&(info->vm_regs.r8);
904 *v3_reg = (addr_t)&(info->vm_regs.r8);
908 *v3_reg = (addr_t)&(info->vm_regs.r8);
912 *v3_reg = (addr_t)&(info->vm_regs.r8);
917 *v3_reg = (addr_t)&(info->vm_regs.r9);
921 *v3_reg = (addr_t)&(info->vm_regs.r9);
925 *v3_reg = (addr_t)&(info->vm_regs.r9);
929 *v3_reg = (addr_t)&(info->vm_regs.r9);
934 *v3_reg = (addr_t)&(info->vm_regs.r10);
938 *v3_reg = (addr_t)&(info->vm_regs.r10);
942 *v3_reg = (addr_t)&(info->vm_regs.r10);
946 *v3_reg = (addr_t)&(info->vm_regs.r10);
951 *v3_reg = (addr_t)&(info->vm_regs.r11);
955 *v3_reg = (addr_t)&(info->vm_regs.r11);
959 *v3_reg = (addr_t)&(info->vm_regs.r11);
963 *v3_reg = (addr_t)&(info->vm_regs.r11);
968 *v3_reg = (addr_t)&(info->vm_regs.r12);
972 *v3_reg = (addr_t)&(info->vm_regs.r12);
976 *v3_reg = (addr_t)&(info->vm_regs.r12);
980 *v3_reg = (addr_t)&(info->vm_regs.r12);
985 *v3_reg = (addr_t)&(info->vm_regs.r13);
989 *v3_reg = (addr_t)&(info->vm_regs.r13);
993 *v3_reg = (addr_t)&(info->vm_regs.r13);
997 *v3_reg = (addr_t)&(info->vm_regs.r13);
1002 *v3_reg = (addr_t)&(info->vm_regs.r14);
1004 return GPR_REGISTER;
1006 *v3_reg = (addr_t)&(info->vm_regs.r14);
1008 return GPR_REGISTER;
1010 *v3_reg = (addr_t)&(info->vm_regs.r14);
1012 return GPR_REGISTER;
1014 *v3_reg = (addr_t)&(info->vm_regs.r14);
1016 return GPR_REGISTER;
1019 *v3_reg = (addr_t)&(info->vm_regs.r15);
1021 return GPR_REGISTER;
1023 *v3_reg = (addr_t)&(info->vm_regs.r15);
1025 return GPR_REGISTER;
1027 *v3_reg = (addr_t)&(info->vm_regs.r15);
1029 return GPR_REGISTER;
1031 *v3_reg = (addr_t)&(info->vm_regs.r15);
1033 return GPR_REGISTER;
1040 *v3_reg = (addr_t)&(info->rip);
1042 return CTRL_REGISTER;
1044 *v3_reg = (addr_t)&(info->rip);
1046 return CTRL_REGISTER;
1048 *v3_reg = (addr_t)&(info->rip);
1050 return CTRL_REGISTER;
1053 *v3_reg = (addr_t)&(info->ctrl_regs.rflags);
1055 return CTRL_REGISTER;
1056 case XED_REG_EFLAGS:
1057 *v3_reg = (addr_t)&(info->ctrl_regs.rflags);
1059 return CTRL_REGISTER;
1060 case XED_REG_RFLAGS:
1061 *v3_reg = (addr_t)&(info->ctrl_regs.rflags);
1063 return CTRL_REGISTER;
1066 *v3_reg = (addr_t)&(info->ctrl_regs.cr0);
1068 return CTRL_REGISTER;
1070 *v3_reg = (addr_t)&(info->ctrl_regs.cr2);
1072 return CTRL_REGISTER;
1074 *v3_reg = (addr_t)&(info->ctrl_regs.cr3);
1076 return CTRL_REGISTER;
1078 *v3_reg = (addr_t)&(info->ctrl_regs.cr4);
1080 return CTRL_REGISTER;
1082 *v3_reg = (addr_t)&(info->ctrl_regs.cr8);
1084 return CTRL_REGISTER;
1106 *v3_reg = (addr_t)&(info->segments.cs);
1108 return SEGMENT_REGISTER;
1110 *v3_reg = (addr_t)&(info->segments.ds);
1112 return SEGMENT_REGISTER;
1114 *v3_reg = (addr_t)&(info->segments.es);
1116 return SEGMENT_REGISTER;
1118 *v3_reg = (addr_t)&(info->segments.ss);
1120 return SEGMENT_REGISTER;
1122 *v3_reg = (addr_t)&(info->segments.fs);
1124 return SEGMENT_REGISTER;
1126 *v3_reg = (addr_t)&(info->segments.gs);
1128 return SEGMENT_REGISTER;
1135 PrintError("Segment selector operand... Don't know how to handle this...\n");
1200 case XED_REG_STACKPUSH:
1201 case XED_REG_STACKPOP:
1204 case XED_REG_TSCAUX:
1207 case XED_REG_X87CONTROL:
1208 case XED_REG_X87STATUS:
1209 case XED_REG_X87TOP:
1210 case XED_REG_X87TAG:
1211 case XED_REG_X87PUSH:
1212 case XED_REG_X87POP:
1213 case XED_REG_X87POP2:
1248 static v3_op_type_t get_opcode(xed_iform_enum_t iform) {
1252 /* Control Instructions */
1254 case XED_IFORM_MOV_CR_GPR64_CR:
1255 case XED_IFORM_MOV_CR_GPR32_CR:
1256 return V3_OP_MOVCR2;
1258 case XED_IFORM_MOV_CR_CR_GPR64:
1259 case XED_IFORM_MOV_CR_CR_GPR32:
1260 return V3_OP_MOV2CR;
1262 case XED_IFORM_SMSW_GPRv:
1265 case XED_IFORM_LMSW_GPR16:
1268 case XED_IFORM_CLTS:
1271 case XED_IFORM_INVLPG_MEMb:
1272 return V3_OP_INVLPG;
1275 /* Data Instructions */
1278 case XED_IFORM_ADC_MEMv_GPRv:
1279 case XED_IFORM_ADC_MEMv_IMM:
1280 case XED_IFORM_ADC_MEMb_GPR8:
1281 case XED_IFORM_ADC_MEMb_IMM:
1283 case XED_IFORM_ADC_GPRv_MEMv:
1284 case XED_IFORM_ADC_GPR8_MEMb:
1288 case XED_IFORM_ADD_MEMv_GPRv:
1289 case XED_IFORM_ADD_MEMb_IMM:
1290 case XED_IFORM_ADD_MEMb_GPR8:
1291 case XED_IFORM_ADD_MEMv_IMM:
1293 case XED_IFORM_ADD_GPRv_MEMv:
1294 case XED_IFORM_ADD_GPR8_MEMb:
1298 case XED_IFORM_AND_MEMv_IMM:
1299 case XED_IFORM_AND_MEMb_GPR8:
1300 case XED_IFORM_AND_MEMv_GPRv:
1301 case XED_IFORM_AND_MEMb_IMM:
1303 case XED_IFORM_AND_GPR8_MEMb:
1304 case XED_IFORM_AND_GPRv_MEMv:
1308 case XED_IFORM_SUB_MEMv_IMM:
1309 case XED_IFORM_SUB_MEMb_GPR8:
1310 case XED_IFORM_SUB_MEMb_IMM:
1311 case XED_IFORM_SUB_MEMv_GPRv:
1313 case XED_IFORM_SUB_GPR8_MEMb:
1314 case XED_IFORM_SUB_GPRv_MEMv:
1318 case XED_IFORM_MOV_MEMv_GPRv:
1319 case XED_IFORM_MOV_MEMb_GPR8:
1320 case XED_IFORM_MOV_MEMv_OrAX:
1321 case XED_IFORM_MOV_MEMb_AL:
1322 case XED_IFORM_MOV_MEMv_IMM:
1323 case XED_IFORM_MOV_MEMb_IMM:
1325 case XED_IFORM_MOV_GPRv_MEMv:
1326 case XED_IFORM_MOV_GPR8_MEMb:
1327 case XED_IFORM_MOV_OrAX_MEMv:
1328 case XED_IFORM_MOV_AL_MEMb:
1333 case XED_IFORM_MOVZX_GPRv_MEMb:
1334 case XED_IFORM_MOVZX_GPRv_MEMw:
1338 case XED_IFORM_MOVSX_GPRv_MEMb:
1339 case XED_IFORM_MOVSX_GPRv_MEMw:
1344 case XED_IFORM_DEC_MEMv:
1345 case XED_IFORM_DEC_MEMb:
1348 case XED_IFORM_INC_MEMb:
1349 case XED_IFORM_INC_MEMv:
1353 case XED_IFORM_OR_MEMv_IMM:
1354 case XED_IFORM_OR_MEMb_IMM:
1355 case XED_IFORM_OR_MEMv_GPRv:
1356 case XED_IFORM_OR_MEMb_GPR8:
1358 case XED_IFORM_OR_GPRv_MEMv:
1359 case XED_IFORM_OR_GPR8_MEMb:
1363 case XED_IFORM_XOR_MEMv_GPRv:
1364 case XED_IFORM_XOR_MEMb_IMM:
1365 case XED_IFORM_XOR_MEMb_GPR8:
1366 case XED_IFORM_XOR_MEMv_IMM:
1368 case XED_IFORM_XOR_GPRv_MEMv:
1369 case XED_IFORM_XOR_GPR8_MEMb:
1372 case XED_IFORM_NEG_MEMb:
1373 case XED_IFORM_NEG_MEMv:
1376 case XED_IFORM_NOT_MEMv:
1377 case XED_IFORM_NOT_MEMb:
1380 case XED_IFORM_XCHG_MEMv_GPRv:
1381 case XED_IFORM_XCHG_MEMb_GPR8:
1384 case XED_IFORM_SETB_MEMb:
1387 case XED_IFORM_SETBE_MEMb:
1390 case XED_IFORM_SETL_MEMb:
1393 case XED_IFORM_SETLE_MEMb:
1396 case XED_IFORM_SETNB_MEMb:
1399 case XED_IFORM_SETNBE_MEMb:
1400 return V3_OP_SETNBE;
1402 case XED_IFORM_SETNL_MEMb:
1405 case XED_IFORM_SETNLE_MEMb:
1406 return V3_OP_SETNLE;
1408 case XED_IFORM_SETNO_MEMb:
1411 case XED_IFORM_SETNP_MEMb:
1414 case XED_IFORM_SETNS_MEMb:
1417 case XED_IFORM_SETNZ_MEMb:
1420 case XED_IFORM_SETO_MEMb:
1423 case XED_IFORM_SETP_MEMb:
1426 case XED_IFORM_SETS_MEMb:
1429 case XED_IFORM_SETZ_MEMb:
1432 case XED_IFORM_MOVSB:
1433 case XED_IFORM_MOVSW:
1434 case XED_IFORM_MOVSD:
1435 case XED_IFORM_MOVSQ:
1438 case XED_IFORM_STOSB:
1439 case XED_IFORM_STOSW:
1440 case XED_IFORM_STOSD:
1441 case XED_IFORM_STOSQ:
1446 return V3_INVALID_OP;