2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #ifdef __DECODER_TEST__
21 #include "vmm_decoder.h"
23 #include <xed/xed-interface.h>
29 #include <palacios/vmm_decoder.h>
30 #include <palacios/vmm_xed.h>
31 #include <xed/xed-interface.h>
32 #include <palacios/vm_guest.h>
33 #include <palacios/vmm.h>
38 #ifndef CONFIG_DEBUG_DECODER
40 #define PrintDebug(fmt, args...)
46 static uint_t tables_inited = 0;
49 #define GPR_REGISTER 0
50 #define SEGMENT_REGISTER 1
51 #define CTRL_REGISTER 2
52 #define DEBUG_REGISTER 3
56 /* Disgusting mask hack...
57 I can't think right now, so we'll do it this way...
59 static const ullong_t mask_1 = 0x00000000000000ffLL;
60 static const ullong_t mask_2 = 0x000000000000ffffLL;
61 static const ullong_t mask_4 = 0x00000000ffffffffLL;
62 static const ullong_t mask_8 = 0xffffffffffffffffLL;
65 #define MASK(val, length) ({ \
66 ullong_t mask = 0x0LL; \
84 struct memory_operand {
92 uint_t displacement_size;
93 ullong_t displacement;
99 static v3_op_type_t get_opcode(xed_iform_enum_t iform);
101 static int xed_reg_to_v3_reg(struct guest_info * info, xed_reg_enum_t xed_reg, addr_t * v3_reg, uint_t * reg_len);
102 static int get_memory_operand(struct guest_info * info, xed_decoded_inst_t * xed_instr, uint_t index, struct x86_operand * operand);
104 static int set_decoder_mode(struct guest_info * info, xed_state_t * state) {
105 switch (v3_get_vm_cpu_mode(info)) {
107 if (state->mmode != XED_MACHINE_MODE_LEGACY_16) {
108 xed_state_init(state,
109 XED_MACHINE_MODE_LEGACY_16,
110 XED_ADDRESS_WIDTH_16b,
111 XED_ADDRESS_WIDTH_16b);
116 if (state->mmode != XED_MACHINE_MODE_LEGACY_32) {
117 xed_state_init(state,
118 XED_MACHINE_MODE_LEGACY_32,
119 XED_ADDRESS_WIDTH_32b,
120 XED_ADDRESS_WIDTH_32b);
124 if (state->mmode != XED_MACHINE_MODE_LONG_COMPAT_32) {
125 xed_state_init(state,
126 XED_MACHINE_MODE_LONG_COMPAT_32,
127 XED_ADDRESS_WIDTH_32b,
128 XED_ADDRESS_WIDTH_32b);
132 if (state->mmode != XED_MACHINE_MODE_LONG_64) {
133 PrintDebug("Setting decoder to long mode\n");
134 // state->mmode = XED_MACHINE_MODE_LONG_64;
135 //xed_state_set_machine_mode(state, XED_MACHINE_MODE_LONG_64);
136 xed_state_init(state,
137 XED_MACHINE_MODE_LONG_64,
138 XED_ADDRESS_WIDTH_64b,
139 XED_ADDRESS_WIDTH_64b);
143 PrintError("Unsupported CPU mode: %d\n", info->cpu_mode);
150 static int is_flags_reg(xed_reg_enum_t xed_reg) {
162 int v3_init_decoder(struct guest_info * info) {
163 // Global library initialization, only do it once
164 if (tables_inited == 0) {
169 xed_state_t * decoder_state = (xed_state_t *)V3_Malloc(sizeof(xed_state_t));
170 xed_state_zero(decoder_state);
171 xed_state_init(decoder_state,
172 XED_MACHINE_MODE_LEGACY_32,
173 XED_ADDRESS_WIDTH_32b,
174 XED_ADDRESS_WIDTH_32b);
176 info->decoder_state = decoder_state;
183 int v3_deinit_decoder(struct guest_info * core) {
184 V3_Free(core->decoder_state);
192 static int decode_string_op(struct guest_info * info,
193 xed_decoded_inst_t * xed_instr, const xed_inst_t * xi,
194 struct x86_instr * instr) {
196 PrintDebug("String operation\n");
198 if (instr->op_type == V3_OP_MOVS) {
199 instr->num_operands = 2;
201 if (get_memory_operand(info, xed_instr, 0, &(instr->dst_operand)) == -1) {
202 PrintError("Could not get Destination memory operand\n");
207 if (get_memory_operand(info, xed_instr, 1, &(instr->src_operand)) == -1) {
208 PrintError("Could not get Source memory operand\n");
212 instr->dst_operand.write = 1;
213 instr->src_operand.read = 1;
215 if (instr->prefixes.rep == 1) {
217 uint_t reg_length = 0;
219 xed_reg_to_v3_reg(info, xed_decoded_inst_get_reg(xed_instr, XED_OPERAND_REG0), ®_addr, ®_length);
220 instr->str_op_length = MASK(*(addr_t *)reg_addr, reg_length);
222 instr->str_op_length = 1;
225 } else if (instr->op_type == V3_OP_STOS) {
226 instr->num_operands = 2;
228 if (get_memory_operand(info, xed_instr, 0, &(instr->dst_operand)) == -1) {
229 PrintError("Could not get Destination memory operand\n");
233 // STOS reads from rax
234 xed_reg_to_v3_reg(info, xed_decoded_inst_get_reg(xed_instr, XED_OPERAND_REG0),
235 &(instr->src_operand.operand),
236 &(instr->src_operand.size));
237 instr->src_operand.type = REG_OPERAND;
239 instr->src_operand.read = 1;
240 instr->dst_operand.write = 1;
242 if (instr->prefixes.rep == 1) {
244 uint_t reg_length = 0;
246 xed_reg_to_v3_reg(info, xed_decoded_inst_get_reg(xed_instr, XED_OPERAND_REG1),
247 ®_addr, ®_length);
248 instr->str_op_length = MASK(*(addr_t *)reg_addr, reg_length);
250 instr->str_op_length = 1;
254 PrintError("Unhandled String OP\n");
263 int v3_disasm(struct guest_info * info, void *instr_ptr, addr_t * rip, int mark) {
267 xed_decoded_inst_t xed_instr;
268 xed_error_enum_t xed_error;
270 /* disassemble the specified instruction */
271 if (set_decoder_mode(info, info->decoder_state) == -1) {
272 PrintError("Could not set decoder mode\n");
276 xed_decoded_inst_zero_set_mode(&xed_instr, info->decoder_state);
278 xed_error = xed_decode(&xed_instr,
279 REINTERPRET_CAST(const xed_uint8_t *, instr_ptr),
280 XED_MAX_INSTRUCTION_BYTES);
282 if (xed_error != XED_ERROR_NONE) {
283 PrintError("Xed error: %s\n", xed_error_enum_t2str(xed_error));
287 /* obtain string representation in AT&T syntax */
288 if (!xed_format_att(&xed_instr, buffer, sizeof(buffer), *rip)) {
289 PrintError("Xed error: cannot disaaemble\n");
293 /* print address, opcode bytes and the disassembled instruction */
294 length = xed_decoded_inst_get_length(&xed_instr);
295 V3_Print("0x%p %c ", (void *) *rip, mark ? '*' : ' ');
296 for (i = 0; i < length; i++) {
297 unsigned char b = ((unsigned char *) instr_ptr)[i];
298 V3_Print("%x%x ", b >> 4, b & 0xf);
303 V3_Print("%s\n", buffer);
305 /* move on to next instruction */
312 int v3_decode(struct guest_info * info, addr_t instr_ptr, struct x86_instr * instr) {
313 xed_decoded_inst_t xed_instr;
314 xed_error_enum_t xed_error;
317 v3_get_prefixes((uchar_t *)instr_ptr, &(instr->prefixes));
319 if (set_decoder_mode(info, info->decoder_state) == -1) {
320 PrintError("Could not set decoder mode\n");
324 xed_decoded_inst_zero_set_mode(&xed_instr, info->decoder_state);
326 xed_error = xed_decode(&xed_instr,
327 REINTERPRET_CAST(const xed_uint8_t *, instr_ptr),
328 XED_MAX_INSTRUCTION_BYTES);
331 if (xed_error != XED_ERROR_NONE) {
332 PrintError("Xed error: %s\n", xed_error_enum_t2str(xed_error));
336 const xed_inst_t * xi = xed_decoded_inst_inst(&xed_instr);
338 instr->instr_length = xed_decoded_inst_get_length(&xed_instr);
341 xed_iform_enum_t iform = xed_decoded_inst_get_iform_enum(&xed_instr);
343 #ifdef CONFIG_DEBUG_DECODER
344 xed_iclass_enum_t iclass = xed_decoded_inst_get_iclass(&xed_instr);
346 PrintDebug("iform=%s, iclass=%s\n", xed_iform_enum_t2str(iform), xed_iclass_enum_t2str(iclass));
350 if ((instr->op_type = get_opcode(iform)) == V3_INVALID_OP) {
351 PrintError("Could not get opcode. (iform=%s)\n", xed_iform_enum_t2str(iform));
356 // We special case the string operations...
357 if (xed_decoded_inst_get_category(&xed_instr) == XED_CATEGORY_STRINGOP) {
358 instr->is_str_op = 1;
359 return decode_string_op(info, &xed_instr, xi, instr);
361 instr->is_str_op = 0;
362 instr->str_op_length = 0;
365 instr->num_operands = xed_decoded_inst_noperands(&xed_instr);
368 if (instr->num_operands > 3) {
369 PrintDebug("Special Case Not Handled (more than 3 operands) (iform=%s)\n", xed_iform_enum_t2str(iform)
372 } else if (instr->num_operands == 3) {
373 const xed_operand_t * op = xed_inst_operand(xi, 2);
374 xed_operand_enum_t op_enum = xed_operand_name(op);
376 if ((!xed_operand_is_register(op_enum)) ||
377 (!is_flags_reg(xed_decoded_inst_get_reg(&xed_instr, op_enum)))) {
379 PrintError("Special Case not handled (iform=%s)\n", xed_iform_enum_t2str(iform));
385 //PrintDebug("Number of operands: %d\n", instr->num_operands);
386 //PrintDebug("INSTR length: %d\n", instr->instr_length);
389 if (instr->num_operands >= 1) {
390 const xed_operand_t * op = xed_inst_operand(xi, 0);
391 xed_operand_enum_t op_enum = xed_operand_name(op);
393 struct x86_operand * v3_op = NULL;
396 if (xed_operand_written(op)) {
397 v3_op = &(instr->dst_operand);
399 v3_op = &(instr->src_operand);
403 v3_op = &(instr->dst_operand);
405 if ((op->_rw == XED_OPERAND_ACTION_RW) ||
406 (op->_rw == XED_OPERAND_ACTION_R)||
407 (op->_rw == XED_OPERAND_ACTION_RCW)) {
411 if ((op->_rw == XED_OPERAND_ACTION_RW) ||
412 (op->_rw == XED_OPERAND_ACTION_W) ||
413 (op->_rw == XED_OPERAND_ACTION_CRW)) {
417 if (xed_operand_is_register(op_enum)) {
418 xed_reg_enum_t xed_reg = xed_decoded_inst_get_reg(&xed_instr, op_enum);
419 int v3_reg_type = xed_reg_to_v3_reg(info,
424 if (v3_reg_type == -1) {
425 PrintError("First operand is an Unhandled Operand: %s\n", xed_reg_enum_t2str(xed_reg));
426 v3_op->type = INVALID_OPERAND;
428 } else if (v3_reg_type == SEGMENT_REGISTER) {
429 struct v3_segment * seg_reg = (struct v3_segment *)(v3_op->operand);
430 v3_op->operand = (addr_t)&(seg_reg->selector);
433 v3_op->type = REG_OPERAND;
438 case XED_OPERAND_MEM0:
440 PrintDebug("Memory operand (1)\n");
441 if (get_memory_operand(info, &xed_instr, 0, v3_op) == -1) {
442 PrintError("Could not get first memory operand\n");
448 case XED_OPERAND_MEM1:
449 case XED_OPERAND_IMM1:
451 PrintError("Illegal Operand Order\n");
455 case XED_OPERAND_IMM0:
456 case XED_OPERAND_AGEN:
457 case XED_OPERAND_PTR:
458 case XED_OPERAND_RELBR:
460 PrintError("Unhandled Operand Type\n");
466 // set second operand
467 if (instr->num_operands >= 2) {
468 const xed_operand_t * op = xed_inst_operand(xi, 1);
469 // xed_operand_type_enum_t op_type = xed_operand_type(op);
470 xed_operand_enum_t op_enum = xed_operand_name(op);
472 struct x86_operand * v3_op;
475 if (xed_operand_written(op)) {
476 v3_op = &(instr->dst_operand);
478 v3_op = &(instr->src_operand);
481 v3_op = &(instr->src_operand);
483 if ((op->_rw == XED_OPERAND_ACTION_RW) ||
484 (op->_rw == XED_OPERAND_ACTION_R)||
485 (op->_rw == XED_OPERAND_ACTION_RCW)) {
489 if ((op->_rw == XED_OPERAND_ACTION_RW) ||
490 (op->_rw == XED_OPERAND_ACTION_W) ||
491 (op->_rw == XED_OPERAND_ACTION_CRW)) {
495 if (xed_operand_is_register(op_enum)) {
496 xed_reg_enum_t xed_reg = xed_decoded_inst_get_reg(&xed_instr, op_enum);
497 int v3_reg_type = xed_reg_to_v3_reg(info,
501 if (v3_reg_type == -1) {
502 PrintError("Second operand is an Unhandled Operand: %s\n", xed_reg_enum_t2str(xed_reg));
503 v3_op->type = INVALID_OPERAND;
505 } else if (v3_reg_type == SEGMENT_REGISTER) {
506 struct v3_segment * seg_reg = (struct v3_segment *)(v3_op->operand);
507 v3_op->operand = (addr_t)&(seg_reg->selector);
510 v3_op->type = REG_OPERAND;
514 case XED_OPERAND_MEM0:
516 PrintDebug("Memory operand (2)\n");
517 if (get_memory_operand(info, &xed_instr, 0, v3_op) == -1) {
518 PrintError("Could not get first memory operand\n");
524 case XED_OPERAND_IMM0:
526 instr->src_operand.size = xed_decoded_inst_get_immediate_width(&xed_instr);
528 if (instr->src_operand.size > 4) {
529 PrintError("Unhandled 64 bit immediates\n");
532 instr->src_operand.operand = xed_decoded_inst_get_unsigned_immediate(&xed_instr);
534 instr->src_operand.type = IMM_OPERAND;
539 case XED_OPERAND_MEM1:
540 case XED_OPERAND_IMM1:
542 PrintError("Illegal Operand Order\n");
545 case XED_OPERAND_AGEN:
546 case XED_OPERAND_PTR:
547 case XED_OPERAND_RELBR:
549 PrintError("Unhandled Operand Type\n");
556 if (instr->num_operands >= 3) {
557 const xed_operand_t * op = xed_inst_operand(xi, 2);
558 xed_operand_type_enum_t op_type = xed_operand_type(op);
559 xed_operand_enum_t op_enum = xed_operand_name(op);
561 if ((op->_rw == XED_OPERAND_ACTION_RW) ||
562 (op->_rw == XED_OPERAND_ACTION_R)||
563 (op->_rw == XED_OPERAND_ACTION_RCW)) {
564 instr->third_operand.read = 1;
567 if ((op->_rw == XED_OPERAND_ACTION_RW) ||
568 (op->_rw == XED_OPERAND_ACTION_W) ||
569 (op->_rw == XED_OPERAND_ACTION_CRW)) {
570 instr->third_operand.write = 1;
573 if (xed_operand_is_register(op_enum)) {
574 xed_reg_enum_t xed_reg = xed_decoded_inst_get_reg(&xed_instr, op_enum);
575 int v3_reg_type = xed_reg_to_v3_reg(info,
577 &(instr->third_operand.operand),
578 &(instr->third_operand.size));
580 if (v3_reg_type == -1) {
581 PrintError("Third operand is an Unhandled Operand: %s\n", xed_reg_enum_t2str(xed_reg));
582 instr->third_operand.type = INVALID_OPERAND;
584 } else if (v3_reg_type == SEGMENT_REGISTER) {
585 struct v3_segment * seg_reg = (struct v3_segment *)(instr->third_operand.operand);
586 instr->third_operand.operand = (addr_t)&(seg_reg->selector);
590 instr->third_operand.type = REG_OPERAND;
593 PrintError("Unhandled third operand type %s\n", xed_operand_type_enum_t2str(op_type));
594 instr->num_operands = 2;
602 int v3_encode(struct guest_info * info, struct x86_instr * instr, uint8_t * instr_buf) {
611 static int get_memory_operand(struct guest_info * info, xed_decoded_inst_t * xed_instr, uint_t op_index, struct x86_operand * operand) {
612 struct memory_operand mem_op;
618 ullong_t displacement;
619 int addr_width = v3_get_addr_width(info);
620 v3_cpu_mode_t cpu_mode = v3_get_vm_cpu_mode(info);
621 // struct v3_segment * seg_reg;
623 PrintDebug("Xed mode = %s\n", xed_machine_mode_enum_t2str(xed_state_get_machine_mode(info->decoder_state)));
624 PrintDebug("Address width: %s\n",
625 xed_address_width_enum_t2str(xed_state_get_address_width(info->decoder_state)));
626 PrintDebug("Stack Address width: %s\n",
627 xed_address_width_enum_t2str(xed_state_get_stack_address_width(info->decoder_state)));
631 memset((void*)&mem_op, '\0', sizeof(struct memory_operand));
633 xed_reg_enum_t xed_seg = xed_decoded_inst_get_seg_reg(xed_instr, op_index);
634 if (xed_seg != XED_REG_INVALID) {
635 struct v3_segment *tmp_segment;
636 if (xed_reg_to_v3_reg(info, xed_seg, (addr_t *)&tmp_segment, &(mem_op.segment_size)) == -1) {
637 PrintError("Unhandled Segment Register\n");
640 mem_op.segment = tmp_segment->base;
643 xed_reg_enum_t xed_base = xed_decoded_inst_get_base_reg(xed_instr, op_index);
644 if (xed_base != XED_REG_INVALID) {
646 if (xed_reg_to_v3_reg(info, xed_base, &base_reg, &(mem_op.base_size)) == -1) {
647 PrintError("Unhandled Base register\n");
650 mem_op.base = *(addr_t *)base_reg;
655 xed_reg_enum_t xed_idx = xed_decoded_inst_get_index_reg(xed_instr, op_index);
656 if ((op_index == 0) && (xed_idx != XED_REG_INVALID)) {
659 if (xed_reg_to_v3_reg(info, xed_idx, &index_reg, &(mem_op.index_size)) == -1) {
660 PrintError("Unhandled Index Register\n");
664 mem_op.index= *(addr_t *)index_reg;
666 xed_uint_t xed_scale = xed_decoded_inst_get_scale(xed_instr, op_index);
667 if (xed_scale != 0) {
668 mem_op.scale = xed_scale;
673 xed_uint_t disp_bits = xed_decoded_inst_get_memory_displacement_width(xed_instr, op_index);
675 xed_int64_t xed_disp = xed_decoded_inst_get_memory_displacement(xed_instr, op_index);
677 mem_op.displacement_size = disp_bits;
678 mem_op.displacement = xed_disp;
681 operand->type = MEM_OPERAND;
682 operand->size = xed_decoded_inst_get_memory_operand_length(xed_instr, op_index);
686 PrintDebug("Struct: Seg=%p (size=%d), base=%p, index=%p, scale=%p, displacement=%p (size=%d)\n",
687 (void *)mem_op.segment, mem_op.segment_size, (void*)mem_op.base, (void *)mem_op.index,
688 (void *)mem_op.scale, (void *)(addr_t)mem_op.displacement, mem_op.displacement_size);
691 PrintDebug("operand size: %d\n", operand->size);
693 seg = MASK(mem_op.segment, mem_op.segment_size);
694 base = MASK(mem_op.base, mem_op.base_size);
695 index = MASK(mem_op.index, mem_op.index_size);
696 scale = mem_op.scale;
698 // XED returns the displacement as a 2s complement signed number, but it can
699 // have different sizes, depending on the instruction encoding.
700 // we put that into a 64 bit unsigned (the unsigned doesn't matter since
701 // we only ever do 2s complement arithmetic on it. However, this means we
702 // need to sign-extend what XED provides through 64 bits.
703 displacement = mem_op.displacement;
704 displacement <<= 64 - mem_op.displacement_size * 8;
705 displacement = ((sllong_t)displacement) >> (64 - mem_op.displacement_size * 8);
708 PrintDebug("Seg=%p, base=%p, index=%p, scale=%p, displacement=%p\n",
709 (void *)seg, (void *)base, (void *)index, (void *)scale, (void *)(addr_t)displacement);
711 if (cpu_mode == REAL) {
712 operand->operand = seg + MASK((base + (scale * index) + displacement), addr_width);
714 operand->operand = MASK((seg + base + (scale * index) + displacement), addr_width);
721 static int xed_reg_to_v3_reg(struct guest_info * info, xed_reg_enum_t xed_reg,
722 addr_t * v3_reg, uint_t * reg_len) {
724 PrintDebug("Xed Register: %s\n", xed_reg_enum_t2str(xed_reg));
727 case XED_REG_INVALID:
736 *v3_reg = (addr_t)&(info->vm_regs.rax);
740 *v3_reg = (addr_t)&(info->vm_regs.rax);
744 *v3_reg = (addr_t)&(info->vm_regs.rax);
748 *v3_reg = (addr_t)(&(info->vm_regs.rax)) + 1;
752 *v3_reg = (addr_t)&(info->vm_regs.rax);
757 *v3_reg = (addr_t)&(info->vm_regs.rcx);
761 *v3_reg = (addr_t)&(info->vm_regs.rcx);
765 *v3_reg = (addr_t)&(info->vm_regs.rcx);
769 *v3_reg = (addr_t)(&(info->vm_regs.rcx)) + 1;
773 *v3_reg = (addr_t)&(info->vm_regs.rcx);
778 *v3_reg = (addr_t)&(info->vm_regs.rdx);
782 *v3_reg = (addr_t)&(info->vm_regs.rdx);
786 *v3_reg = (addr_t)&(info->vm_regs.rdx);
790 *v3_reg = (addr_t)(&(info->vm_regs.rdx)) + 1;
794 *v3_reg = (addr_t)&(info->vm_regs.rdx);
799 *v3_reg = (addr_t)&(info->vm_regs.rbx);
803 *v3_reg = (addr_t)&(info->vm_regs.rbx);
807 *v3_reg = (addr_t)&(info->vm_regs.rbx);
811 *v3_reg = (addr_t)(&(info->vm_regs.rbx)) + 1;
815 *v3_reg = (addr_t)&(info->vm_regs.rbx);
821 *v3_reg = (addr_t)&(info->vm_regs.rsp);
825 *v3_reg = (addr_t)&(info->vm_regs.rsp);
829 *v3_reg = (addr_t)&(info->vm_regs.rsp);
833 *v3_reg = (addr_t)&(info->vm_regs.rsp);
838 *v3_reg = (addr_t)&(info->vm_regs.rbp);
842 *v3_reg = (addr_t)&(info->vm_regs.rbp);
846 *v3_reg = (addr_t)&(info->vm_regs.rbp);
850 *v3_reg = (addr_t)&(info->vm_regs.rbp);
857 *v3_reg = (addr_t)&(info->vm_regs.rsi);
861 *v3_reg = (addr_t)&(info->vm_regs.rsi);
865 *v3_reg = (addr_t)&(info->vm_regs.rsi);
869 *v3_reg = (addr_t)&(info->vm_regs.rsi);
875 *v3_reg = (addr_t)&(info->vm_regs.rdi);
879 *v3_reg = (addr_t)&(info->vm_regs.rdi);
883 *v3_reg = (addr_t)&(info->vm_regs.rdi);
887 *v3_reg = (addr_t)&(info->vm_regs.rdi);
896 *v3_reg = (addr_t)&(info->vm_regs.r8);
900 *v3_reg = (addr_t)&(info->vm_regs.r8);
904 *v3_reg = (addr_t)&(info->vm_regs.r8);
908 *v3_reg = (addr_t)&(info->vm_regs.r8);
913 *v3_reg = (addr_t)&(info->vm_regs.r9);
917 *v3_reg = (addr_t)&(info->vm_regs.r9);
921 *v3_reg = (addr_t)&(info->vm_regs.r9);
925 *v3_reg = (addr_t)&(info->vm_regs.r9);
930 *v3_reg = (addr_t)&(info->vm_regs.r10);
934 *v3_reg = (addr_t)&(info->vm_regs.r10);
938 *v3_reg = (addr_t)&(info->vm_regs.r10);
942 *v3_reg = (addr_t)&(info->vm_regs.r10);
947 *v3_reg = (addr_t)&(info->vm_regs.r11);
951 *v3_reg = (addr_t)&(info->vm_regs.r11);
955 *v3_reg = (addr_t)&(info->vm_regs.r11);
959 *v3_reg = (addr_t)&(info->vm_regs.r11);
964 *v3_reg = (addr_t)&(info->vm_regs.r12);
968 *v3_reg = (addr_t)&(info->vm_regs.r12);
972 *v3_reg = (addr_t)&(info->vm_regs.r12);
976 *v3_reg = (addr_t)&(info->vm_regs.r12);
981 *v3_reg = (addr_t)&(info->vm_regs.r13);
985 *v3_reg = (addr_t)&(info->vm_regs.r13);
989 *v3_reg = (addr_t)&(info->vm_regs.r13);
993 *v3_reg = (addr_t)&(info->vm_regs.r13);
998 *v3_reg = (addr_t)&(info->vm_regs.r14);
1000 return GPR_REGISTER;
1002 *v3_reg = (addr_t)&(info->vm_regs.r14);
1004 return GPR_REGISTER;
1006 *v3_reg = (addr_t)&(info->vm_regs.r14);
1008 return GPR_REGISTER;
1010 *v3_reg = (addr_t)&(info->vm_regs.r14);
1012 return GPR_REGISTER;
1015 *v3_reg = (addr_t)&(info->vm_regs.r15);
1017 return GPR_REGISTER;
1019 *v3_reg = (addr_t)&(info->vm_regs.r15);
1021 return GPR_REGISTER;
1023 *v3_reg = (addr_t)&(info->vm_regs.r15);
1025 return GPR_REGISTER;
1027 *v3_reg = (addr_t)&(info->vm_regs.r15);
1029 return GPR_REGISTER;
1036 *v3_reg = (addr_t)&(info->rip);
1038 return CTRL_REGISTER;
1040 *v3_reg = (addr_t)&(info->rip);
1042 return CTRL_REGISTER;
1044 *v3_reg = (addr_t)&(info->rip);
1046 return CTRL_REGISTER;
1049 *v3_reg = (addr_t)&(info->ctrl_regs.rflags);
1051 return CTRL_REGISTER;
1052 case XED_REG_EFLAGS:
1053 *v3_reg = (addr_t)&(info->ctrl_regs.rflags);
1055 return CTRL_REGISTER;
1056 case XED_REG_RFLAGS:
1057 *v3_reg = (addr_t)&(info->ctrl_regs.rflags);
1059 return CTRL_REGISTER;
1062 *v3_reg = (addr_t)&(info->ctrl_regs.cr0);
1064 return CTRL_REGISTER;
1066 *v3_reg = (addr_t)&(info->ctrl_regs.cr2);
1068 return CTRL_REGISTER;
1070 *v3_reg = (addr_t)&(info->ctrl_regs.cr3);
1072 return CTRL_REGISTER;
1074 *v3_reg = (addr_t)&(info->ctrl_regs.cr4);
1076 return CTRL_REGISTER;
1078 *v3_reg = (addr_t)&(info->ctrl_regs.cr8);
1080 return CTRL_REGISTER;
1102 *v3_reg = (addr_t)&(info->segments.cs);
1104 return SEGMENT_REGISTER;
1106 *v3_reg = (addr_t)&(info->segments.ds);
1108 return SEGMENT_REGISTER;
1110 *v3_reg = (addr_t)&(info->segments.es);
1112 return SEGMENT_REGISTER;
1114 *v3_reg = (addr_t)&(info->segments.ss);
1116 return SEGMENT_REGISTER;
1118 *v3_reg = (addr_t)&(info->segments.fs);
1120 return SEGMENT_REGISTER;
1122 *v3_reg = (addr_t)&(info->segments.gs);
1124 return SEGMENT_REGISTER;
1131 PrintError("Segment selector operand... Don't know how to handle this...\n");
1196 case XED_REG_STACKPUSH:
1197 case XED_REG_STACKPOP:
1200 case XED_REG_TSCAUX:
1203 case XED_REG_X87CONTROL:
1204 case XED_REG_X87STATUS:
1205 case XED_REG_X87TOP:
1206 case XED_REG_X87TAG:
1207 case XED_REG_X87PUSH:
1208 case XED_REG_X87POP:
1209 case XED_REG_X87POP2:
1244 static v3_op_type_t get_opcode(xed_iform_enum_t iform) {
1248 /* Control Instructions */
1250 case XED_IFORM_MOV_CR_GPR64_CR:
1251 case XED_IFORM_MOV_CR_GPR32_CR:
1252 return V3_OP_MOVCR2;
1254 case XED_IFORM_MOV_CR_CR_GPR64:
1255 case XED_IFORM_MOV_CR_CR_GPR32:
1256 return V3_OP_MOV2CR;
1258 case XED_IFORM_SMSW_GPRv:
1261 case XED_IFORM_LMSW_GPR16:
1264 case XED_IFORM_CLTS:
1267 case XED_IFORM_INVLPG_MEMb:
1268 return V3_OP_INVLPG;
1271 /* Data Instructions */
1274 case XED_IFORM_ADC_MEMv_GPRv:
1275 case XED_IFORM_ADC_MEMv_IMM:
1276 case XED_IFORM_ADC_MEMb_GPR8:
1277 case XED_IFORM_ADC_MEMb_IMM:
1279 case XED_IFORM_ADC_GPRv_MEMv:
1280 case XED_IFORM_ADC_GPR8_MEMb:
1284 case XED_IFORM_ADD_MEMv_GPRv:
1285 case XED_IFORM_ADD_MEMb_IMM:
1286 case XED_IFORM_ADD_MEMb_GPR8:
1287 case XED_IFORM_ADD_MEMv_IMM:
1289 case XED_IFORM_ADD_GPRv_MEMv:
1290 case XED_IFORM_ADD_GPR8_MEMb:
1294 case XED_IFORM_AND_MEMv_IMM:
1295 case XED_IFORM_AND_MEMb_GPR8:
1296 case XED_IFORM_AND_MEMv_GPRv:
1297 case XED_IFORM_AND_MEMb_IMM:
1299 case XED_IFORM_AND_GPR8_MEMb:
1300 case XED_IFORM_AND_GPRv_MEMv:
1304 case XED_IFORM_SUB_MEMv_IMM:
1305 case XED_IFORM_SUB_MEMb_GPR8:
1306 case XED_IFORM_SUB_MEMb_IMM:
1307 case XED_IFORM_SUB_MEMv_GPRv:
1309 case XED_IFORM_SUB_GPR8_MEMb:
1310 case XED_IFORM_SUB_GPRv_MEMv:
1314 case XED_IFORM_MOV_MEMv_GPRv:
1315 case XED_IFORM_MOV_MEMb_GPR8:
1316 case XED_IFORM_MOV_MEMv_OrAX:
1317 case XED_IFORM_MOV_MEMb_AL:
1318 case XED_IFORM_MOV_MEMv_IMM:
1319 case XED_IFORM_MOV_MEMb_IMM:
1321 case XED_IFORM_MOV_GPRv_MEMv:
1322 case XED_IFORM_MOV_GPR8_MEMb:
1323 case XED_IFORM_MOV_OrAX_MEMv:
1324 case XED_IFORM_MOV_AL_MEMb:
1329 case XED_IFORM_MOVZX_GPRv_MEMb:
1330 case XED_IFORM_MOVZX_GPRv_MEMw:
1334 case XED_IFORM_MOVSX_GPRv_MEMb:
1335 case XED_IFORM_MOVSX_GPRv_MEMw:
1340 case XED_IFORM_DEC_MEMv:
1341 case XED_IFORM_DEC_MEMb:
1344 case XED_IFORM_INC_MEMb:
1345 case XED_IFORM_INC_MEMv:
1349 case XED_IFORM_OR_MEMv_IMM:
1350 case XED_IFORM_OR_MEMb_IMM:
1351 case XED_IFORM_OR_MEMv_GPRv:
1352 case XED_IFORM_OR_MEMb_GPR8:
1354 case XED_IFORM_OR_GPRv_MEMv:
1355 case XED_IFORM_OR_GPR8_MEMb:
1359 case XED_IFORM_XOR_MEMv_GPRv:
1360 case XED_IFORM_XOR_MEMb_IMM:
1361 case XED_IFORM_XOR_MEMb_GPR8:
1362 case XED_IFORM_XOR_MEMv_IMM:
1364 case XED_IFORM_XOR_GPRv_MEMv:
1365 case XED_IFORM_XOR_GPR8_MEMb:
1368 case XED_IFORM_NEG_MEMb:
1369 case XED_IFORM_NEG_MEMv:
1372 case XED_IFORM_NOT_MEMv:
1373 case XED_IFORM_NOT_MEMb:
1376 case XED_IFORM_XCHG_MEMv_GPRv:
1377 case XED_IFORM_XCHG_MEMb_GPR8:
1380 case XED_IFORM_SETB_MEMb:
1383 case XED_IFORM_SETBE_MEMb:
1386 case XED_IFORM_SETL_MEMb:
1389 case XED_IFORM_SETLE_MEMb:
1392 case XED_IFORM_SETNB_MEMb:
1395 case XED_IFORM_SETNBE_MEMb:
1396 return V3_OP_SETNBE;
1398 case XED_IFORM_SETNL_MEMb:
1401 case XED_IFORM_SETNLE_MEMb:
1402 return V3_OP_SETNLE;
1404 case XED_IFORM_SETNO_MEMb:
1407 case XED_IFORM_SETNP_MEMb:
1410 case XED_IFORM_SETNS_MEMb:
1413 case XED_IFORM_SETNZ_MEMb:
1416 case XED_IFORM_SETO_MEMb:
1419 case XED_IFORM_SETP_MEMb:
1422 case XED_IFORM_SETS_MEMb:
1425 case XED_IFORM_SETZ_MEMb:
1428 case XED_IFORM_MOVSB:
1429 case XED_IFORM_MOVSW:
1430 case XED_IFORM_MOVSD:
1431 case XED_IFORM_MOVSQ:
1434 case XED_IFORM_STOSB:
1435 case XED_IFORM_STOSW:
1436 case XED_IFORM_STOSD:
1437 case XED_IFORM_STOSQ:
1442 return V3_INVALID_OP;