2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
11 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
17 * This is free software. You are permitted to use,
18 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #ifndef __VMM_DIRECT_PAGING_64_H__
22 #define __VMM_DIRECT_PAGING_64_H__
24 #include <palacios/vmm_mem.h>
25 #include <palacios/vmm_paging.h>
26 #include <palacios/vmm.h>
27 #include <palacios/vm_guest_mem.h>
28 #include <palacios/vm_guest.h>
32 static inline int handle_passthrough_pagefault_64(struct guest_info * info,
34 pf_error_t error_code) {
35 pml4e64_t * pml = NULL;
36 pdpe64_t * pdpe = NULL;
41 int pml_index = PML4E64_INDEX(fault_addr);
42 int pdpe_index = PDPE64_INDEX(fault_addr);
43 int pde_index = PDE64_INDEX(fault_addr);
44 int pte_index = PTE64_INDEX(fault_addr);
49 struct v3_mem_region * region = v3_get_mem_region(info->vm_info, info->cpu_id, fault_addr);
52 PrintError("Invalid region in passthrough page fault 64, addr=%p\n",
57 host_addr = v3_get_shadow_addr(region, info->cpu_id, fault_addr);
60 // Lookup the correct PML address based on the PAGING MODE
61 if (info->shdw_pg_mode == SHADOW_PAGING) {
62 pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
64 pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
67 //Fix up the PML entry
68 if (pml[pml_index].present == 0) {
69 pdpe = (pdpe64_t *)create_generic_pt_page();
71 // Set default PML Flags...
72 pml[pml_index].present = 1;
73 pml[pml_index].writable = 1;
74 pml[pml_index].user_page = 1;
76 pml[pml_index].pdp_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pdpe));
78 pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
81 // Fix up the PDPE entry
82 if (pdpe[pdpe_index].present == 0) {
83 pde = (pde64_t *)create_generic_pt_page();
85 // Set default PDPE Flags...
86 pdpe[pdpe_index].present = 1;
87 pdpe[pdpe_index].writable = 1;
88 pdpe[pdpe_index].user_page = 1;
90 pdpe[pdpe_index].pd_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pde));
92 pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
96 // Fix up the PDE entry
97 if (pde[pde_index].present == 0) {
98 pte = (pte64_t *)create_generic_pt_page();
100 pde[pde_index].present = 1;
101 pde[pde_index].writable = 1;
102 pde[pde_index].user_page = 1;
104 pde[pde_index].pt_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pte));
106 pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
110 // Fix up the PTE entry
111 if (pte[pte_index].present == 0) {
112 pte[pte_index].user_page = 1;
114 if ((region->flags.alloced == 1) &&
115 (region->flags.read == 1)) {
117 pte[pte_index].present = 1;
119 if (region->flags.write == 1) {
120 pte[pte_index].writable = 1;
122 pte[pte_index].writable = 0;
125 pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
127 return region->unhandled(info, fault_addr, fault_addr, region, error_code);
130 // We fix all permissions on the first pass,
131 // so we only get here if its an unhandled exception
133 return region->unhandled(info, fault_addr, fault_addr, region, error_code);
139 static inline int invalidate_addr_64(struct guest_info * info, addr_t inv_addr) {
140 pml4e64_t * pml = NULL;
141 pdpe64_t * pdpe = NULL;
142 pde64_t * pde = NULL;
143 pte64_t * pte = NULL;
149 // clear the page table entry
150 int pml_index = PML4E64_INDEX(inv_addr);
151 int pdpe_index = PDPE64_INDEX(inv_addr);
152 int pde_index = PDE64_INDEX(inv_addr);
153 int pte_index = PTE64_INDEX(inv_addr);
156 // Lookup the correct PDE address based on the PAGING MODE
157 if (info->shdw_pg_mode == SHADOW_PAGING) {
158 pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
160 pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
163 if (pml[pml_index].present == 0) {
167 pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
169 if (pdpe[pdpe_index].present == 0) {
171 } else if (pdpe[pdpe_index].large_page == 1) {
172 pdpe[pdpe_index].present = 0;
176 pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
178 if (pde[pde_index].present == 0) {
180 } else if (pde[pde_index].large_page == 1) {
181 pde[pde_index].present = 0;
185 pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
187 pte[pte_index].present = 0;