2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
11 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
17 * This is free software. You are permitted to use,
18 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #ifndef __VMM_DIRECT_PAGING_64_H__
22 #define __VMM_DIRECT_PAGING_64_H__
24 #include <palacios/vmm_mem.h>
25 #include <palacios/vmm_paging.h>
26 #include <palacios/vmm.h>
27 #include <palacios/vm_guest_mem.h>
28 #include <palacios/vm_guest.h>
30 // Reference: AMD Software Developer Manual Vol.2 Ch.5 "Page Translation and Protection"
32 static int get_page_size() {
34 // Need to fix this....
39 static inline int handle_passthrough_pagefault_64(struct guest_info * core, addr_t fault_addr, pf_error_t error_code) {
40 pml4e64_t * pml = NULL;
41 pdpe64_t * pdpe = NULL;
43 pde64_2MB_t * pde2mb = NULL;
47 int pml_index = PML4E64_INDEX(fault_addr);
48 int pdpe_index = PDPE64_INDEX(fault_addr);
49 int pde_index = PDE64_INDEX(fault_addr);
50 int pte_index = PTE64_INDEX(fault_addr);
52 struct v3_mem_region * region = v3_get_mem_region(core->vm_info, core->cpu_id, fault_addr);
53 int page_size = PAGE_SIZE_4KB;
57 * 1. the guest is configured to use large pages and
58 * 2. the memory regions can be referenced by a large page
60 if ((core->use_large_pages == 1) ) {
61 page_size = get_page_size();
65 // Lookup the correct PML address based on the PAGING MODE
66 if (core->shdw_pg_mode == SHADOW_PAGING) {
67 pml = CR3_TO_PML4E64_VA(core->ctrl_regs.cr3);
69 pml = CR3_TO_PML4E64_VA(core->direct_map_pt);
72 //Fix up the PML entry
73 if (pml[pml_index].present == 0) {
74 pdpe = (pdpe64_t *)create_generic_pt_page();
76 // Set default PML Flags...
77 pml[pml_index].present = 1;
78 pml[pml_index].writable = 1;
79 pml[pml_index].user_page = 1;
81 pml[pml_index].pdp_base_addr = PAGE_BASE_ADDR_4KB((addr_t)V3_PAddr(pdpe));
83 pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR_4KB(pml[pml_index].pdp_base_addr));
86 // Fix up the PDPE entry
87 if (pdpe[pdpe_index].present == 0) {
88 pde = (pde64_t *)create_generic_pt_page();
90 // Set default PDPE Flags...
91 pdpe[pdpe_index].present = 1;
92 pdpe[pdpe_index].writable = 1;
93 pdpe[pdpe_index].user_page = 1;
95 pdpe[pdpe_index].pd_base_addr = PAGE_BASE_ADDR_4KB((addr_t)V3_PAddr(pde));
97 pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR_4KB(pdpe[pdpe_index].pd_base_addr));
102 // Continue with the 4KiB page heirarchy
104 // Fix up the PDE entry
105 if (pde[pde_index].present == 0) {
106 pte = (pte64_t *)create_generic_pt_page();
108 pde[pde_index].present = 1;
109 pde[pde_index].writable = 1;
110 pde[pde_index].user_page = 1;
112 pde[pde_index].pt_base_addr = PAGE_BASE_ADDR_4KB((addr_t)V3_PAddr(pte));
114 pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR_4KB(pde[pde_index].pt_base_addr));
117 // Fix up the PTE entry
118 if (pte[pte_index].present == 0) {
119 pte[pte_index].user_page = 1;
121 if ((region->flags.alloced == 1) &&
122 (region->flags.read == 1)) {
124 pte[pte_index].present = 1;
126 if (region->flags.write == 1) {
127 pte[pte_index].writable = 1;
129 pte[pte_index].writable = 0;
132 if (v3_gpa_to_hpa(core, fault_addr, &host_addr) == -1) {
133 PrintError("Error Could not translate fault addr (%p)\n", (void *)fault_addr);
137 pte[pte_index].page_base_addr = PAGE_BASE_ADDR_4KB(host_addr);
139 return region->unhandled(core, fault_addr, fault_addr, region, error_code);
142 // We fix all permissions on the first pass,
143 // so we only get here if its an unhandled exception
145 return region->unhandled(core, fault_addr, fault_addr, region, error_code);
151 static inline int invalidate_addr_64(struct guest_info * core, addr_t inv_addr) {
152 pml4e64_t * pml = NULL;
153 pdpe64_t * pdpe = NULL;
154 pde64_t * pde = NULL;
155 pte64_t * pte = NULL;
161 // clear the page table entry
162 int pml_index = PML4E64_INDEX(inv_addr);
163 int pdpe_index = PDPE64_INDEX(inv_addr);
164 int pde_index = PDE64_INDEX(inv_addr);
165 int pte_index = PTE64_INDEX(inv_addr);
168 // Lookup the correct PDE address based on the PAGING MODE
169 if (core->shdw_pg_mode == SHADOW_PAGING) {
170 pml = CR3_TO_PML4E64_VA(core->ctrl_regs.cr3);
172 pml = CR3_TO_PML4E64_VA(core->direct_map_pt);
175 if (pml[pml_index].present == 0) {
179 pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
181 if (pdpe[pdpe_index].present == 0) {
183 } else if (pdpe[pdpe_index].large_page == 1) { // 1GiB
184 pdpe[pdpe_index].present = 0;
188 pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
190 if (pde[pde_index].present == 0) {
192 } else if (pde[pde_index].large_page == 1) { // 2MiB
193 pde[pde_index].present = 0;
197 pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
199 pte[pte_index].present = 0; // 4KiB