2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
11 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
17 * This is free software. You are permitted to use,
18 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #ifndef __VMM_DIRECT_PAGING_64_H__
22 #define __VMM_DIRECT_PAGING_64_H__
24 #include <palacios/vmm_mem.h>
25 #include <palacios/vmm_paging.h>
26 #include <palacios/vmm.h>
27 #include <palacios/vm_guest_mem.h>
28 #include <palacios/vm_guest.h>
32 static inline int handle_passthrough_pagefault_64(struct guest_info * info,
34 pf_error_t error_code) {
35 pml4e64_t * pml = NULL;
36 pdpe64_t * pdpe = NULL;
41 int pml_index = PML4E64_INDEX(fault_addr);
42 int pdpe_index = PDPE64_INDEX(fault_addr);
43 int pde_index = PDE64_INDEX(fault_addr);
44 int pte_index = PTE64_INDEX(fault_addr);
49 struct v3_mem_region * region = v3_get_mem_region(info->vm_info, info->cpu_id, fault_addr);
52 PrintError("Invalid region in passthrough page fault 64, addr=%p\n",
57 // Lookup the correct PML address based on the PAGING MODE
58 if (info->shdw_pg_mode == SHADOW_PAGING) {
59 pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
61 pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
64 //Fix up the PML entry
65 if (pml[pml_index].present == 0) {
66 pdpe = (pdpe64_t *)create_generic_pt_page();
68 // Set default PML Flags...
69 pml[pml_index].present = 1;
70 pml[pml_index].writable = 1;
71 pml[pml_index].user_page = 1;
73 pml[pml_index].pdp_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pdpe));
75 pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
78 // Fix up the PDPE entry
79 if (pdpe[pdpe_index].present == 0) {
80 pde = (pde64_t *)create_generic_pt_page();
82 // Set default PDPE Flags...
83 pdpe[pdpe_index].present = 1;
84 pdpe[pdpe_index].writable = 1;
85 pdpe[pdpe_index].user_page = 1;
87 pdpe[pdpe_index].pd_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pde));
89 pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
93 // Fix up the PDE entry
94 if (pde[pde_index].present == 0) {
95 pte = (pte64_t *)create_generic_pt_page();
97 pde[pde_index].present = 1;
98 pde[pde_index].writable = 1;
99 pde[pde_index].user_page = 1;
101 pde[pde_index].pt_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pte));
103 pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
107 // Fix up the PTE entry
108 if (pte[pte_index].present == 0) {
109 pte[pte_index].user_page = 1;
111 if ((region->flags.alloced == 1) &&
112 (region->flags.read == 1)) {
114 pte[pte_index].present = 1;
116 if (region->flags.write == 1) {
117 pte[pte_index].writable = 1;
119 pte[pte_index].writable = 0;
122 if (v3_gpa_to_hpa(info, fault_addr, &host_addr) == -1) {
123 PrintError("Error Could not translate fault addr (%p)\n", (void *)fault_addr);
127 pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
129 return region->unhandled(info, fault_addr, fault_addr, region, error_code);
132 // We fix all permissions on the first pass,
133 // so we only get here if its an unhandled exception
135 return region->unhandled(info, fault_addr, fault_addr, region, error_code);
141 static inline int invalidate_addr_64(struct guest_info * info, addr_t inv_addr) {
142 pml4e64_t * pml = NULL;
143 pdpe64_t * pdpe = NULL;
144 pde64_t * pde = NULL;
145 pte64_t * pte = NULL;
151 // clear the page table entry
152 int pml_index = PML4E64_INDEX(inv_addr);
153 int pdpe_index = PDPE64_INDEX(inv_addr);
154 int pde_index = PDE64_INDEX(inv_addr);
155 int pte_index = PTE64_INDEX(inv_addr);
158 // Lookup the correct PDE address based on the PAGING MODE
159 if (info->shdw_pg_mode == SHADOW_PAGING) {
160 pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
162 pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
165 if (pml[pml_index].present == 0) {
169 pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
171 if (pdpe[pdpe_index].present == 0) {
173 } else if (pdpe[pdpe_index].large_page == 1) {
174 pdpe[pdpe_index].present = 0;
178 pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
180 if (pde[pde_index].present == 0) {
182 } else if (pde[pde_index].large_page == 1) {
183 pde[pde_index].present = 0;
187 pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
189 pte[pte_index].present = 0;