2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
11 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Steven Jaconette <stevenjaconette2007@u.northwestern.edu>
17 * This is free software. You are permitted to use,
18 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #ifndef __VMM_DIRECT_PAGING_64_H__
22 #define __VMM_DIRECT_PAGING_64_H__
24 #include <palacios/vmm_mem.h>
25 #include <palacios/vmm_paging.h>
26 #include <palacios/vmm.h>
27 #include <palacios/vm_guest_mem.h>
28 #include <palacios/vm_guest.h>
32 static inline int handle_passthrough_pagefault_64(struct guest_info * info,
34 pf_error_t error_code) {
35 pml4e64_t * pml = NULL;
36 pdpe64_t * pdpe = NULL;
41 int pml_index = PML4E64_INDEX(fault_addr);
42 int pdpe_index = PDPE64_INDEX(fault_addr);
43 int pde_index = PDE64_INDEX(fault_addr);
44 int pte_index = PTE64_INDEX(fault_addr);
49 struct v3_mem_region * region = v3_get_mem_region(info->vm_info, info->cpu_id, fault_addr);
52 PrintError("Invalid region in passthrough page fault 64, addr=%p\n",
57 if (v3_gpa_to_hpa(info, fault_addr, &host_addr) == -1) {
58 PrintError("Error Could not translate fault addr (%p)\n", (void *)fault_addr);
63 // Lookup the correct PML address based on the PAGING MODE
64 if (info->shdw_pg_mode == SHADOW_PAGING) {
65 pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
67 pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
70 //Fix up the PML entry
71 if (pml[pml_index].present == 0) {
72 pdpe = (pdpe64_t *)create_generic_pt_page();
74 // Set default PML Flags...
75 pml[pml_index].present = 1;
76 pml[pml_index].writable = 1;
77 pml[pml_index].user_page = 1;
79 pml[pml_index].pdp_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pdpe));
81 pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
84 // Fix up the PDPE entry
85 if (pdpe[pdpe_index].present == 0) {
86 pde = (pde64_t *)create_generic_pt_page();
88 // Set default PDPE Flags...
89 pdpe[pdpe_index].present = 1;
90 pdpe[pdpe_index].writable = 1;
91 pdpe[pdpe_index].user_page = 1;
93 pdpe[pdpe_index].pd_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pde));
95 pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
99 // Fix up the PDE entry
100 if (pde[pde_index].present == 0) {
101 pte = (pte64_t *)create_generic_pt_page();
103 pde[pde_index].present = 1;
104 pde[pde_index].writable = 1;
105 pde[pde_index].user_page = 1;
107 pde[pde_index].pt_base_addr = PAGE_BASE_ADDR((addr_t)V3_PAddr(pte));
109 pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
113 // Fix up the PTE entry
114 if (pte[pte_index].present == 0) {
115 pte[pte_index].user_page = 1;
117 if ((region->flags.alloced == 1) &&
118 (region->flags.read == 1)) {
120 pte[pte_index].present = 1;
122 if (region->flags.write == 1) {
123 pte[pte_index].writable = 1;
125 pte[pte_index].writable = 0;
128 pte[pte_index].page_base_addr = PAGE_BASE_ADDR(host_addr);
130 return region->unhandled(info, fault_addr, fault_addr, region, error_code);
133 // We fix all permissions on the first pass,
134 // so we only get here if its an unhandled exception
136 return region->unhandled(info, fault_addr, fault_addr, region, error_code);
142 static inline int invalidate_addr_64(struct guest_info * info, addr_t inv_addr) {
143 pml4e64_t * pml = NULL;
144 pdpe64_t * pdpe = NULL;
145 pde64_t * pde = NULL;
146 pte64_t * pte = NULL;
152 // clear the page table entry
153 int pml_index = PML4E64_INDEX(inv_addr);
154 int pdpe_index = PDPE64_INDEX(inv_addr);
155 int pde_index = PDE64_INDEX(inv_addr);
156 int pte_index = PTE64_INDEX(inv_addr);
159 // Lookup the correct PDE address based on the PAGING MODE
160 if (info->shdw_pg_mode == SHADOW_PAGING) {
161 pml = CR3_TO_PML4E64_VA(info->ctrl_regs.cr3);
163 pml = CR3_TO_PML4E64_VA(info->direct_map_pt);
166 if (pml[pml_index].present == 0) {
170 pdpe = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pml[pml_index].pdp_base_addr));
172 if (pdpe[pdpe_index].present == 0) {
174 } else if (pdpe[pdpe_index].large_page == 1) {
175 pdpe[pdpe_index].present = 0;
179 pde = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pdpe[pdpe_index].pd_base_addr));
181 if (pde[pde_index].present == 0) {
183 } else if (pde[pde_index].large_page == 1) {
184 pde[pde_index].present = 0;
188 pte = V3_VAddr((void*)BASE_TO_PAGE_ADDR(pde[pde_index].pt_base_addr));
190 pte[pte_index].present = 0;