2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
22 #include <palacios/svm.h>
23 #include <palacios/vmm.h>
25 #include <palacios/vmcb.h>
26 #include <palacios/vmm_mem.h>
27 #include <palacios/vmm_paging.h>
28 #include <palacios/svm_handler.h>
30 #include <palacios/vmm_debug.h>
31 #include <palacios/vm_guest_mem.h>
33 #include <palacios/vmm_decoder.h>
34 #include <palacios/vmm_string.h>
35 #include <palacios/vmm_lowlevel.h>
36 #include <palacios/svm_msr.h>
38 #include <palacios/vmm_rbtree.h>
39 #include <palacios/vmm_barrier.h>
40 #include <palacios/vmm_debug.h>
42 #include <palacios/vmm_perftune.h>
45 #ifdef V3_CONFIG_CHECKPOINT
46 #include <palacios/vmm_checkpoint.h>
49 #include <palacios/vmm_direct_paging.h>
51 #include <palacios/vmm_ctrl_regs.h>
52 #include <palacios/svm_io.h>
54 #include <palacios/vmm_sprintf.h>
56 #ifdef V3_CONFIG_TM_FUNC
57 #include <extensions/trans_mem.h>
60 #ifndef V3_CONFIG_DEBUG_SVM
62 #define PrintDebug(fmt, args...)
67 uint32_t v3_last_exit;
69 // This is a global pointer to the host's VMCB
70 static addr_t host_vmcbs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0};
74 extern void v3_stgi();
75 extern void v3_clgi();
76 //extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, uint64_t * fs, uint64_t * gs);
77 extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, vmcb_t * host_vmcb);
80 static vmcb_t * Allocate_VMCB() {
81 vmcb_t * vmcb_page = NULL;
82 addr_t vmcb_pa = (addr_t)V3_AllocPages(1); // need not be shadow safe, not exposed to guest
84 if ((void *)vmcb_pa == NULL) {
85 PrintError(VM_NONE, VCORE_NONE, "Error allocating VMCB\n");
89 vmcb_page = (vmcb_t *)V3_VAddr((void *)vmcb_pa);
91 memset(vmcb_page, 0, 4096);
97 static int v3_svm_handle_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data)
101 // Call arch-independent handler
102 if ((status = v3_handle_efer_write(core, msr, src, priv_data)) != 0) {
108 // Ensure that hardware visible EFER.SVME bit is set (SVM Enable)
109 struct efer_64 * hw_efer = (struct efer_64 *)&(core->ctrl_regs.efer);
117 static void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info * core) {
118 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
119 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
124 ctrl_area->svm_instrs.VMRUN = 1;
125 ctrl_area->svm_instrs.VMMCALL = 1;
126 ctrl_area->svm_instrs.VMLOAD = 1;
127 ctrl_area->svm_instrs.VMSAVE = 1;
128 ctrl_area->svm_instrs.STGI = 1;
129 ctrl_area->svm_instrs.CLGI = 1;
130 ctrl_area->svm_instrs.SKINIT = 1;
131 ctrl_area->svm_instrs.ICEBP = 1;
132 ctrl_area->svm_instrs.WBINVD = 1;
133 ctrl_area->svm_instrs.MONITOR = 1;
134 ctrl_area->svm_instrs.MWAIT_always = 1;
135 ctrl_area->svm_instrs.MWAIT_if_armed = 1;
136 ctrl_area->instrs.INVLPGA = 1;
137 ctrl_area->instrs.CPUID = 1;
139 ctrl_area->instrs.HLT = 1;
141 /* Set at VMM launch as needed */
142 ctrl_area->instrs.RDTSC = 0;
143 ctrl_area->svm_instrs.RDTSCP = 0;
145 // guest_state->cr0 = 0x00000001; // PE
148 ctrl_area->exceptions.de = 1;
149 ctrl_area->exceptions.df = 1;
151 ctrl_area->exceptions.ts = 1;
152 ctrl_area->exceptions.ss = 1;
153 ctrl_area->exceptions.ac = 1;
154 ctrl_area->exceptions.mc = 1;
155 ctrl_area->exceptions.gp = 1;
156 ctrl_area->exceptions.ud = 1;
157 ctrl_area->exceptions.np = 1;
158 ctrl_area->exceptions.of = 1;
160 ctrl_area->exceptions.nmi = 1;
163 #ifdef V3_CONFIG_TM_FUNC
164 v3_tm_set_excp_intercepts(ctrl_area);
168 ctrl_area->instrs.NMI = 1;
169 ctrl_area->instrs.SMI = 0; // allow SMIs to run in guest
170 ctrl_area->instrs.INIT = 1;
171 // ctrl_area->instrs.PAUSE = 1;
172 ctrl_area->instrs.shutdown_evts = 1;
175 /* DEBUG FOR RETURN CODE */
176 ctrl_area->exit_code = 1;
179 /* Setup Guest Machine state */
181 core->vm_regs.rsp = 0x00;
184 core->vm_regs.rdx = 0x00000f00;
189 core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1
190 core->ctrl_regs.cr0 = 0x60010010; // Set the WP flag so the memory hooks work in real-mode
191 core->ctrl_regs.efer |= EFER_MSR_svm_enable;
197 core->segments.cs.selector = 0xf000;
198 core->segments.cs.limit = 0xffff;
199 core->segments.cs.base = 0x0000000f0000LL;
201 // (raw attributes = 0xf3)
202 core->segments.cs.type = 0x3;
203 core->segments.cs.system = 0x1;
204 core->segments.cs.dpl = 0x3;
205 core->segments.cs.present = 1;
209 struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds),
210 &(core->segments.es), &(core->segments.fs),
211 &(core->segments.gs), NULL};
213 for ( i = 0; segregs[i] != NULL; i++) {
214 struct v3_segment * seg = segregs[i];
216 seg->selector = 0x0000;
217 // seg->base = seg->selector << 4;
218 seg->base = 0x00000000;
221 // (raw attributes = 0xf3)
228 core->segments.gdtr.limit = 0x0000ffff;
229 core->segments.gdtr.base = 0x0000000000000000LL;
230 core->segments.idtr.limit = 0x0000ffff;
231 core->segments.idtr.base = 0x0000000000000000LL;
233 core->segments.ldtr.selector = 0x0000;
234 core->segments.ldtr.limit = 0x0000ffff;
235 core->segments.ldtr.base = 0x0000000000000000LL;
236 core->segments.tr.selector = 0x0000;
237 core->segments.tr.limit = 0x0000ffff;
238 core->segments.tr.base = 0x0000000000000000LL;
241 core->dbg_regs.dr6 = 0x00000000ffff0ff0LL;
242 core->dbg_regs.dr7 = 0x0000000000000400LL;
245 ctrl_area->IOPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->io_map.arch_data);
246 ctrl_area->instrs.IOIO_PROT = 1;
248 ctrl_area->MSRPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data);
249 ctrl_area->instrs.MSR_PROT = 1;
252 PrintDebug(core->vm_info, core, "Exiting on interrupts\n");
253 ctrl_area->guest_ctrl.V_INTR_MASKING = 1;
254 ctrl_area->instrs.INTR = 1;
255 // The above also assures the TPR changes (CR8) are only virtual
258 // However, we need to see TPR writes since they will
259 // affect the virtual apic
260 // we reflect out cr8 to ctrl_regs->apic_tpr
261 ctrl_area->cr_reads.cr8 = 1;
262 ctrl_area->cr_writes.cr8 = 1;
263 // We will do all TPR comparisons in the virtual apic
264 // We also do not want the V_TPR to be able to mask the PIC
265 ctrl_area->guest_ctrl.V_IGN_TPR = 1;
269 v3_hook_msr(core->vm_info, EFER_MSR,
270 &v3_handle_efer_read,
271 &v3_svm_handle_efer_write,
274 if (core->shdw_pg_mode == SHADOW_PAGING) {
275 PrintDebug(core->vm_info, core, "Creating initial shadow page table\n");
277 /* JRL: This is a performance killer, and a simplistic solution */
278 /* We need to fix this */
279 ctrl_area->TLB_CONTROL = 1;
280 ctrl_area->guest_ASID = 1;
283 if (v3_init_passthrough_pts(core) == -1) {
284 PrintError(core->vm_info, core, "Could not initialize passthrough page tables\n");
289 core->shdw_pg_state.guest_cr0 = 0x0000000000000010LL;
290 PrintDebug(core->vm_info, core, "Created\n");
292 core->ctrl_regs.cr0 |= 0x80000000;
293 core->ctrl_regs.cr3 = core->direct_map_pt;
295 ctrl_area->cr_reads.cr0 = 1;
296 ctrl_area->cr_writes.cr0 = 1;
297 //ctrl_area->cr_reads.cr4 = 1;
298 ctrl_area->cr_writes.cr4 = 1;
299 ctrl_area->cr_reads.cr3 = 1;
300 ctrl_area->cr_writes.cr3 = 1;
303 ctrl_area->instrs.INVLPG = 1;
305 ctrl_area->exceptions.pf = 1;
307 guest_state->g_pat = 0x7040600070406ULL;
310 } else if (core->shdw_pg_mode == NESTED_PAGING) {
311 // Flush the TLB on entries/exits
312 ctrl_area->TLB_CONTROL = 1;
313 ctrl_area->guest_ASID = 1;
315 // Enable Nested Paging
316 ctrl_area->NP_ENABLE = 1;
318 PrintDebug(core->vm_info, core, "NP_Enable at 0x%p\n", (void *)&(ctrl_area->NP_ENABLE));
320 // Set the Nested Page Table pointer
321 if (v3_init_passthrough_pts(core) == -1) {
322 PrintError(core->vm_info, core, "Could not initialize Nested page tables\n");
326 ctrl_area->N_CR3 = core->direct_map_pt;
328 guest_state->g_pat = 0x7040600070406ULL;
331 /* tell the guest that we don't support SVM */
332 v3_hook_msr(core->vm_info, SVM_VM_CR_MSR,
333 &v3_handle_vm_cr_read,
334 &v3_handle_vm_cr_write,
339 #define INT_PENDING_AMD_MSR 0xc0010055
341 v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL);
342 v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL);
343 v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL);
344 v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL);
345 v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL);
347 v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL);
348 v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL);
349 v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL);
352 v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL);
353 v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL);
355 // Passthrough read operations are ok.
356 v3_hook_msr(core->vm_info, INT_PENDING_AMD_MSR, NULL, v3_msr_unhandled_write, NULL);
361 int v3_init_svm_vmcb(struct guest_info * core, v3_vm_class_t vm_class) {
363 PrintDebug(core->vm_info, core, "Allocating VMCB\n");
364 core->vmm_data = (void *)Allocate_VMCB();
366 if (core->vmm_data == NULL) {
367 PrintError(core->vm_info, core, "Could not allocate VMCB, Exiting...\n");
371 if (vm_class == V3_PC_VM) {
372 PrintDebug(core->vm_info, core, "Initializing VMCB (addr=%p)\n", (void *)core->vmm_data);
373 Init_VMCB_BIOS((vmcb_t*)(core->vmm_data), core);
375 PrintError(core->vm_info, core, "Invalid VM class\n");
379 core->core_run_state = CORE_STOPPED;
385 int v3_deinit_svm_vmcb(struct guest_info * core) {
386 V3_FreePages(V3_PAddr(core->vmm_data), 1);
391 #ifdef V3_CONFIG_CHECKPOINT
392 int v3_svm_save_core(struct guest_info * core, void * ctx){
394 vmcb_saved_state_t * guest_area = GET_VMCB_SAVE_STATE_AREA(core->vmm_data);
396 // Special case saves of data we need immediate access to
398 V3_CHKPT_SAVE(ctx, "CPL", core->cpl, failout);
399 V3_CHKPT_SAVE(ctx,"STAR", guest_area->star, failout);
400 V3_CHKPT_SAVE(ctx,"CSTAR", guest_area->cstar, failout);
401 V3_CHKPT_SAVE(ctx,"LSTAR", guest_area->lstar, failout);
402 V3_CHKPT_SAVE(ctx,"SFMASK", guest_area->sfmask, failout);
403 V3_CHKPT_SAVE(ctx,"KERNELGSBASE", guest_area->KernelGsBase, failout);
404 V3_CHKPT_SAVE(ctx,"SYSENTER_CS", guest_area->sysenter_cs, failout);
405 V3_CHKPT_SAVE(ctx,"SYSENTER_ESP", guest_area->sysenter_esp, failout);
406 V3_CHKPT_SAVE(ctx,"SYSENTER_EIP", guest_area->sysenter_eip, failout);
408 // and then we save the whole enchilada
409 if (v3_chkpt_save(ctx, "VMCB_DATA", PAGE_SIZE, core->vmm_data)) {
410 PrintError(core->vm_info, core, "Could not save SVM vmcb\n");
417 PrintError(core->vm_info, core, "Failed to save SVM state for core\n");
422 int v3_svm_load_core(struct guest_info * core, void * ctx){
425 vmcb_saved_state_t * guest_area = GET_VMCB_SAVE_STATE_AREA(core->vmm_data);
427 // Reload what we special cased, which we will overwrite in a minute
428 V3_CHKPT_LOAD(ctx, "CPL", core->cpl, failout);
429 V3_CHKPT_LOAD(ctx,"STAR", guest_area->star, failout);
430 V3_CHKPT_LOAD(ctx,"CSTAR", guest_area->cstar, failout);
431 V3_CHKPT_LOAD(ctx,"LSTAR", guest_area->lstar, failout);
432 V3_CHKPT_LOAD(ctx,"SFMASK", guest_area->sfmask, failout);
433 V3_CHKPT_LOAD(ctx,"KERNELGSBASE", guest_area->KernelGsBase, failout);
434 V3_CHKPT_LOAD(ctx,"SYSENTER_CS", guest_area->sysenter_cs, failout);
435 V3_CHKPT_LOAD(ctx,"SYSENTER_ESP", guest_area->sysenter_esp, failout);
436 V3_CHKPT_LOAD(ctx,"SYSENTER_EIP", guest_area->sysenter_eip, failout);
438 // and then we load the whole enchilada
439 if (v3_chkpt_load(ctx, "VMCB_DATA", PAGE_SIZE, core->vmm_data)) {
440 PrintError(core->vm_info, core, "Could not load SVM vmcb\n");
447 PrintError(core->vm_info, core, "Failed to save SVM state for core\n");
453 static int update_irq_exit_state(struct guest_info * info) {
454 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
456 // Fix for QEMU bug using EVENTINJ as an internal cache
457 guest_ctrl->EVENTINJ.valid = 0;
459 if ((info->intr_core_state.irq_pending == 1) && (guest_ctrl->guest_ctrl.V_IRQ == 0)) {
461 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
462 PrintDebug(info->vm_info, info, "INTAK cycle completed for irq %d\n", info->intr_core_state.irq_vector);
465 info->intr_core_state.irq_started = 1;
466 info->intr_core_state.irq_pending = 0;
468 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
471 if ((info->intr_core_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 0)) {
472 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
473 PrintDebug(info->vm_info, info, "Interrupt %d taken by guest\n", info->intr_core_state.irq_vector);
476 // Interrupt was taken fully vectored
477 info->intr_core_state.irq_started = 0;
479 } else if ((info->intr_core_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 1)) {
480 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
481 PrintDebug(info->vm_info, info, "EXIT INT INFO is set (vec=%d)\n", guest_ctrl->exit_int_info.vector);
489 static int update_irq_entry_state(struct guest_info * info) {
490 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
493 if (info->intr_core_state.irq_pending == 0) {
494 guest_ctrl->guest_ctrl.V_IRQ = 0;
495 guest_ctrl->guest_ctrl.V_INTR_VECTOR = 0;
498 if (v3_excp_pending(info)) {
499 uint_t excp = v3_get_excp_number(info);
501 guest_ctrl->EVENTINJ.type = SVM_INJECTION_EXCEPTION;
503 if (info->excp_state.excp_error_code_valid) {
504 guest_ctrl->EVENTINJ.error_code = info->excp_state.excp_error_code;
505 guest_ctrl->EVENTINJ.ev = 1;
506 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
507 PrintDebug(info->vm_info, info, "Injecting exception %d with error code %x\n", excp, guest_ctrl->EVENTINJ.error_code);
511 guest_ctrl->EVENTINJ.vector = excp;
513 guest_ctrl->EVENTINJ.valid = 1;
515 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
516 PrintDebug(info->vm_info, info, "<%d> Injecting Exception %d (CR2=%p) (EIP=%p)\n",
517 (int)info->num_exits,
518 guest_ctrl->EVENTINJ.vector,
519 (void *)(addr_t)info->ctrl_regs.cr2,
520 (void *)(addr_t)info->rip);
523 v3_injecting_excp(info, excp);
524 } else if (info->intr_core_state.irq_started == 1) {
525 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
526 PrintDebug(info->vm_info, info, "IRQ pending from previous injection\n");
528 guest_ctrl->guest_ctrl.V_IRQ = 1;
529 guest_ctrl->guest_ctrl.V_INTR_VECTOR = info->intr_core_state.irq_vector;
531 // We ignore the virtual TPR on this injection
532 // TPR/PPR tests have already been done in the APIC.
533 guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
534 guest_ctrl->guest_ctrl.V_INTR_PRIO = info->intr_core_state.irq_vector >> 4 ; // 0xf;
537 switch (v3_intr_pending(info)) {
538 case V3_EXTERNAL_IRQ: {
539 int irq = v3_get_intr(info);
545 guest_ctrl->guest_ctrl.V_IRQ = 1;
546 guest_ctrl->guest_ctrl.V_INTR_VECTOR = irq;
548 // We ignore the virtual TPR on this injection
549 // TPR/PPR tests have already been done in the APIC.
550 guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
551 guest_ctrl->guest_ctrl.V_INTR_PRIO = info->intr_core_state.irq_vector >> 4 ; // 0xf;
553 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
554 PrintDebug(info->vm_info, info, "Injecting Interrupt %d (EIP=%p)\n",
555 guest_ctrl->guest_ctrl.V_INTR_VECTOR,
556 (void *)(addr_t)info->rip);
559 info->intr_core_state.irq_pending = 1;
560 info->intr_core_state.irq_vector = irq;
565 guest_ctrl->EVENTINJ.type = SVM_INJECTION_NMI;
567 case V3_SOFTWARE_INTR:
568 guest_ctrl->EVENTINJ.type = SVM_INJECTION_SOFT_INTR;
570 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
571 PrintDebug(info->vm_info, info, "Injecting software interrupt -- type: %d, vector: %d\n",
572 SVM_INJECTION_SOFT_INTR, info->intr_core_state.swintr_vector);
574 guest_ctrl->EVENTINJ.vector = info->intr_core_state.swintr_vector;
575 guest_ctrl->EVENTINJ.valid = 1;
577 /* reset swintr state */
578 info->intr_core_state.swintr_posted = 0;
579 info->intr_core_state.swintr_vector = 0;
583 guest_ctrl->EVENTINJ.type = SVM_INJECTION_IRQ;
586 case V3_INVALID_INTR:
597 v3_svm_config_tsc_virtualization(struct guest_info * info) {
598 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
601 if (info->time_state.flags & VM_TIME_TRAP_RDTSC) {
602 ctrl_area->instrs.RDTSC = 1;
603 ctrl_area->svm_instrs.RDTSCP = 1;
605 ctrl_area->instrs.RDTSC = 0;
606 ctrl_area->svm_instrs.RDTSCP = 0;
608 if (info->time_state.flags & VM_TIME_TSC_PASSTHROUGH) {
609 ctrl_area->TSC_OFFSET = 0;
611 ctrl_area->TSC_OFFSET = v3_tsc_host_offset(&info->time_state);
618 * CAUTION and DANGER!!!
620 * The VMCB CANNOT(!!) be accessed outside of the clgi/stgi calls inside this function
621 * When exectuing a symbiotic call, the VMCB WILL be overwritten, so any dependencies
622 * on its contents will cause things to break. The contents at the time of the exit WILL
623 * change before the exit handler is executed.
625 int v3_svm_enter(struct guest_info * info) {
626 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
627 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
628 addr_t exit_code = 0, exit_info1 = 0, exit_info2 = 0;
629 uint64_t guest_cycles = 0;
631 // Conditionally yield the CPU if the timeslice has expired
634 // Update timer devices after being in the VM before doing
635 // IRQ updates, so that any interrupts they raise get seen
637 v3_advance_time(info, NULL);
638 v3_update_timers(info);
640 // disable global interrupts for vm state transition
643 // Synchronize the guest state to the VMCB
644 guest_state->cr0 = info->ctrl_regs.cr0;
645 guest_state->cr2 = info->ctrl_regs.cr2;
646 guest_state->cr3 = info->ctrl_regs.cr3;
647 guest_state->cr4 = info->ctrl_regs.cr4;
648 guest_state->dr6 = info->dbg_regs.dr6;
649 guest_state->dr7 = info->dbg_regs.dr7;
651 // CR8 is now updated by read/writes and it contains the APIC TPR
652 // the V_TPR should be just the class part of that.
653 // This update is here just for completeness. We currently
654 // are ignoring V_TPR on all injections and doing the priority logivc
656 // guest_ctrl->guest_ctrl.V_TPR = ((info->ctrl_regs.apic_tpr) >> 4) & 0xf;
658 //guest_ctrl->guest_ctrl.V_TPR = info->ctrl_regs.cr8 & 0xff;
661 guest_state->rflags = info->ctrl_regs.rflags;
662 guest_state->efer = info->ctrl_regs.efer;
664 /* Synchronize MSRs */
665 guest_state->star = info->msrs.star;
666 guest_state->lstar = info->msrs.lstar;
667 guest_state->sfmask = info->msrs.sfmask;
668 guest_state->KernelGsBase = info->msrs.kern_gs_base;
670 guest_state->cpl = info->cpl;
672 v3_set_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
674 guest_state->rax = info->vm_regs.rax;
675 guest_state->rip = info->rip;
676 guest_state->rsp = info->vm_regs.rsp;
678 V3_FP_ENTRY_RESTORE(info);
680 #ifdef V3_CONFIG_SYMCALL
681 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
682 update_irq_entry_state(info);
685 update_irq_entry_state(info);
688 #ifdef V3_CONFIG_TM_FUNC
689 v3_tm_check_intr_state(info, guest_ctrl, guest_state);
696 PrintDebug(info->vm_info, info, "SVM Entry to CS=%p rip=%p...\n",
697 (void *)(addr_t)info->segments.cs.base,
698 (void *)(addr_t)info->rip);
701 #ifdef V3_CONFIG_SYMCALL
702 if (info->sym_core_state.symcall_state.sym_call_active == 1) {
703 if (guest_ctrl->guest_ctrl.V_IRQ == 1) {
704 V3_Print(info->vm_info, info, "!!! Injecting Interrupt during Sym call !!!\n");
709 v3_svm_config_tsc_virtualization(info);
711 //V3_Print(info->vm_info, info, "Calling v3_svm_launch\n");
713 uint64_t entry_tsc = 0;
714 uint64_t exit_tsc = 0;
716 #ifdef V3_CONFIG_PWRSTAT_TELEMETRY
717 v3_pwrstat_telemetry_enter(info);
720 #ifdef V3_CONFIG_PMU_TELEMETRY
721 v3_pmu_telemetry_enter(info);
727 v3_svm_launch((vmcb_t *)V3_PAddr(info->vmm_data), &(info->vm_regs), (vmcb_t *)host_vmcbs[V3_Get_CPU()]);
731 #ifdef V3_CONFIG_PMU_TELEMETRY
732 v3_pmu_telemetry_exit(info);
735 #ifdef V3_CONFIG_PWRSTAT_TELEMETRY
736 v3_pwrstat_telemetry_exit(info);
739 guest_cycles = exit_tsc - entry_tsc;
743 //V3_Print(info->vm_info, info, "SVM Returned: Exit Code: %x, guest_rip=%lx\n", (uint32_t)(guest_ctrl->exit_code), (unsigned long)guest_state->rip);
745 v3_last_exit = (uint32_t)(guest_ctrl->exit_code);
747 v3_advance_time(info, &guest_cycles);
751 V3_FP_EXIT_SAVE(info);
753 // Save Guest state from VMCB
754 info->rip = guest_state->rip;
755 info->vm_regs.rsp = guest_state->rsp;
756 info->vm_regs.rax = guest_state->rax;
758 info->cpl = guest_state->cpl;
760 info->ctrl_regs.cr0 = guest_state->cr0;
761 info->ctrl_regs.cr2 = guest_state->cr2;
762 info->ctrl_regs.cr3 = guest_state->cr3;
763 info->ctrl_regs.cr4 = guest_state->cr4;
764 info->dbg_regs.dr6 = guest_state->dr6;
765 info->dbg_regs.dr7 = guest_state->dr7;
767 // We do not track this anymore
768 // V_TPR is ignored and we do the logic in the APIC
769 //info->ctrl_regs.cr8 = guest_ctrl->guest_ctrl.V_TPR;
771 info->ctrl_regs.rflags = guest_state->rflags;
772 info->ctrl_regs.efer = guest_state->efer;
774 /* Synchronize MSRs */
775 info->msrs.star = guest_state->star;
776 info->msrs.lstar = guest_state->lstar;
777 info->msrs.sfmask = guest_state->sfmask;
778 info->msrs.kern_gs_base = guest_state->KernelGsBase;
780 v3_get_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
781 info->cpu_mode = v3_get_vm_cpu_mode(info);
782 info->mem_mode = v3_get_vm_mem_mode(info);
785 // save exit info here
786 exit_code = guest_ctrl->exit_code;
787 exit_info1 = guest_ctrl->exit_info1;
788 exit_info2 = guest_ctrl->exit_info2;
790 #ifdef V3_CONFIG_SYMCALL
791 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
792 update_irq_exit_state(info);
795 update_irq_exit_state(info);
798 // reenable global interrupts after vm exit
801 // Conditionally yield the CPU if the timeslice has expired
804 // This update timers is for time-dependent handlers
805 // if we're slaved to host time
806 v3_advance_time(info, NULL);
807 v3_update_timers(info);
810 int ret = v3_handle_svm_exit(info, exit_code, exit_info1, exit_info2);
813 PrintError(info->vm_info, info, "Error in SVM exit handler (ret=%d)\n", ret);
814 PrintError(info->vm_info, info, " last Exit was %d (exit code=0x%llx)\n", v3_last_exit, (uint64_t) exit_code);
819 if (info->timeouts.timeout_active) {
820 /* Check to see if any timeouts have expired */
821 v3_handle_timeouts(info, guest_cycles);
829 int v3_start_svm_guest(struct guest_info * info) {
830 // vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
831 // vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
833 PrintDebug(info->vm_info, info, "Starting SVM core %u (on logical core %u)\n", info->vcpu_id, info->pcpu_id);
837 if (info->core_run_state == CORE_STOPPED) {
839 if (info->vcpu_id == 0) {
840 info->core_run_state = CORE_RUNNING;
842 PrintDebug(info->vm_info, info, "SVM core %u (on %u): Waiting for core initialization\n", info->vcpu_id, info->pcpu_id);
846 while (info->core_run_state == CORE_STOPPED) {
848 if (info->vm_info->run_state == VM_STOPPED) {
849 // The VM was stopped before this core was initialized.
853 V3_STILL_NO_WORK(info);
855 //PrintDebug(info->vm_info, info, "SVM core %u: still waiting for INIT\n", info->vcpu_id);
858 V3_HAVE_WORK_AGAIN(info);
860 PrintDebug(info->vm_info, info, "SVM core %u(on %u) initialized\n", info->vcpu_id, info->pcpu_id);
862 // We'll be paranoid about race conditions here
863 v3_wait_at_barrier(info);
866 PrintDebug(info->vm_info, info, "SVM core %u(on %u): I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
867 info->vcpu_id, info->pcpu_id,
868 info->segments.cs.selector, (void *)(info->segments.cs.base),
869 info->segments.cs.limit, (void *)(info->rip));
873 PrintDebug(info->vm_info, info, "SVM core %u: Launching SVM VM (vmcb=%p) (on cpu %u)\n",
874 info->vcpu_id, (void *)info->vmm_data, info->pcpu_id);
875 //PrintDebugVMCB((vmcb_t*)(info->vmm_data));
880 if (info->vm_info->run_state == VM_STOPPED) {
881 info->core_run_state = CORE_STOPPED;
886 #ifdef V3_CONFIG_PMU_TELEMETRY
887 v3_pmu_telemetry_start(info);
890 #ifdef V3_CONFIG_PWRSTAT_TELEMETRY
891 v3_pwrstat_telemetry_start(info);
894 if (v3_svm_enter(info) == -1) {
895 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
897 addr_t linear_addr = 0;
899 info->vm_info->run_state = VM_ERROR;
901 V3_Print(info->vm_info, info, "SVM core %u: SVM ERROR!!\n", info->vcpu_id);
903 v3_print_guest_state(info);
905 V3_Print(info->vm_info, info, "SVM core %u: SVM Exit Code: %p\n", info->vcpu_id, (void *)(addr_t)guest_ctrl->exit_code);
907 V3_Print(info->vm_info, info, "SVM core %u: exit_info1 low = 0x%.8x\n", info->vcpu_id, *(uint_t*)&(guest_ctrl->exit_info1));
908 V3_Print(info->vm_info, info, "SVM core %u: exit_info1 high = 0x%.8x\n", info->vcpu_id, *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info1)) + 4));
910 V3_Print(info->vm_info, info, "SVM core %u: exit_info2 low = 0x%.8x\n", info->vcpu_id, *(uint_t*)&(guest_ctrl->exit_info2));
911 V3_Print(info->vm_info, info, "SVM core %u: exit_info2 high = 0x%.8x\n", info->vcpu_id, *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info2)) + 4));
913 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
915 if (info->mem_mode == PHYSICAL_MEM) {
916 v3_gpa_to_hva(info, linear_addr, &host_addr);
917 } else if (info->mem_mode == VIRTUAL_MEM) {
918 v3_gva_to_hva(info, linear_addr, &host_addr);
921 V3_Print(info->vm_info, info, "SVM core %u: Host Address of rip = 0x%p\n", info->vcpu_id, (void *)host_addr);
923 V3_Print(info->vm_info, info, "SVM core %u: Instr (15 bytes) at %p:\n", info->vcpu_id, (void *)host_addr);
924 v3_dump_mem((uint8_t *)host_addr, 15);
926 v3_print_stack(info);
931 v3_wait_at_barrier(info);
934 if (info->vm_info->run_state == VM_STOPPED) {
935 info->core_run_state = CORE_STOPPED;
942 if ((info->num_exits % 50000) == 0) {
943 V3_Print(info->vm_info, info, "SVM Exit number %d\n", (uint32_t)info->num_exits);
944 v3_print_guest_state(info);
950 #ifdef V3_CONFIG_PMU_TELEMETRY
951 v3_pmu_telemetry_end(info);
954 #ifdef V3_CONFIG_PWRSTAT_TELEMETRY
955 v3_pwrstat_telemetry_end(info);
957 // Need to take down the other cores on error...
965 int v3_reset_svm_vm_core(struct guest_info * core, addr_t rip) {
968 // Write the RIP, CS, and descriptor
969 // assume the rest is already good to go
971 // vector VV -> rip at 0
973 // This means we start executing at linear address VV000
975 // So the selector needs to be VV00
976 // and the base needs to be VV000
979 core->segments.cs.selector = rip << 8;
980 core->segments.cs.limit = 0xffff;
981 core->segments.cs.base = rip << 12;
991 /* Checks machine SVM capability */
992 /* Implemented from: AMD Arch Manual 3, sect 15.4 */
993 int v3_is_svm_capable() {
994 uint_t vm_cr_low = 0, vm_cr_high = 0;
995 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
997 v3_cpuid(CPUID_EXT_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
999 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_EXT_FEATURE_IDS_ecx=0x%x\n", ecx);
1001 if ((ecx & CPUID_EXT_FEATURE_IDS_ecx_svm_avail) == 0) {
1002 V3_Print(VM_NONE, VCORE_NONE, "SVM Not Available\n");
1005 v3_get_msr(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
1007 PrintDebug(VM_NONE, VCORE_NONE, "SVM_VM_CR_MSR = 0x%x 0x%x\n", vm_cr_high, vm_cr_low);
1009 if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 1) {
1010 V3_Print(VM_NONE, VCORE_NONE, "SVM is available but is disabled.\n");
1012 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
1014 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
1016 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
1017 V3_Print(VM_NONE, VCORE_NONE, "SVM BIOS Disabled, not unlockable\n");
1019 V3_Print(VM_NONE, VCORE_NONE, "SVM is locked with a key\n");
1024 V3_Print(VM_NONE, VCORE_NONE, "SVM is available and enabled.\n");
1026 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
1027 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_eax=0x%x\n", eax);
1028 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_ebx=0x%x\n", ebx);
1029 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_ecx=0x%x\n", ecx);
1030 PrintDebug(VM_NONE, VCORE_NONE, "CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
1037 static int has_svm_nested_paging() {
1038 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1040 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
1042 //PrintDebug(VM_NONE, VCORE_NONE, "CPUID_EXT_FEATURE_IDS_edx=0x%x\n", edx);
1044 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
1045 V3_Print(VM_NONE, VCORE_NONE, "SVM Nested Paging not supported\n");
1048 V3_Print(VM_NONE, VCORE_NONE, "SVM Nested Paging supported\n");
1055 void v3_init_svm_cpu(int cpu_id) {
1057 extern v3_cpu_arch_t v3_cpu_types[];
1059 // Enable SVM on the CPU
1060 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
1061 msr.e_reg.low |= EFER_MSR_svm_enable;
1062 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
1064 V3_Print(VM_NONE, VCORE_NONE, "SVM Enabled\n");
1066 // Setup the host state save area
1067 host_vmcbs[cpu_id] = (addr_t)V3_AllocPages(4); // need not be shadow-safe, not exposed to guest
1069 if (!host_vmcbs[cpu_id]) {
1070 PrintError(VM_NONE, VCORE_NONE, "Failed to allocate VMCB\n");
1075 // msr.e_reg.high = 0;
1076 //msr.e_reg.low = (uint_t)host_vmcb;
1077 msr.r_reg = host_vmcbs[cpu_id];
1079 PrintDebug(VM_NONE, VCORE_NONE, "Host State being saved at %p\n", (void *)host_vmcbs[cpu_id]);
1080 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
1083 if (has_svm_nested_paging() == 1) {
1084 v3_cpu_types[cpu_id] = V3_SVM_REV3_CPU;
1086 v3_cpu_types[cpu_id] = V3_SVM_CPU;
1092 void v3_deinit_svm_cpu(int cpu_id) {
1094 extern v3_cpu_arch_t v3_cpu_types[];
1096 // reset SVM_VM_HSAVE_PA_MSR
1097 // Does setting it to NULL disable??
1099 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
1102 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
1103 msr.e_reg.low &= ~EFER_MSR_svm_enable;
1104 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
1106 v3_cpu_types[cpu_id] = V3_INVALID_CPU;
1108 V3_FreePages((void *)host_vmcbs[cpu_id], 4);
1110 V3_Print(VM_NONE, VCORE_NONE, "Host CPU %d host area freed, and SVM disabled\n", cpu_id);
1165 * Test VMSAVE/VMLOAD Latency
1167 #define vmsave ".byte 0x0F,0x01,0xDB ; "
1168 #define vmload ".byte 0x0F,0x01,0xDA ; "
1170 uint32_t start_lo, start_hi;
1171 uint32_t end_lo, end_hi;
1172 uint64_t start, end;
1174 __asm__ __volatile__ (
1176 "movl %%eax, %%esi ; "
1177 "movl %%edx, %%edi ; "
1178 "movq %%rcx, %%rax ; "
1181 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
1182 : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
1193 PrintDebug(core->vm_info, core, "VMSave Cycle Latency: %d\n", (uint32_t)(end - start));
1195 __asm__ __volatile__ (
1197 "movl %%eax, %%esi ; "
1198 "movl %%edx, %%edi ; "
1199 "movq %%rcx, %%rax ; "
1202 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
1203 : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
1215 PrintDebug(core->vm_info, core, "VMLoad Cycle Latency: %d\n", (uint32_t)(end - start));
1217 /* End Latency Test */
1228 void Init_VMCB_pe(vmcb_t *vmcb, struct guest_info vm_info) {
1229 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
1230 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
1234 guest_state->rsp = vm_info.vm_regs.rsp;
1235 guest_state->rip = vm_info.rip;
1238 /* I pretty much just gutted this from TVMM */
1239 /* Note: That means its probably wrong */
1241 // set the segment registers to mirror ours
1242 guest_state->cs.selector = 1<<3;
1243 guest_state->cs.attrib.fields.type = 0xa; // Code segment+read
1244 guest_state->cs.attrib.fields.S = 1;
1245 guest_state->cs.attrib.fields.P = 1;
1246 guest_state->cs.attrib.fields.db = 1;
1247 guest_state->cs.attrib.fields.G = 1;
1248 guest_state->cs.limit = 0xfffff;
1249 guest_state->cs.base = 0;
1251 struct vmcb_selector *segregs [] = {&(guest_state->ss), &(guest_state->ds), &(guest_state->es), &(guest_state->fs), &(guest_state->gs), NULL};
1252 for ( i = 0; segregs[i] != NULL; i++) {
1253 struct vmcb_selector * seg = segregs[i];
1255 seg->selector = 2<<3;
1256 seg->attrib.fields.type = 0x2; // Data Segment+read/write
1257 seg->attrib.fields.S = 1;
1258 seg->attrib.fields.P = 1;
1259 seg->attrib.fields.db = 1;
1260 seg->attrib.fields.G = 1;
1261 seg->limit = 0xfffff;
1267 /* JRL THIS HAS TO GO */
1269 // guest_state->tr.selector = GetTR_Selector();
1270 guest_state->tr.attrib.fields.type = 0x9;
1271 guest_state->tr.attrib.fields.P = 1;
1272 // guest_state->tr.limit = GetTR_Limit();
1273 //guest_state->tr.base = GetTR_Base();// - 0x2000;
1281 guest_state->efer |= EFER_MSR_svm_enable;
1282 guest_state->rflags = 0x00000002; // The reserved bit is always 1
1283 ctrl_area->svm_instrs.VMRUN = 1;
1284 guest_state->cr0 = 0x00000001; // PE
1285 ctrl_area->guest_ASID = 1;
1288 // guest_state->cpl = 0;
1294 ctrl_area->cr_writes.cr4 = 1;
1296 ctrl_area->exceptions.de = 1;
1297 ctrl_area->exceptions.df = 1;
1298 ctrl_area->exceptions.pf = 1;
1299 ctrl_area->exceptions.ts = 1;
1300 ctrl_area->exceptions.ss = 1;
1301 ctrl_area->exceptions.ac = 1;
1302 ctrl_area->exceptions.mc = 1;
1303 ctrl_area->exceptions.gp = 1;
1304 ctrl_area->exceptions.ud = 1;
1305 ctrl_area->exceptions.np = 1;
1306 ctrl_area->exceptions.of = 1;
1307 ctrl_area->exceptions.nmi = 1;
1311 ctrl_area->instrs.IOIO_PROT = 1;
1312 ctrl_area->IOPM_BASE_PA = (uint_t)V3_AllocPages(3); // need not be shadow-safe, not exposed to guest
1314 if (!ctrl_area->IOPM_BASE_PA) {
1315 PrintError(core->vm_info, core, "Cannot allocate IO bitmap\n");
1321 tmp_reg.r_reg = ctrl_area->IOPM_BASE_PA;
1322 memset((void*)(tmp_reg.e_reg.low), 0xffffffff, PAGE_SIZE * 2);
1325 ctrl_area->instrs.INTR = 1;
1332 memset(gdt_buf, 0, 6);
1333 memset(idt_buf, 0, 6);
1336 uint_t gdt_base, idt_base;
1337 ushort_t gdt_limit, idt_limit;
1340 gdt_base = *(ulong_t*)((uchar_t*)gdt_buf + 2) & 0xffffffff;
1341 gdt_limit = *(ushort_t*)(gdt_buf) & 0xffff;
1342 PrintDebug(core->vm_info, core, "GDT: base: %x, limit: %x\n", gdt_base, gdt_limit);
1345 idt_base = *(ulong_t*)(idt_buf + 2) & 0xffffffff;
1346 idt_limit = *(ushort_t*)(idt_buf) & 0xffff;
1347 PrintDebug(core->vm_info, core, "IDT: base: %x, limit: %x\n",idt_base, idt_limit);
1350 // gdt_base -= 0x2000;
1351 //idt_base -= 0x2000;
1353 guest_state->gdtr.base = gdt_base;
1354 guest_state->gdtr.limit = gdt_limit;
1355 guest_state->idtr.base = idt_base;
1356 guest_state->idtr.limit = idt_limit;
1362 // also determine if CPU supports nested paging
1364 if (vm_info.page_tables) {
1366 // Flush the TLB on entries/exits
1367 ctrl_area->TLB_CONTROL = 1;
1369 // Enable Nested Paging
1370 ctrl_area->NP_ENABLE = 1;
1372 PrintDebug(core->vm_info, core, "NP_Enable at 0x%x\n", &(ctrl_area->NP_ENABLE));
1374 // Set the Nested Page Table pointer
1375 ctrl_area->N_CR3 |= ((addr_t)vm_info.page_tables & 0xfffff000);
1378 // ctrl_area->N_CR3 = Get_CR3();
1379 // guest_state->cr3 |= (Get_CR3() & 0xfffff000);
1381 guest_state->g_pat = 0x7040600070406ULL;
1383 PrintDebug(core->vm_info, core, "Set Nested CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(ctrl_area->N_CR3)), (uint_t)*((unsigned char *)&(ctrl_area->N_CR3) + 4));
1384 PrintDebug(core->vm_info, core, "Set Guest CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(guest_state->cr3)), (uint_t)*((unsigned char *)&(guest_state->cr3) + 4));
1386 // guest_state->cr0 |= 0x80000000;