2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/svm.h>
22 #include <palacios/vmm.h>
24 #include <palacios/vmcb.h>
25 #include <palacios/vmm_mem.h>
26 #include <palacios/vmm_paging.h>
27 #include <palacios/svm_handler.h>
29 #include <palacios/vmm_debug.h>
30 #include <palacios/vm_guest_mem.h>
32 #include <palacios/vmm_decoder.h>
33 #include <palacios/vmm_string.h>
34 #include <palacios/vmm_lowlevel.h>
35 #include <palacios/svm_msr.h>
37 #include <palacios/vmm_rbtree.h>
38 #include <palacios/vmm_barrier.h>
40 #ifdef V3_CONFIG_CHECKPOINT
41 #include <palacios/vmm_checkpoint.h>
44 #include <palacios/vmm_direct_paging.h>
46 #include <palacios/vmm_ctrl_regs.h>
47 #include <palacios/svm_io.h>
49 #include <palacios/vmm_sprintf.h>
52 #ifndef V3_CONFIG_DEBUG_SVM
54 #define PrintDebug(fmt, args...)
58 uint32_t v3_last_exit;
60 // This is a global pointer to the host's VMCB
61 static addr_t host_vmcbs[V3_CONFIG_MAX_CPUS] = { [0 ... V3_CONFIG_MAX_CPUS - 1] = 0};
65 extern void v3_stgi();
66 extern void v3_clgi();
67 //extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, uint64_t * fs, uint64_t * gs);
68 extern int v3_svm_launch(vmcb_t * vmcb, struct v3_gprs * vm_regs, vmcb_t * host_vmcb);
71 static vmcb_t * Allocate_VMCB() {
72 vmcb_t * vmcb_page = NULL;
73 addr_t vmcb_pa = (addr_t)V3_AllocPages(1);
75 if ((void *)vmcb_pa == NULL) {
76 PrintError("Error allocating VMCB\n");
80 vmcb_page = (vmcb_t *)V3_VAddr((void *)vmcb_pa);
82 memset(vmcb_page, 0, 4096);
88 static int v3_svm_handle_efer_write(struct guest_info * core, uint_t msr, struct v3_msr src, void * priv_data)
92 // Call arch-independent handler
93 if ((status = v3_handle_efer_write(core, msr, src, priv_data)) != 0) {
99 // Ensure that hardware visible EFER.SVME bit is set (SVM Enable)
100 struct efer_64 * hw_efer = (struct efer_64 *)&(core->ctrl_regs.efer);
108 static void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info * core) {
109 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
110 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
115 ctrl_area->svm_instrs.VMRUN = 1;
116 ctrl_area->svm_instrs.VMMCALL = 1;
117 ctrl_area->svm_instrs.VMLOAD = 1;
118 ctrl_area->svm_instrs.VMSAVE = 1;
119 ctrl_area->svm_instrs.STGI = 1;
120 ctrl_area->svm_instrs.CLGI = 1;
121 ctrl_area->svm_instrs.SKINIT = 1;
122 ctrl_area->svm_instrs.ICEBP = 1;
123 ctrl_area->svm_instrs.WBINVD = 1;
124 ctrl_area->svm_instrs.MONITOR = 1;
125 ctrl_area->svm_instrs.MWAIT_always = 1;
126 ctrl_area->svm_instrs.MWAIT_if_armed = 1;
127 ctrl_area->instrs.INVLPGA = 1;
128 ctrl_area->instrs.CPUID = 1;
130 ctrl_area->instrs.HLT = 1;
132 /* Set at VMM launch as needed */
133 ctrl_area->instrs.RDTSC = 0;
134 ctrl_area->svm_instrs.RDTSCP = 0;
136 // guest_state->cr0 = 0x00000001; // PE
139 ctrl_area->exceptions.de = 1;
140 ctrl_area->exceptions.df = 1;
142 ctrl_area->exceptions.ts = 1;
143 ctrl_area->exceptions.ss = 1;
144 ctrl_area->exceptions.ac = 1;
145 ctrl_area->exceptions.mc = 1;
146 ctrl_area->exceptions.gp = 1;
147 ctrl_area->exceptions.ud = 1;
148 ctrl_area->exceptions.np = 1;
149 ctrl_area->exceptions.of = 1;
151 ctrl_area->exceptions.nmi = 1;
155 ctrl_area->instrs.NMI = 1;
156 ctrl_area->instrs.SMI = 0; // allow SMIs to run in guest
157 ctrl_area->instrs.INIT = 1;
158 // ctrl_area->instrs.PAUSE = 1;
159 ctrl_area->instrs.shutdown_evts = 1;
162 /* DEBUG FOR RETURN CODE */
163 ctrl_area->exit_code = 1;
166 /* Setup Guest Machine state */
168 core->vm_regs.rsp = 0x00;
171 core->vm_regs.rdx = 0x00000f00;
176 core->ctrl_regs.rflags = 0x00000002; // The reserved bit is always 1
177 core->ctrl_regs.cr0 = 0x60010010; // Set the WP flag so the memory hooks work in real-mode
178 core->ctrl_regs.efer |= EFER_MSR_svm_enable;
184 core->segments.cs.selector = 0xf000;
185 core->segments.cs.limit = 0xffff;
186 core->segments.cs.base = 0x0000000f0000LL;
188 // (raw attributes = 0xf3)
189 core->segments.cs.type = 0x3;
190 core->segments.cs.system = 0x1;
191 core->segments.cs.dpl = 0x3;
192 core->segments.cs.present = 1;
196 struct v3_segment * segregs [] = {&(core->segments.ss), &(core->segments.ds),
197 &(core->segments.es), &(core->segments.fs),
198 &(core->segments.gs), NULL};
200 for ( i = 0; segregs[i] != NULL; i++) {
201 struct v3_segment * seg = segregs[i];
203 seg->selector = 0x0000;
204 // seg->base = seg->selector << 4;
205 seg->base = 0x00000000;
208 // (raw attributes = 0xf3)
215 core->segments.gdtr.limit = 0x0000ffff;
216 core->segments.gdtr.base = 0x0000000000000000LL;
217 core->segments.idtr.limit = 0x0000ffff;
218 core->segments.idtr.base = 0x0000000000000000LL;
220 core->segments.ldtr.selector = 0x0000;
221 core->segments.ldtr.limit = 0x0000ffff;
222 core->segments.ldtr.base = 0x0000000000000000LL;
223 core->segments.tr.selector = 0x0000;
224 core->segments.tr.limit = 0x0000ffff;
225 core->segments.tr.base = 0x0000000000000000LL;
228 core->dbg_regs.dr6 = 0x00000000ffff0ff0LL;
229 core->dbg_regs.dr7 = 0x0000000000000400LL;
232 ctrl_area->IOPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->io_map.arch_data);
233 ctrl_area->instrs.IOIO_PROT = 1;
235 ctrl_area->MSRPM_BASE_PA = (addr_t)V3_PAddr(core->vm_info->msr_map.arch_data);
236 ctrl_area->instrs.MSR_PROT = 1;
239 PrintDebug("Exiting on interrupts\n");
240 ctrl_area->guest_ctrl.V_INTR_MASKING = 1;
241 ctrl_area->instrs.INTR = 1;
244 v3_hook_msr(core->vm_info, EFER_MSR,
245 &v3_handle_efer_read,
246 &v3_svm_handle_efer_write,
249 if (core->shdw_pg_mode == SHADOW_PAGING) {
250 PrintDebug("Creating initial shadow page table\n");
252 /* JRL: This is a performance killer, and a simplistic solution */
253 /* We need to fix this */
254 ctrl_area->TLB_CONTROL = 1;
255 ctrl_area->guest_ASID = 1;
258 if (v3_init_passthrough_pts(core) == -1) {
259 PrintError("Could not initialize passthrough page tables\n");
264 core->shdw_pg_state.guest_cr0 = 0x0000000000000010LL;
265 PrintDebug("Created\n");
267 core->ctrl_regs.cr0 |= 0x80000000;
268 core->ctrl_regs.cr3 = core->direct_map_pt;
270 ctrl_area->cr_reads.cr0 = 1;
271 ctrl_area->cr_writes.cr0 = 1;
272 //ctrl_area->cr_reads.cr4 = 1;
273 ctrl_area->cr_writes.cr4 = 1;
274 ctrl_area->cr_reads.cr3 = 1;
275 ctrl_area->cr_writes.cr3 = 1;
279 ctrl_area->instrs.INVLPG = 1;
281 ctrl_area->exceptions.pf = 1;
283 guest_state->g_pat = 0x7040600070406ULL;
287 } else if (core->shdw_pg_mode == NESTED_PAGING) {
288 // Flush the TLB on entries/exits
289 ctrl_area->TLB_CONTROL = 1;
290 ctrl_area->guest_ASID = 1;
292 // Enable Nested Paging
293 ctrl_area->NP_ENABLE = 1;
295 PrintDebug("NP_Enable at 0x%p\n", (void *)&(ctrl_area->NP_ENABLE));
297 // Set the Nested Page Table pointer
298 if (v3_init_passthrough_pts(core) == -1) {
299 PrintError("Could not initialize Nested page tables\n");
303 ctrl_area->N_CR3 = core->direct_map_pt;
305 guest_state->g_pat = 0x7040600070406ULL;
308 /* tell the guest that we don't support SVM */
309 v3_hook_msr(core->vm_info, SVM_VM_CR_MSR,
310 &v3_handle_vm_cr_read,
311 &v3_handle_vm_cr_write,
316 #define INT_PENDING_AMD_MSR 0xc0010055
318 v3_hook_msr(core->vm_info, IA32_STAR_MSR, NULL, NULL, NULL);
319 v3_hook_msr(core->vm_info, IA32_LSTAR_MSR, NULL, NULL, NULL);
320 v3_hook_msr(core->vm_info, IA32_FMASK_MSR, NULL, NULL, NULL);
321 v3_hook_msr(core->vm_info, IA32_KERN_GS_BASE_MSR, NULL, NULL, NULL);
322 v3_hook_msr(core->vm_info, IA32_CSTAR_MSR, NULL, NULL, NULL);
324 v3_hook_msr(core->vm_info, SYSENTER_CS_MSR, NULL, NULL, NULL);
325 v3_hook_msr(core->vm_info, SYSENTER_ESP_MSR, NULL, NULL, NULL);
326 v3_hook_msr(core->vm_info, SYSENTER_EIP_MSR, NULL, NULL, NULL);
329 v3_hook_msr(core->vm_info, FS_BASE_MSR, NULL, NULL, NULL);
330 v3_hook_msr(core->vm_info, GS_BASE_MSR, NULL, NULL, NULL);
332 // Passthrough read operations are ok.
333 v3_hook_msr(core->vm_info, INT_PENDING_AMD_MSR, NULL, v3_msr_unhandled_write, NULL);
338 int v3_init_svm_vmcb(struct guest_info * core, v3_vm_class_t vm_class) {
340 PrintDebug("Allocating VMCB\n");
341 core->vmm_data = (void *)Allocate_VMCB();
343 if (core->vmm_data == NULL) {
344 PrintError("Could not allocate VMCB, Exiting...\n");
348 if (vm_class == V3_PC_VM) {
349 PrintDebug("Initializing VMCB (addr=%p)\n", (void *)core->vmm_data);
350 Init_VMCB_BIOS((vmcb_t*)(core->vmm_data), core);
352 PrintError("Invalid VM class\n");
360 int v3_deinit_svm_vmcb(struct guest_info * core) {
361 V3_FreePages(V3_PAddr(core->vmm_data), 1);
366 #ifdef V3_CONFIG_CHECKPOINT
367 int v3_svm_save_core(struct guest_info * core, void * ctx){
369 v3_chkpt_save_8(ctx, "cpl", &(core->cpl));
370 v3_chkpt_save(ctx, "vmcb_data", PAGE_SIZE, core->vmm_data);
375 int v3_svm_load_core(struct guest_info * core, void * ctx){
377 v3_chkpt_load_8(ctx, "cpl", &(core->cpl));
379 if (v3_chkpt_load(ctx, "vmcb_data", PAGE_SIZE, core->vmm_data) == -1) {
387 static int update_irq_exit_state(struct guest_info * info) {
388 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
390 // Fix for QEMU bug using EVENTINJ as an internal cache
391 guest_ctrl->EVENTINJ.valid = 0;
393 if ((info->intr_core_state.irq_pending == 1) && (guest_ctrl->guest_ctrl.V_IRQ == 0)) {
395 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
396 PrintDebug("INTAK cycle completed for irq %d\n", info->intr_core_state.irq_vector);
399 info->intr_core_state.irq_started = 1;
400 info->intr_core_state.irq_pending = 0;
402 v3_injecting_intr(info, info->intr_core_state.irq_vector, V3_EXTERNAL_IRQ);
405 if ((info->intr_core_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 0)) {
406 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
407 PrintDebug("Interrupt %d taken by guest\n", info->intr_core_state.irq_vector);
410 // Interrupt was taken fully vectored
411 info->intr_core_state.irq_started = 0;
413 } else if ((info->intr_core_state.irq_started == 1) && (guest_ctrl->exit_int_info.valid == 1)) {
414 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
415 PrintDebug("EXIT INT INFO is set (vec=%d)\n", guest_ctrl->exit_int_info.vector);
423 static int update_irq_entry_state(struct guest_info * info) {
424 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
427 if (info->intr_core_state.irq_pending == 0) {
428 guest_ctrl->guest_ctrl.V_IRQ = 0;
429 guest_ctrl->guest_ctrl.V_INTR_VECTOR = 0;
432 if (v3_excp_pending(info)) {
433 uint_t excp = v3_get_excp_number(info);
435 guest_ctrl->EVENTINJ.type = SVM_INJECTION_EXCEPTION;
437 if (info->excp_state.excp_error_code_valid) {
438 guest_ctrl->EVENTINJ.error_code = info->excp_state.excp_error_code;
439 guest_ctrl->EVENTINJ.ev = 1;
440 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
441 PrintDebug("Injecting exception %d with error code %x\n", excp, guest_ctrl->EVENTINJ.error_code);
445 guest_ctrl->EVENTINJ.vector = excp;
447 guest_ctrl->EVENTINJ.valid = 1;
449 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
450 PrintDebug("<%d> Injecting Exception %d (CR2=%p) (EIP=%p)\n",
451 (int)info->num_exits,
452 guest_ctrl->EVENTINJ.vector,
453 (void *)(addr_t)info->ctrl_regs.cr2,
454 (void *)(addr_t)info->rip);
457 v3_injecting_excp(info, excp);
458 } else if (info->intr_core_state.irq_started == 1) {
459 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
460 PrintDebug("IRQ pending from previous injection\n");
462 guest_ctrl->guest_ctrl.V_IRQ = 1;
463 guest_ctrl->guest_ctrl.V_INTR_VECTOR = info->intr_core_state.irq_vector;
464 guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
465 guest_ctrl->guest_ctrl.V_INTR_PRIO = 0xf;
468 switch (v3_intr_pending(info)) {
469 case V3_EXTERNAL_IRQ: {
470 uint32_t irq = v3_get_intr(info);
472 guest_ctrl->guest_ctrl.V_IRQ = 1;
473 guest_ctrl->guest_ctrl.V_INTR_VECTOR = irq;
474 guest_ctrl->guest_ctrl.V_IGN_TPR = 1;
475 guest_ctrl->guest_ctrl.V_INTR_PRIO = 0xf;
477 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
478 PrintDebug("Injecting Interrupt %d (EIP=%p)\n",
479 guest_ctrl->guest_ctrl.V_INTR_VECTOR,
480 (void *)(addr_t)info->rip);
483 info->intr_core_state.irq_pending = 1;
484 info->intr_core_state.irq_vector = irq;
489 guest_ctrl->EVENTINJ.type = SVM_INJECTION_NMI;
491 case V3_SOFTWARE_INTR:
492 guest_ctrl->EVENTINJ.type = SVM_INJECTION_SOFT_INTR;
494 #ifdef V3_CONFIG_DEBUG_INTERRUPTS
495 PrintDebug("Injecting software interrupt -- type: %d, vector: %d\n",
496 SVM_INJECTION_SOFT_INTR, info->intr_core_state.swintr_vector);
498 guest_ctrl->EVENTINJ.vector = info->intr_core_state.swintr_vector;
499 guest_ctrl->EVENTINJ.valid = 1;
501 /* reset swintr state */
502 info->intr_core_state.swintr_posted = 0;
503 info->intr_core_state.swintr_vector = 0;
507 guest_ctrl->EVENTINJ.type = SVM_INJECTION_IRQ;
510 case V3_INVALID_INTR:
521 v3_svm_config_tsc_virtualization(struct guest_info * info) {
522 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
524 if (info->time_state.time_flags & V3_TIME_TRAP_RDTSC) {
525 ctrl_area->instrs.RDTSC = 1;
526 ctrl_area->svm_instrs.RDTSCP = 1;
528 ctrl_area->instrs.RDTSC = 0;
529 ctrl_area->svm_instrs.RDTSCP = 0;
530 ctrl_area->TSC_OFFSET = v3_tsc_host_offset(&info->time_state);
536 * CAUTION and DANGER!!!
538 * The VMCB CANNOT(!!) be accessed outside of the clgi/stgi calls inside this function
539 * When exectuing a symbiotic call, the VMCB WILL be overwritten, so any dependencies
540 * on its contents will cause things to break. The contents at the time of the exit WILL
541 * change before the exit handler is executed.
543 int v3_svm_enter(struct guest_info * info) {
544 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
545 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
546 addr_t exit_code = 0, exit_info1 = 0, exit_info2 = 0;
547 uint64_t guest_cycles = 0;
549 // Conditionally yield the CPU if the timeslice has expired
552 // disable global interrupts for vm state transition
555 // Update timer devices after being in the VM, with interupts
556 // disabled, but before doing IRQ updates, so that any interrupts they
557 //raise get seen immediately.
558 v3_advance_time(info);
559 v3_update_timers(info);
561 // Synchronize the guest state to the VMCB
562 guest_state->cr0 = info->ctrl_regs.cr0;
563 guest_state->cr2 = info->ctrl_regs.cr2;
564 guest_state->cr3 = info->ctrl_regs.cr3;
565 guest_state->cr4 = info->ctrl_regs.cr4;
566 guest_state->dr6 = info->dbg_regs.dr6;
567 guest_state->dr7 = info->dbg_regs.dr7;
568 guest_ctrl->guest_ctrl.V_TPR = info->ctrl_regs.cr8 & 0xff;
569 guest_state->rflags = info->ctrl_regs.rflags;
570 guest_state->efer = info->ctrl_regs.efer;
572 /* Synchronize MSRs */
573 guest_state->star = info->msrs.star;
574 guest_state->lstar = info->msrs.lstar;
575 guest_state->sfmask = info->msrs.sfmask;
576 guest_state->KernelGsBase = info->msrs.kern_gs_base;
578 guest_state->cpl = info->cpl;
580 v3_set_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
582 guest_state->rax = info->vm_regs.rax;
583 guest_state->rip = info->rip;
584 guest_state->rsp = info->vm_regs.rsp;
586 #ifdef V3_CONFIG_SYMCALL
587 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
588 update_irq_entry_state(info);
591 update_irq_entry_state(info);
598 PrintDebug("SVM Entry to CS=%p rip=%p...\n",
599 (void *)(addr_t)info->segments.cs.base,
600 (void *)(addr_t)info->rip);
603 #ifdef V3_CONFIG_SYMCALL
604 if (info->sym_core_state.symcall_state.sym_call_active == 1) {
605 if (guest_ctrl->guest_ctrl.V_IRQ == 1) {
606 V3_Print("!!! Injecting Interrupt during Sym call !!!\n");
611 v3_time_enter_vm(info);
612 v3_svm_config_tsc_virtualization(info);
614 //V3_Print("Calling v3_svm_launch\n");
616 uint64_t entry_tsc = 0;
617 uint64_t exit_tsc = 0;
621 v3_svm_launch((vmcb_t *)V3_PAddr(info->vmm_data), &(info->vm_regs), (vmcb_t *)host_vmcbs[V3_Get_CPU()]);
625 guest_cycles = exit_tsc - entry_tsc;
629 //V3_Print("SVM Returned: Exit Code: %x, guest_rip=%lx\n", (uint32_t)(guest_ctrl->exit_code), (unsigned long)guest_state->rip);
631 v3_last_exit = (uint32_t)(guest_ctrl->exit_code);
633 // Immediate exit from VM time bookkeeping
634 v3_time_exit_vm(info, &guest_cycles);
638 // Save Guest state from VMCB
639 info->rip = guest_state->rip;
640 info->vm_regs.rsp = guest_state->rsp;
641 info->vm_regs.rax = guest_state->rax;
643 info->cpl = guest_state->cpl;
645 info->ctrl_regs.cr0 = guest_state->cr0;
646 info->ctrl_regs.cr2 = guest_state->cr2;
647 info->ctrl_regs.cr3 = guest_state->cr3;
648 info->ctrl_regs.cr4 = guest_state->cr4;
649 info->dbg_regs.dr6 = guest_state->dr6;
650 info->dbg_regs.dr7 = guest_state->dr7;
651 info->ctrl_regs.cr8 = guest_ctrl->guest_ctrl.V_TPR;
652 info->ctrl_regs.rflags = guest_state->rflags;
653 info->ctrl_regs.efer = guest_state->efer;
655 /* Synchronize MSRs */
656 info->msrs.star = guest_state->star;
657 info->msrs.lstar = guest_state->lstar;
658 info->msrs.sfmask = guest_state->sfmask;
659 info->msrs.kern_gs_base = guest_state->KernelGsBase;
661 v3_get_vmcb_segments((vmcb_t*)(info->vmm_data), &(info->segments));
662 info->cpu_mode = v3_get_vm_cpu_mode(info);
663 info->mem_mode = v3_get_vm_mem_mode(info);
666 // save exit info here
667 exit_code = guest_ctrl->exit_code;
668 exit_info1 = guest_ctrl->exit_info1;
669 exit_info2 = guest_ctrl->exit_info2;
671 #ifdef V3_CONFIG_SYMCALL
672 if (info->sym_core_state.symcall_state.sym_call_active == 0) {
673 update_irq_exit_state(info);
676 update_irq_exit_state(info);
679 // reenable global interrupts after vm exit
682 // Conditionally yield the CPU if the timeslice has expired
686 int ret = v3_handle_svm_exit(info, exit_code, exit_info1, exit_info2);
689 PrintError("Error in SVM exit handler (ret=%d)\n", ret);
690 PrintError(" last Exit was %d (exit code=0x%llx)\n", v3_last_exit, (uint64_t) exit_code);
695 if (info->timeouts.timeout_active) {
696 /* Check to see if any timeouts have expired */
697 v3_handle_timeouts(info, guest_cycles);
705 int v3_start_svm_guest(struct guest_info * info) {
706 // vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA((vmcb_t*)(info->vmm_data));
707 // vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
709 PrintDebug("Starting SVM core %u (on logical core %u)\n", info->vcpu_id, info->pcpu_id);
711 if (info->vcpu_id == 0) {
712 info->core_run_state = CORE_RUNNING;
714 PrintDebug("SVM core %u (on %u): Waiting for core initialization\n", info->vcpu_id, info->pcpu_id);
716 while (info->core_run_state == CORE_STOPPED) {
718 if (info->vm_info->run_state == VM_STOPPED) {
719 // The VM was stopped before this core was initialized.
724 //PrintDebug("SVM core %u: still waiting for INIT\n", info->vcpu_id);
727 PrintDebug("SVM core %u(on %u) initialized\n", info->vcpu_id, info->pcpu_id);
729 // We'll be paranoid about race conditions here
730 v3_wait_at_barrier(info);
733 PrintDebug("SVM core %u(on %u): I am starting at CS=0x%x (base=0x%p, limit=0x%x), RIP=0x%p\n",
734 info->vcpu_id, info->pcpu_id,
735 info->segments.cs.selector, (void *)(info->segments.cs.base),
736 info->segments.cs.limit, (void *)(info->rip));
740 PrintDebug("SVM core %u: Launching SVM VM (vmcb=%p) (on cpu %u)\n",
741 info->vcpu_id, (void *)info->vmm_data, info->pcpu_id);
742 //PrintDebugVMCB((vmcb_t*)(info->vmm_data));
748 if (info->vm_info->run_state == VM_STOPPED) {
749 info->core_run_state = CORE_STOPPED;
753 if (v3_svm_enter(info) == -1) {
754 vmcb_ctrl_t * guest_ctrl = GET_VMCB_CTRL_AREA((vmcb_t*)(info->vmm_data));
756 addr_t linear_addr = 0;
758 info->vm_info->run_state = VM_ERROR;
760 V3_Print("SVM core %u: SVM ERROR!!\n", info->vcpu_id);
762 v3_print_guest_state(info);
764 V3_Print("SVM core %u: SVM Exit Code: %p\n", info->vcpu_id, (void *)(addr_t)guest_ctrl->exit_code);
766 V3_Print("SVM core %u: exit_info1 low = 0x%.8x\n", info->vcpu_id, *(uint_t*)&(guest_ctrl->exit_info1));
767 V3_Print("SVM core %u: exit_info1 high = 0x%.8x\n", info->vcpu_id, *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info1)) + 4));
769 V3_Print("SVM core %u: exit_info2 low = 0x%.8x\n", info->vcpu_id, *(uint_t*)&(guest_ctrl->exit_info2));
770 V3_Print("SVM core %u: exit_info2 high = 0x%.8x\n", info->vcpu_id, *(uint_t *)(((uchar_t *)&(guest_ctrl->exit_info2)) + 4));
772 linear_addr = get_addr_linear(info, info->rip, &(info->segments.cs));
774 if (info->mem_mode == PHYSICAL_MEM) {
775 v3_gpa_to_hva(info, linear_addr, &host_addr);
776 } else if (info->mem_mode == VIRTUAL_MEM) {
777 v3_gva_to_hva(info, linear_addr, &host_addr);
780 V3_Print("SVM core %u: Host Address of rip = 0x%p\n", info->vcpu_id, (void *)host_addr);
782 V3_Print("SVM core %u: Instr (15 bytes) at %p:\n", info->vcpu_id, (void *)host_addr);
783 v3_dump_mem((uint8_t *)host_addr, 15);
785 v3_print_stack(info);
790 v3_wait_at_barrier(info);
793 if (info->vm_info->run_state == VM_STOPPED) {
794 info->core_run_state = CORE_STOPPED;
801 if ((info->num_exits % 50000) == 0) {
802 V3_Print("SVM Exit number %d\n", (uint32_t)info->num_exits);
803 v3_print_guest_state(info);
809 // Need to take down the other cores on error...
817 int v3_reset_svm_vm_core(struct guest_info * core, addr_t rip) {
820 // Write the RIP, CS, and descriptor
821 // assume the rest is already good to go
823 // vector VV -> rip at 0
825 // This means we start executing at linear address VV000
827 // So the selector needs to be VV00
828 // and the base needs to be VV000
831 core->segments.cs.selector = rip << 8;
832 core->segments.cs.limit = 0xffff;
833 core->segments.cs.base = rip << 12;
843 /* Checks machine SVM capability */
844 /* Implemented from: AMD Arch Manual 3, sect 15.4 */
845 int v3_is_svm_capable() {
846 uint_t vm_cr_low = 0, vm_cr_high = 0;
847 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
849 v3_cpuid(CPUID_EXT_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
851 PrintDebug("CPUID_EXT_FEATURE_IDS_ecx=0x%x\n", ecx);
853 if ((ecx & CPUID_EXT_FEATURE_IDS_ecx_svm_avail) == 0) {
854 V3_Print("SVM Not Available\n");
857 v3_get_msr(SVM_VM_CR_MSR, &vm_cr_high, &vm_cr_low);
859 PrintDebug("SVM_VM_CR_MSR = 0x%x 0x%x\n", vm_cr_high, vm_cr_low);
861 if ((vm_cr_low & SVM_VM_CR_MSR_svmdis) == 1) {
862 V3_Print("SVM is available but is disabled.\n");
864 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
866 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
868 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml) == 0) {
869 V3_Print("SVM BIOS Disabled, not unlockable\n");
871 V3_Print("SVM is locked with a key\n");
876 V3_Print("SVM is available and enabled.\n");
878 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
879 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_eax=0x%x\n", eax);
880 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ebx=0x%x\n", ebx);
881 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_ecx=0x%x\n", ecx);
882 PrintDebug("CPUID_SVM_REV_AND_FEATURE_IDS_edx=0x%x\n", edx);
889 static int has_svm_nested_paging() {
890 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
892 v3_cpuid(CPUID_SVM_REV_AND_FEATURE_IDS, &eax, &ebx, &ecx, &edx);
894 //PrintDebug("CPUID_EXT_FEATURE_IDS_edx=0x%x\n", edx);
896 if ((edx & CPUID_SVM_REV_AND_FEATURE_IDS_edx_np) == 0) {
897 V3_Print("SVM Nested Paging not supported\n");
900 V3_Print("SVM Nested Paging supported\n");
907 void v3_init_svm_cpu(int cpu_id) {
909 extern v3_cpu_arch_t v3_cpu_types[];
911 // Enable SVM on the CPU
912 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
913 msr.e_reg.low |= EFER_MSR_svm_enable;
914 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
916 V3_Print("SVM Enabled\n");
918 // Setup the host state save area
919 host_vmcbs[cpu_id] = (addr_t)V3_AllocPages(4);
922 // msr.e_reg.high = 0;
923 //msr.e_reg.low = (uint_t)host_vmcb;
924 msr.r_reg = host_vmcbs[cpu_id];
926 PrintDebug("Host State being saved at %p\n", (void *)host_vmcbs[cpu_id]);
927 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
930 if (has_svm_nested_paging() == 1) {
931 v3_cpu_types[cpu_id] = V3_SVM_REV3_CPU;
933 v3_cpu_types[cpu_id] = V3_SVM_CPU;
939 void v3_deinit_svm_cpu(int cpu_id) {
941 extern v3_cpu_arch_t v3_cpu_types[];
943 // reset SVM_VM_HSAVE_PA_MSR
944 // Does setting it to NULL disable??
946 v3_set_msr(SVM_VM_HSAVE_PA_MSR, msr.e_reg.high, msr.e_reg.low);
949 v3_get_msr(EFER_MSR, &(msr.e_reg.high), &(msr.e_reg.low));
950 msr.e_reg.low &= ~EFER_MSR_svm_enable;
951 v3_set_msr(EFER_MSR, 0, msr.e_reg.low);
953 v3_cpu_types[cpu_id] = V3_INVALID_CPU;
955 V3_FreePages((void *)host_vmcbs[cpu_id], 4);
957 V3_Print("Host CPU %d host area freed, and SVM disabled\n", cpu_id);
1012 * Test VMSAVE/VMLOAD Latency
1014 #define vmsave ".byte 0x0F,0x01,0xDB ; "
1015 #define vmload ".byte 0x0F,0x01,0xDA ; "
1017 uint32_t start_lo, start_hi;
1018 uint32_t end_lo, end_hi;
1019 uint64_t start, end;
1021 __asm__ __volatile__ (
1023 "movl %%eax, %%esi ; "
1024 "movl %%edx, %%edi ; "
1025 "movq %%rcx, %%rax ; "
1028 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
1029 : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
1040 PrintDebug("VMSave Cycle Latency: %d\n", (uint32_t)(end - start));
1042 __asm__ __volatile__ (
1044 "movl %%eax, %%esi ; "
1045 "movl %%edx, %%edi ; "
1046 "movq %%rcx, %%rax ; "
1049 : "=D"(start_hi), "=S"(start_lo), "=a"(end_lo),"=d"(end_hi)
1050 : "c"(host_vmcb[cpu_id]), "0"(0), "1"(0), "2"(0), "3"(0)
1062 PrintDebug("VMLoad Cycle Latency: %d\n", (uint32_t)(end - start));
1064 /* End Latency Test */
1075 void Init_VMCB_pe(vmcb_t *vmcb, struct guest_info vm_info) {
1076 vmcb_ctrl_t * ctrl_area = GET_VMCB_CTRL_AREA(vmcb);
1077 vmcb_saved_state_t * guest_state = GET_VMCB_SAVE_STATE_AREA(vmcb);
1081 guest_state->rsp = vm_info.vm_regs.rsp;
1082 guest_state->rip = vm_info.rip;
1085 /* I pretty much just gutted this from TVMM */
1086 /* Note: That means its probably wrong */
1088 // set the segment registers to mirror ours
1089 guest_state->cs.selector = 1<<3;
1090 guest_state->cs.attrib.fields.type = 0xa; // Code segment+read
1091 guest_state->cs.attrib.fields.S = 1;
1092 guest_state->cs.attrib.fields.P = 1;
1093 guest_state->cs.attrib.fields.db = 1;
1094 guest_state->cs.attrib.fields.G = 1;
1095 guest_state->cs.limit = 0xfffff;
1096 guest_state->cs.base = 0;
1098 struct vmcb_selector *segregs [] = {&(guest_state->ss), &(guest_state->ds), &(guest_state->es), &(guest_state->fs), &(guest_state->gs), NULL};
1099 for ( i = 0; segregs[i] != NULL; i++) {
1100 struct vmcb_selector * seg = segregs[i];
1102 seg->selector = 2<<3;
1103 seg->attrib.fields.type = 0x2; // Data Segment+read/write
1104 seg->attrib.fields.S = 1;
1105 seg->attrib.fields.P = 1;
1106 seg->attrib.fields.db = 1;
1107 seg->attrib.fields.G = 1;
1108 seg->limit = 0xfffff;
1114 /* JRL THIS HAS TO GO */
1116 // guest_state->tr.selector = GetTR_Selector();
1117 guest_state->tr.attrib.fields.type = 0x9;
1118 guest_state->tr.attrib.fields.P = 1;
1119 // guest_state->tr.limit = GetTR_Limit();
1120 //guest_state->tr.base = GetTR_Base();// - 0x2000;
1128 guest_state->efer |= EFER_MSR_svm_enable;
1129 guest_state->rflags = 0x00000002; // The reserved bit is always 1
1130 ctrl_area->svm_instrs.VMRUN = 1;
1131 guest_state->cr0 = 0x00000001; // PE
1132 ctrl_area->guest_ASID = 1;
1135 // guest_state->cpl = 0;
1141 ctrl_area->cr_writes.cr4 = 1;
1143 ctrl_area->exceptions.de = 1;
1144 ctrl_area->exceptions.df = 1;
1145 ctrl_area->exceptions.pf = 1;
1146 ctrl_area->exceptions.ts = 1;
1147 ctrl_area->exceptions.ss = 1;
1148 ctrl_area->exceptions.ac = 1;
1149 ctrl_area->exceptions.mc = 1;
1150 ctrl_area->exceptions.gp = 1;
1151 ctrl_area->exceptions.ud = 1;
1152 ctrl_area->exceptions.np = 1;
1153 ctrl_area->exceptions.of = 1;
1154 ctrl_area->exceptions.nmi = 1;
1158 ctrl_area->instrs.IOIO_PROT = 1;
1159 ctrl_area->IOPM_BASE_PA = (uint_t)V3_AllocPages(3);
1163 tmp_reg.r_reg = ctrl_area->IOPM_BASE_PA;
1164 memset((void*)(tmp_reg.e_reg.low), 0xffffffff, PAGE_SIZE * 2);
1167 ctrl_area->instrs.INTR = 1;
1174 memset(gdt_buf, 0, 6);
1175 memset(idt_buf, 0, 6);
1178 uint_t gdt_base, idt_base;
1179 ushort_t gdt_limit, idt_limit;
1182 gdt_base = *(ulong_t*)((uchar_t*)gdt_buf + 2) & 0xffffffff;
1183 gdt_limit = *(ushort_t*)(gdt_buf) & 0xffff;
1184 PrintDebug("GDT: base: %x, limit: %x\n", gdt_base, gdt_limit);
1187 idt_base = *(ulong_t*)(idt_buf + 2) & 0xffffffff;
1188 idt_limit = *(ushort_t*)(idt_buf) & 0xffff;
1189 PrintDebug("IDT: base: %x, limit: %x\n",idt_base, idt_limit);
1192 // gdt_base -= 0x2000;
1193 //idt_base -= 0x2000;
1195 guest_state->gdtr.base = gdt_base;
1196 guest_state->gdtr.limit = gdt_limit;
1197 guest_state->idtr.base = idt_base;
1198 guest_state->idtr.limit = idt_limit;
1204 // also determine if CPU supports nested paging
1206 if (vm_info.page_tables) {
1208 // Flush the TLB on entries/exits
1209 ctrl_area->TLB_CONTROL = 1;
1211 // Enable Nested Paging
1212 ctrl_area->NP_ENABLE = 1;
1214 PrintDebug("NP_Enable at 0x%x\n", &(ctrl_area->NP_ENABLE));
1216 // Set the Nested Page Table pointer
1217 ctrl_area->N_CR3 |= ((addr_t)vm_info.page_tables & 0xfffff000);
1220 // ctrl_area->N_CR3 = Get_CR3();
1221 // guest_state->cr3 |= (Get_CR3() & 0xfffff000);
1223 guest_state->g_pat = 0x7040600070406ULL;
1225 PrintDebug("Set Nested CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(ctrl_area->N_CR3)), (uint_t)*((unsigned char *)&(ctrl_area->N_CR3) + 4));
1226 PrintDebug("Set Guest CR3: lo: 0x%x hi: 0x%x\n", (uint_t)*(&(guest_state->cr3)), (uint_t)*((unsigned char *)&(guest_state->cr3) + 4));
1228 // guest_state->cr0 |= 0x80000000;