2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2009, Lei Xia <lxia@northwestern.edu>
11 * Copyright (c) 2009, Chang Seok Bae <jhuell@gmail.com>
12 * Copyright (c) 2009, Jack Lange <jarusl@cs.northwestern.edu>
13 * Copyright (c) 2009, The V3VEE Project <http://www.v3vee.org>
14 * All rights reserved.
16 * Author: Lei Xia <lxia@northwestern.edu>
17 * Chang Seok Bae <jhuell@gmail.com>
18 * Jack Lange <jarusl@cs.northwestern.edu>
20 * This is free software. You are permitted to use,
21 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
26 #include <palacios/vmm.h>
27 #include <palacios/vmm_types.h>
28 #include <palacios/vmm_io.h>
29 #include <palacios/vmm_intr.h>
30 #include <palacios/vmm_rbtree.h>
32 #include <devices/pci.h>
33 #include <devices/pci_types.h>
37 #define PrintDebug(fmt, args...)
41 #define CONFIG_ADDR_PORT 0x0cf8
42 #define CONFIG_DATA_PORT 0x0cfc
45 #define PCI_BUS_COUNT 1
47 // This must always be a multiple of 8
48 #define MAX_BUS_DEVICES 32
61 } __attribute__((packed));
62 } __attribute__((packed));
63 } __attribute__((packed));
72 // Red Black tree containing all attached devices
73 struct rb_root devices;
75 // Bitmap of the allocated device numbers
76 uint8_t dev_map[MAX_BUS_DEVICES / 8];
82 // Configuration address register
83 struct pci_addr_reg addr_reg;
86 struct pci_bus bus_list[PCI_BUS_COUNT];
95 static void pci_dump_state(struct pci_internal * pci_state) {
96 struct rb_node * node = v3_rb_first(&(pci_state->bus_list[0].devices));
97 struct pci_device * tmp_dev = NULL;
99 PrintDebug("===PCI: Dumping state Begin ==========\n");
102 tmp_dev = rb_entry(node, struct pci_device, dev_tree_node);
104 PrintDebug("PCI Device Number: %d (%s):\n", tmp_dev->dev_num, tmp_dev->name);
105 PrintDebug("irq = %d\n", tmp_dev->config_header.intr_line);
106 PrintDebug("Vend ID: 0x%x\n", tmp_dev->config_header.vendor_id);
107 PrintDebug("Device ID: 0x%x\n", tmp_dev->config_header.device_id);
109 } while ((node = v3_rb_next(node)));
111 PrintDebug("====PCI: Dumping state End==========\n");
119 // Scan the dev_map bitmap for the first '0' bit
120 static int get_free_dev_num(struct pci_bus * bus) {
123 for (i = 0; i < sizeof(bus->dev_map); i++) {
124 if (bus->dev_map[i] != 0xff) {
126 for (j = 0; j < 8; j++) {
127 if (!(bus->dev_map[i] & (0x1 << j))) {
128 return ((i * 8) + j);
137 static void allocate_dev_num(struct pci_bus * bus, int dev_num) {
138 int major = (dev_num / 8);
139 int minor = dev_num % 8;
141 bus->dev_map[major] |= (0x1 << minor);
147 struct pci_device * __add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
149 struct rb_node ** p = &(bus->devices.rb_node);
150 struct rb_node * parent = NULL;
151 struct pci_device * tmp_dev = NULL;
155 tmp_dev = rb_entry(parent, struct pci_device, dev_tree_node);
157 if (dev->dev_num < tmp_dev->dev_num) {
159 } else if (dev->dev_num > tmp_dev->dev_num) {
166 rb_link_node(&(dev->dev_tree_node), parent, p);
173 struct pci_device * add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
175 struct pci_device * ret = NULL;
177 if ((ret = __add_device_to_bus(bus, dev))) {
181 v3_rb_insert_color(&(dev->dev_tree_node), &(bus->devices));
183 allocate_dev_num(bus, dev->dev_num);
189 static struct pci_device * get_device(struct pci_bus * bus, int dev_num) {
190 struct rb_node * n = bus->devices.rb_node;
191 struct pci_device * dev = NULL;
194 dev = rb_entry(n, struct pci_device, dev_tree_node);
196 if (dev_num < dev->dev_num) {
198 } else if (dev_num > dev->dev_num) {
214 static int addr_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
215 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
216 int reg_offset = port & 0x3;
217 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
219 PrintDebug("Reading PCI Address Port (%x): %x len=%d\n", port, pci_state->addr_reg.val, length);
222 if (reg_offset != 0) {
223 PrintError("Invalid Address Port Read\n");
226 *(uint32_t *)dst = *(uint32_t *)reg_addr;
227 } else if (length == 2) {
228 if (reg_offset > 2) {
229 PrintError("Invalid Address Port Read\n");
232 *(uint16_t *)dst = *(uint16_t *)reg_addr;
233 } else if (length == 1) {
234 *(uint8_t *)dst = *(uint8_t *)reg_addr;
236 PrintError("Invalid read length (%d) for PCI address register\n", length);
245 static int addr_port_write(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
246 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
247 int reg_offset = port & 0x3;
248 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
252 if (reg_offset != 0) {
253 PrintError("Invalid Address Port Write\n");
257 PrintDebug("Writing PCI 4 bytes Val=%x\n", *(uint32_t *)src);
259 *(uint32_t *)reg_addr = *(uint32_t *)src;
260 } else if (length == 2) {
261 if (reg_offset > 2) {
262 PrintError("Invalid Address Port Write\n");
266 PrintDebug("Writing PCI 2 byte Val=%x\n", *(uint16_t *)src);
268 *(uint16_t *)reg_addr = *(uint16_t *)src;
269 } else if (length == 1) {
270 PrintDebug("Writing PCI 1 byte Val=%x\n", *(uint8_t *)src);
271 *(uint8_t *)reg_addr = *(uint8_t *)src;
273 PrintError("Invalid write length (%d) for PCI address register\n", length);
277 PrintDebug("Writing PCI Address Port(%x): %x\n", port, pci_state->addr_reg.val);
283 static int data_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * vmdev) {
284 struct pci_internal * pci_state = (struct pci_internal *)(vmdev->private_data);
285 struct pci_device * pci_dev = NULL;
286 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
289 if (pci_state->addr_reg.bus_num != 0) {
291 for (i = 0; i < length; i++) {
292 *((uint8_t *)dst + i) = 0xff;
298 PrintDebug("Reading PCI Data register. bus = %d, dev = %d, reg = %d (%x), cfg_reg = %x\n",
299 pci_state->addr_reg.bus_num,
300 pci_state->addr_reg.dev_num,
302 pci_state->addr_reg.val);
304 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num);
306 if (pci_dev == NULL) {
307 for (i = 0; i < length; i++) {
308 *(uint8_t *)((uint8_t *)dst + i) = 0xff;
314 for (i = 0; i < length; i++) {
315 *(uint8_t *)((uint8_t *)dst + i) = pci_dev->config_space[reg_num + i];
318 PrintDebug("\tVal=%x, len=%d\n", *(uint32_t *)dst, length);
324 static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
325 if (header_type == 0x00) {
344 // PCI to PCI Bridge = 0x01
345 // CardBus Bridge = 0x02
348 PrintError("Invalid PCI Header type (0x%.2x)\n", header_type);
355 static int bar_update(struct pci_device * pci, int bar_num) {
356 PrintError("Bar Updates not handled (bar=%d)\n", bar_num);
361 static int data_port_write(ushort_t port, void * src, uint_t length, struct vm_device * vmdev) {
362 struct pci_internal * pci_state = (struct pci_internal *)vmdev->private_data;
363 struct pci_device * pci_dev = NULL;
364 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
368 if (pci_state->addr_reg.bus_num != 0) {
372 PrintDebug("Writing PCI Data register. bus = %d, dev = %d, reg = %d (%x) addr_reg = %x (val=%x, len=%d)\n",
373 pci_state->addr_reg.bus_num,
374 pci_state->addr_reg.dev_num,
376 pci_state->addr_reg.val,
377 *(uint32_t *)src, length);
380 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num);
382 if (pci_dev == NULL) {
383 PrintError("Writing configuration space for non-present device (dev_num=%d)\n",
384 pci_state->addr_reg.dev_num);
389 for (i = 0; i < length; i++) {
390 uint_t cur_reg = reg_num + i;
392 if (is_cfg_reg_writable(pci_dev->config_header.header_type, cur_reg)) {
393 pci_dev->config_space[cur_reg] = *(uint8_t *)((uint8_t *)src + i);
395 if ((cur_reg >= 0x10) && (cur_reg < 0x28)) {
397 int bar_reg = (cur_reg & ~0x3) - 0x10;
399 pci_dev->bar_update_flag = 1;
400 pci_dev->bar[bar_reg].updated = 1;
402 PrintDebug("Updating BAR register\n");
404 } else if ((cur_reg >= 0x30) && (cur_reg < 0x34)) {
405 pci_dev->ext_rom_update_flag = 1;
406 } else if (cur_reg == 0x04) {
408 uint8_t command = *((uint8_t *)src + i);
410 pci_dev->config_space[cur_reg] = command;
412 if (pci_dev->cmd_update) {
413 pci_dev->cmd_update(pci_dev, (command & 0x01), (command & 0x02));
416 } else if (cur_reg == 0x0f) {
418 pci_dev->config_header.BIST = 0x00;
423 if (pci_dev->config_update) {
424 pci_dev->config_update(pci_dev, reg_num, length);
427 // Scan for BAR updated
428 if (pci_dev->bar_update_flag) {
429 for (i = 0; i < 6; i++) {
430 if (pci_dev->bar[i].updated) {
431 int bar_offset = 0x10 + 4 * i;
433 *(uint32_t *)(pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
436 if (bar_update(pci_dev, i) == -1) {
437 PrintError("PCI Device %s: Bar update Error Bar=%d\n", pci_dev->name, i);
441 pci_dev->bar[i].updated = 0;
444 pci_dev->bar_update_flag = 0;
447 if ((pci_dev->ext_rom_update_flag) && (pci_dev->ext_rom_update)) {
448 pci_dev->ext_rom_update(pci_dev);
449 pci_dev->ext_rom_update_flag = 0;
458 static int pci_reset_device(struct vm_device * dev) {
459 PrintDebug("pci: reset device\n");
464 static int pci_start_device(struct vm_device * dev) {
465 PrintDebug("pci: start device\n");
470 static int pci_stop_device(struct vm_device * dev) {
471 PrintDebug("pci: stop device\n");
477 static int pci_deinit_device(struct vm_device * dev) {
480 for (i = 0; i < 4; i++){
481 v3_dev_unhook_io(dev, CONFIG_ADDR_PORT + i);
482 v3_dev_unhook_io(dev, CONFIG_DATA_PORT + i);
491 static int init_i440fx(struct vm_device * dev) {
492 struct pci_device * pci_dev = NULL;
493 struct v3_pci_bar bars[6];
496 for (i = 0; i < 6; i++) {
497 bars[i].type = PCI_BAR_NONE;
500 pci_dev = v3_pci_register_device(dev, PCI_STD_DEVICE, 0, "i440FX", 0, bars,
501 NULL, NULL, NULL, NULL);
507 pci_dev->config_header.vendor_id = 0x8086;
508 pci_dev->config_header.device_id = 0x1237;
509 pci_dev->config_header.revision = 0x0002;
510 pci_dev->config_header.subclass = 0x00; // SubClass: host2pci
511 pci_dev->config_header.class = 0x06; // Class: PCI bridge
513 pci_dev->bus_num = 0;
520 static void init_pci_busses(struct pci_internal * pci_state) {
523 for (i = 0; i < PCI_BUS_COUNT; i++) {
524 pci_state->bus_list[i].bus_num = i;
525 pci_state->bus_list[i].devices.rb_node = NULL;
526 memset(pci_state->bus_list[i].dev_map, 0, sizeof(pci_state->bus_list[i].dev_map));
532 static int pci_init_device(struct vm_device * dev) {
533 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;;
536 PrintDebug("pci: init_device\n");
539 // dev->vm->pci = dev; //should be in vmm_config.c
541 pci_state->addr_reg.val = 0;
543 init_pci_busses(pci_state);
545 if (init_i440fx(dev) == -1) {
546 PrintError("Could not intialize i440fx\n");
550 PrintDebug("Sizeof config header=%d\n", (int)sizeof(struct pci_config_header));
552 for (i = 0; i < 4; i++) {
553 v3_dev_hook_io(dev, CONFIG_ADDR_PORT + i, &addr_port_read, &addr_port_write);
554 v3_dev_hook_io(dev, CONFIG_DATA_PORT + i, &data_port_read, &data_port_write);
561 static struct vm_device_ops dev_ops = {
562 .init = pci_init_device,
563 .deinit = pci_deinit_device,
564 .reset = pci_reset_device,
565 .start = pci_start_device,
566 .stop = pci_stop_device,
570 struct vm_device * v3_create_pci() {
571 struct pci_internal * pci_state = V3_Malloc(sizeof(struct pci_internal));
573 PrintDebug("PCI internal at %p\n",(void *)pci_state);
575 struct vm_device * device = v3_create_device("PCI", &dev_ops, pci_state);
582 static inline int init_bars(struct pci_device * pci_dev) {
585 for (i = 0; i < 6; i++) {
586 int bar_offset = 0x10 + (4 * i);
588 if (pci_dev->bar[i].type == PCI_BAR_IO) {
590 pci_dev->bar[i].mask = (~((pci_dev->bar[i].num_ports) - 1)) | 0x01;
592 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].default_base_port & pci_dev->bar[i].mask;
593 *(uint32_t *)(pci_dev->config_space + bar_offset) |= 0x00000001;
595 for (j = 0; j < pci_dev->bar[i].num_ports; j++) {
597 if (v3_dev_hook_io(pci_dev->vm_dev, pci_dev->bar[i].default_base_port + j,
598 pci_dev->bar[i].io_read, pci_dev->bar[i].io_write) == -1) {
599 PrintError("Could not hook default io port %x\n", pci_dev->bar[i].default_base_port + j);
604 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
605 pci_dev->bar[i].mask = ~((pci_dev->bar[i].num_pages << 12) - 1);
606 pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
608 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].default_base_addr & pci_dev->bar[i].mask;
611 if (pci_dev->bar[i].mem_read) {
613 v3_hook_full_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
614 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
615 pci_dev->bar[i].mem_read, pci_dev->bar[i].mem_write, pci_dev->vm_dev);
616 } else if (pci_dev->bar[i].mem_write) {
618 PrintError("Write hooks not supported for PCI devices\n");
621 v3_hook_write_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
622 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
623 pci_dev->bar[i].mem_write, pci_dev->vm_dev);
626 // set the prefetchable flag...
627 *(uint8_t *)(pci_dev->config_space + bar_offset) |= 0x00000008;
630 } else if (pci_dev->bar[i].type == PCI_BAR_MEM16) {
631 PrintError("16 Bit memory ranges not supported (reg: %d)\n", i);
633 } else if (pci_dev->bar[i].type == PCI_BAR_NONE) {
634 *(uint32_t *)(pci_dev->config_space + bar_offset) = 0x00000000;
636 PrintError("Invalid BAR type for bar #%d\n", i);
645 // if dev_num == -1, auto assign
646 struct pci_device * v3_pci_register_device(struct vm_device * pci,
647 pci_device_type_t dev_type,
651 struct v3_pci_bar * bars,
652 int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length),
653 int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
654 int (*ext_rom_update)(struct pci_device * pci_dev),
655 void * private_data) {
657 struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
658 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
659 struct pci_device * pci_dev = NULL;
662 if (dev_num > MAX_BUS_DEVICES) {
663 PrintError("Requested Invalid device number (%d)\n", dev_num);
668 if ((dev_num = get_free_dev_num(bus)) == -1) {
669 PrintError("No more available PCI slots on bus %d\n", bus->bus_num);
674 if (get_device(bus, dev_num) != NULL) {
675 PrintError("PCI Device already registered at slot %d on bus %d\n",
676 dev_num, bus->bus_num);
681 pci_dev = (struct pci_device *)V3_Malloc(sizeof(struct pci_device));
683 if (pci_dev == NULL) {
687 memset(pci_dev, 0, sizeof(struct pci_device));
692 pci_dev->config_header.header_type = 0x00;
695 PrintError("Unhandled PCI Device Type: %d\n", dev_type);
699 pci_dev->bus_num = bus_num;
700 pci_dev->dev_num = dev_num;
702 strncpy(pci_dev->name, name, sizeof(pci_dev->name));
703 pci_dev->vm_dev = pci;
705 // register update callbacks
706 pci_dev->config_update = config_update;
707 pci_dev->cmd_update = cmd_update;
708 pci_dev->ext_rom_update = ext_rom_update;
710 pci_dev->priv_data = private_data;
714 for (i = 0; i < 6; i ++){
715 pci_dev->bar[i].type = bars[i].type;
717 if (pci_dev->bar[i].type == PCI_BAR_IO) {
718 pci_dev->bar[i].num_ports = bars[i].num_ports;
719 pci_dev->bar[i].default_base_port = bars[i].default_base_port;
720 pci_dev->bar[i].io_read = bars[i].io_read;
721 pci_dev->bar[i].io_write = bars[i].io_write;
723 pci_dev->bar[i].num_pages = bars[i].num_pages;
724 pci_dev->bar[i].default_base_addr = bars[i].default_base_addr;
725 pci_dev->bar[i].mem_read = bars[i].mem_read;
726 pci_dev->bar[i].mem_write = bars[i].mem_write;
730 if (init_bars(pci_dev) == -1) {
731 PrintError("could not initialize bar registers\n");
736 add_device_to_bus(bus, pci_dev);
739 pci_dump_state(pci_state);