2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2009, Lei Xia <lxia@northwestern.edu>
11 * Copyright (c) 2009, Chang Seok Bae <jhuell@gmail.com>
12 * Copyright (c) 2009, Jack Lange <jarusl@cs.northwestern.edu>
13 * Copyright (c) 2009, The V3VEE Project <http://www.v3vee.org>
14 * All rights reserved.
16 * Author: Lei Xia <lxia@northwestern.edu>
17 * Chang Seok Bae <jhuell@gmail.com>
18 * Jack Lange <jarusl@cs.northwestern.edu>
20 * This is free software. You are permitted to use,
21 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
26 #include <palacios/vmm.h>
27 #include <palacios/vmm_types.h>
28 #include <palacios/vmm_io.h>
29 #include <palacios/vmm_intr.h>
30 #include <palacios/vmm_rbtree.h>
32 #include <devices/pci.h>
33 #include <devices/pci_types.h>
35 #ifndef CONFIG_DEBUG_PCI
37 #define PrintDebug(fmt, args...)
41 #define CONFIG_ADDR_PORT 0x0cf8
42 #define CONFIG_DATA_PORT 0x0cfc
44 #define PCI_DEV_IO_PORT_BASE 0xc000
46 #define PCI_BUS_COUNT 1
48 // This must always be a multiple of 8
49 #define MAX_BUS_DEVICES 32
62 } __attribute__((packed));
63 } __attribute__((packed));
64 } __attribute__((packed));
73 // Red Black tree containing all attached devices
74 struct rb_root devices;
76 // Bitmap of the allocated device numbers
77 uint8_t dev_map[MAX_BUS_DEVICES / 8];
80 int (*raise_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev);
81 int (*lower_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev);
82 struct vm_device * irq_bridge_dev;
88 // Configuration address register
89 struct pci_addr_reg addr_reg;
91 // Base IO Port which PCI devices will register with...
95 struct pci_bus bus_list[PCI_BUS_COUNT];
102 #ifdef CONFIG_DEBUG_PCI
104 static void pci_dump_state(struct pci_internal * pci_state) {
105 struct rb_node * node = v3_rb_first(&(pci_state->bus_list[0].devices));
106 struct pci_device * tmp_dev = NULL;
108 PrintDebug("===PCI: Dumping state Begin ==========\n");
111 tmp_dev = rb_entry(node, struct pci_device, dev_tree_node);
113 PrintDebug("PCI Device Number: %d (%s):\n", tmp_dev->dev_num, tmp_dev->name);
114 PrintDebug("irq = %d\n", tmp_dev->config_header.intr_line);
115 PrintDebug("Vend ID: 0x%x\n", tmp_dev->config_header.vendor_id);
116 PrintDebug("Device ID: 0x%x\n", tmp_dev->config_header.device_id);
118 } while ((node = v3_rb_next(node)));
120 PrintDebug("====PCI: Dumping state End==========\n");
128 // Scan the dev_map bitmap for the first '0' bit
129 static int get_free_dev_num(struct pci_bus * bus) {
132 for (i = 0; i < sizeof(bus->dev_map); i++) {
133 PrintDebug("i=%d\n", i);
134 if (bus->dev_map[i] != 0xff) {
136 for (j = 0; j < 8; j++) {
137 PrintDebug("\tj=%d\n", j);
138 if (!(bus->dev_map[i] & (0x1 << j))) {
139 return ((i * 8) + j);
148 static void allocate_dev_num(struct pci_bus * bus, int dev_num) {
149 int major = (dev_num / 8);
150 int minor = dev_num % 8;
152 bus->dev_map[major] |= (0x1 << minor);
158 struct pci_device * __add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
160 struct rb_node ** p = &(bus->devices.rb_node);
161 struct rb_node * parent = NULL;
162 struct pci_device * tmp_dev = NULL;
166 tmp_dev = rb_entry(parent, struct pci_device, dev_tree_node);
168 if (dev->devfn < tmp_dev->devfn) {
170 } else if (dev->devfn > tmp_dev->devfn) {
177 rb_link_node(&(dev->dev_tree_node), parent, p);
184 struct pci_device * add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
186 struct pci_device * ret = NULL;
188 if ((ret = __add_device_to_bus(bus, dev))) {
192 v3_rb_insert_color(&(dev->dev_tree_node), &(bus->devices));
194 allocate_dev_num(bus, dev->dev_num);
200 static struct pci_device * get_device(struct pci_bus * bus, uint8_t dev_num, uint8_t fn_num) {
201 struct rb_node * n = bus->devices.rb_node;
202 struct pci_device * dev = NULL;
203 uint8_t devfn = ((dev_num & 0x1f) << 3) | (fn_num & 0x7);
206 dev = rb_entry(n, struct pci_device, dev_tree_node);
208 if (devfn < dev->devfn) {
210 } else if (devfn > dev->devfn) {
226 static int addr_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
227 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
228 int reg_offset = port & 0x3;
229 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
231 PrintDebug("Reading PCI Address Port (%x): %x len=%d\n", port, pci_state->addr_reg.val, length);
234 if (reg_offset != 0) {
235 PrintError("Invalid Address Port Read\n");
238 *(uint32_t *)dst = *(uint32_t *)reg_addr;
239 } else if (length == 2) {
240 if (reg_offset > 2) {
241 PrintError("Invalid Address Port Read\n");
244 *(uint16_t *)dst = *(uint16_t *)reg_addr;
245 } else if (length == 1) {
246 *(uint8_t *)dst = *(uint8_t *)reg_addr;
248 PrintError("Invalid read length (%d) for PCI address register\n", length);
257 static int addr_port_write(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
258 struct pci_internal * pci_state = (struct pci_internal *)dev->private_data;
259 int reg_offset = port & 0x3;
260 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
264 if (reg_offset != 0) {
265 PrintError("Invalid Address Port Write\n");
269 PrintDebug("Writing PCI 4 bytes Val=%x\n", *(uint32_t *)src);
271 *(uint32_t *)reg_addr = *(uint32_t *)src;
272 } else if (length == 2) {
273 if (reg_offset > 2) {
274 PrintError("Invalid Address Port Write\n");
278 PrintDebug("Writing PCI 2 byte Val=%x\n", *(uint16_t *)src);
280 *(uint16_t *)reg_addr = *(uint16_t *)src;
281 } else if (length == 1) {
282 PrintDebug("Writing PCI 1 byte Val=%x\n", *(uint8_t *)src);
283 *(uint8_t *)reg_addr = *(uint8_t *)src;
285 PrintError("Invalid write length (%d) for PCI address register\n", length);
289 PrintDebug("Writing PCI Address Port(%x): %x\n", port, pci_state->addr_reg.val);
295 static int data_port_read(ushort_t port, void * dst, uint_t length, struct vm_device * vmdev) {
296 struct pci_internal * pci_state = (struct pci_internal *)(vmdev->private_data);
297 struct pci_device * pci_dev = NULL;
298 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
301 if (pci_state->addr_reg.bus_num != 0) {
303 for (i = 0; i < length; i++) {
304 *((uint8_t *)dst + i) = 0xff;
310 PrintDebug("Reading PCI Data register. bus = %d, dev = %d, reg = %d (%x), cfg_reg = %x\n",
311 pci_state->addr_reg.bus_num,
312 pci_state->addr_reg.dev_num,
314 pci_state->addr_reg.val);
316 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
318 if (pci_dev == NULL) {
319 for (i = 0; i < length; i++) {
320 *(uint8_t *)((uint8_t *)dst + i) = 0xff;
326 for (i = 0; i < length; i++) {
327 *(uint8_t *)((uint8_t *)dst + i) = pci_dev->config_space[reg_num + i];
330 PrintDebug("\tVal=%x, len=%d\n", *(uint32_t *)dst, length);
336 static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
337 if (header_type == 0x00) {
355 } else if (header_type == 0x80) {
374 // PCI to PCI Bridge = 0x01
375 // CardBus Bridge = 0x02
378 PrintError("Invalid PCI Header type (0x%.2x)\n", header_type);
385 static int bar_update(struct pci_device * pci, int bar_num, uint32_t new_val) {
386 struct v3_pci_bar * bar = &(pci->bar[bar_num]);
388 PrintDebug("Updating BAR Register (Dev=%s) (bar=%d) (old_val=0x%x) (new_val=0x%x)\n",
389 pci->name, bar_num, bar->val, new_val);
395 PrintDebug("\tRehooking %d IO ports from base 0x%x to 0x%x for %d ports\n",
396 bar->num_ports, PCI_IO_BASE(bar->val), PCI_IO_BASE(new_val),
399 // only do this if pci device is enabled....
400 if (!(pci->config_header.status & 0x1)) {
401 PrintError("PCI Device IO space not enabled\n");
404 for (i = 0; i < bar->num_ports; i++) {
406 PrintDebug("Rehooking PCI IO port (old port=%u) (new port=%u)\n",
407 PCI_IO_BASE(bar->val) + i, PCI_IO_BASE(new_val) + i);
409 v3_dev_unhook_io(pci->vm_dev, PCI_IO_BASE(bar->val) + i);
411 if (v3_dev_hook_io(pci->vm_dev, PCI_IO_BASE(new_val) + i,
412 bar->io_read, bar->io_write) == -1) {
414 PrintError("Could not hook PCI IO port (old port=%u) (new port=%u)\n",
415 PCI_IO_BASE(bar->val) + i, PCI_IO_BASE(new_val) + i);
424 case PCI_BAR_MEM32: {
425 v3_unhook_mem(pci->vm_dev->vm, (addr_t)(bar->val));
428 v3_hook_full_mem(pci->vm_dev->vm, PCI_MEM32_BASE(new_val),
429 PCI_MEM32_BASE(new_val) + (bar->num_pages * PAGE_SIZE_4KB),
430 bar->mem_read, bar->mem_write, pci->vm_dev);
432 PrintError("Write hooks not supported for PCI\n");
441 PrintDebug("Reprogramming an unsupported BAR register (Dev=%s) (bar=%d) (val=%x)\n",
442 pci->name, bar_num, new_val);
446 PrintError("Invalid Bar Reg updated (bar=%d)\n", bar_num);
454 static int data_port_write(ushort_t port, void * src, uint_t length, struct vm_device * vmdev) {
455 struct pci_internal * pci_state = (struct pci_internal *)vmdev->private_data;
456 struct pci_device * pci_dev = NULL;
457 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
461 if (pci_state->addr_reg.bus_num != 0) {
465 PrintDebug("Writing PCI Data register. bus = %d, dev = %d, fn = %d, reg = %d (%x) addr_reg = %x (val=%x, len=%d)\n",
466 pci_state->addr_reg.bus_num,
467 pci_state->addr_reg.dev_num,
468 pci_state->addr_reg.fn_num,
470 pci_state->addr_reg.val,
471 *(uint32_t *)src, length);
474 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
476 if (pci_dev == NULL) {
477 PrintError("Writing configuration space for non-present device (dev_num=%d)\n",
478 pci_state->addr_reg.dev_num);
483 for (i = 0; i < length; i++) {
484 uint_t cur_reg = reg_num + i;
485 int writable = is_cfg_reg_writable(pci_dev->config_header.header_type, cur_reg);
487 if (writable == -1) {
488 PrintError("Invalid PCI configuration space\n");
493 pci_dev->config_space[cur_reg] = *(uint8_t *)((uint8_t *)src + i);
495 if ((cur_reg >= 0x10) && (cur_reg < 0x28)) {
496 // BAR Register Update
497 int bar_reg = ((cur_reg & ~0x3) - 0x10) / 4;
499 pci_dev->bar_update_flag = 1;
500 pci_dev->bar[bar_reg].updated = 1;
502 // PrintDebug("Updating BAR register %d\n", bar_reg);
504 } else if ((cur_reg >= 0x30) && (cur_reg < 0x34)) {
505 // Extension ROM update
507 pci_dev->ext_rom_update_flag = 1;
508 } else if (cur_reg == 0x04) {
510 uint8_t command = *((uint8_t *)src + i);
512 PrintError("command update for %s old=%x new=%x\n",
514 pci_dev->config_space[cur_reg],command);
516 pci_dev->config_space[cur_reg] = command;
518 if (pci_dev->cmd_update) {
519 pci_dev->cmd_update(pci_dev, (command & 0x01), (command & 0x02));
522 } else if (cur_reg == 0x0f) {
524 pci_dev->config_header.BIST = 0x00;
527 PrintError("PCI Write to read only register %d\n", cur_reg);
531 if (pci_dev->config_update) {
532 pci_dev->config_update(pci_dev, reg_num, length);
535 // Scan for BAR updated
536 if (pci_dev->bar_update_flag) {
537 for (i = 0; i < 6; i++) {
538 if (pci_dev->bar[i].updated) {
539 int bar_offset = 0x10 + 4 * i;
541 *(uint32_t *)(pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
542 // check special flags....
545 if (bar_update(pci_dev, i, *(uint32_t *)(pci_dev->config_space + bar_offset)) == -1) {
546 PrintError("PCI Device %s: Bar update Error Bar=%d\n", pci_dev->name, i);
550 pci_dev->bar[i].updated = 0;
553 pci_dev->bar_update_flag = 0;
556 if ((pci_dev->ext_rom_update_flag) && (pci_dev->ext_rom_update)) {
557 pci_dev->ext_rom_update(pci_dev);
558 pci_dev->ext_rom_update_flag = 0;
567 static int pci_reset_device(struct vm_device * dev) {
568 PrintDebug("pci: reset device\n");
573 static int pci_start_device(struct vm_device * dev) {
574 PrintDebug("pci: start device\n");
579 static int pci_stop_device(struct vm_device * dev) {
580 PrintDebug("pci: stop device\n");
586 static int pci_free(struct vm_device * dev) {
589 for (i = 0; i < 4; i++){
590 v3_dev_unhook_io(dev, CONFIG_ADDR_PORT + i);
591 v3_dev_unhook_io(dev, CONFIG_DATA_PORT + i);
599 static void init_pci_busses(struct pci_internal * pci_state) {
602 for (i = 0; i < PCI_BUS_COUNT; i++) {
603 pci_state->bus_list[i].bus_num = i;
604 pci_state->bus_list[i].devices.rb_node = NULL;
605 memset(pci_state->bus_list[i].dev_map, 0, sizeof(pci_state->bus_list[i].dev_map));
612 static struct v3_device_ops dev_ops = {
614 .reset = pci_reset_device,
615 .start = pci_start_device,
616 .stop = pci_stop_device,
622 static int pci_init(struct guest_info * vm, void * cfg_data) {
623 struct pci_internal * pci_state = V3_Malloc(sizeof(struct pci_internal));
626 PrintDebug("PCI internal at %p\n",(void *)pci_state);
628 struct vm_device * dev = v3_allocate_device("PCI", &dev_ops, pci_state);
630 if (v3_attach_device(vm, dev) == -1) {
631 PrintError("Could not attach device %s\n", "PCI");
636 pci_state->addr_reg.val = 0;
637 pci_state->dev_io_base = PCI_DEV_IO_PORT_BASE;
639 init_pci_busses(pci_state);
641 PrintDebug("Sizeof config header=%d\n", (int)sizeof(struct pci_config_header));
643 for (i = 0; i < 4; i++) {
644 v3_dev_hook_io(dev, CONFIG_ADDR_PORT + i, &addr_port_read, &addr_port_write);
645 v3_dev_hook_io(dev, CONFIG_DATA_PORT + i, &data_port_read, &data_port_write);
652 device_register("PCI", pci_init)
655 static inline int init_bars(struct pci_device * pci_dev) {
658 for (i = 0; i < 6; i++) {
659 int bar_offset = 0x10 + (4 * i);
661 if (pci_dev->bar[i].type == PCI_BAR_IO) {
663 pci_dev->bar[i].mask = (~((pci_dev->bar[i].num_ports) - 1)) | 0x01;
665 if (pci_dev->bar[i].default_base_port != 0xffff) {
666 pci_dev->bar[i].val = pci_dev->bar[i].default_base_port & pci_dev->bar[i].mask;
668 pci_dev->bar[i].val = 0;
671 pci_dev->bar[i].val |= 0x00000001;
673 for (j = 0; j < pci_dev->bar[i].num_ports; j++) {
675 if (pci_dev->bar[i].default_base_port != 0xffff) {
676 if (v3_dev_hook_io(pci_dev->vm_dev, pci_dev->bar[i].default_base_port + j,
677 pci_dev->bar[i].io_read, pci_dev->bar[i].io_write) == -1) {
678 PrintError("Could not hook default io port %x\n", pci_dev->bar[i].default_base_port + j);
684 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
686 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
687 pci_dev->bar[i].mask = ~((pci_dev->bar[i].num_pages << 12) - 1);
688 pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
690 if (pci_dev->bar[i].default_base_addr != 0xffffffff) {
691 pci_dev->bar[i].val = pci_dev->bar[i].default_base_addr & pci_dev->bar[i].mask;
693 pci_dev->bar[i].val = 0;
697 if (pci_dev->bar[i].mem_read) {
699 v3_hook_full_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
700 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
701 pci_dev->bar[i].mem_read, pci_dev->bar[i].mem_write, pci_dev->vm_dev);
702 } else if (pci_dev->bar[i].mem_write) {
704 PrintError("Write hooks not supported for PCI devices\n");
707 v3_hook_write_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
708 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
709 pci_dev->bar[i].mem_write, pci_dev->vm_dev);
712 // set the prefetchable flag...
713 pci_dev->bar[i].val |= 0x00000008;
717 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
719 } else if (pci_dev->bar[i].type == PCI_BAR_MEM16) {
720 PrintError("16 Bit memory ranges not supported (reg: %d)\n", i);
722 } else if (pci_dev->bar[i].type == PCI_BAR_NONE) {
723 pci_dev->bar[i].val = 0x00000000;
724 pci_dev->bar[i].mask = 0x00000000; // This ensures that all updates will be dropped
725 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
727 PrintError("Invalid BAR type for bar #%d\n", i);
736 int v3_pci_set_irq_bridge(struct vm_device * pci_bus, int bus_num,
737 int (*raise_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev),
738 int (*lower_pci_irq)(struct vm_device * dev, struct pci_device * pci_dev),
739 struct vm_device * bridge_dev) {
740 struct pci_internal * pci_state = (struct pci_internal *)pci_bus->private_data;
743 pci_state->bus_list[bus_num].raise_pci_irq = raise_pci_irq;
744 pci_state->bus_list[bus_num].lower_pci_irq = lower_pci_irq;
745 pci_state->bus_list[bus_num].irq_bridge_dev = bridge_dev;
750 int v3_pci_raise_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev) {
751 struct pci_internal * pci_state = (struct pci_internal *)pci_bus->private_data;
752 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
754 return bus->raise_pci_irq(bus->irq_bridge_dev, dev);
757 int v3_pci_lower_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev) {
758 struct pci_internal * pci_state = (struct pci_internal *)pci_bus->private_data;
759 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
761 return bus->lower_pci_irq(bus->irq_bridge_dev, dev);
764 // if dev_num == -1, auto assign
765 struct pci_device * v3_pci_register_device(struct vm_device * pci,
766 pci_device_type_t dev_type,
771 struct v3_pci_bar * bars,
772 int (*config_update)(struct pci_device * pci_dev, uint_t reg_num, int length),
773 int (*cmd_update)(struct pci_device *pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
774 int (*ext_rom_update)(struct pci_device * pci_dev),
775 struct vm_device * dev) {
777 struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
778 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
779 struct pci_device * pci_dev = NULL;
782 if (dev_num > MAX_BUS_DEVICES) {
783 PrintError("Requested Invalid device number (%d)\n", dev_num);
787 if (dev_num == PCI_AUTO_DEV_NUM) {
788 PrintDebug("Searching for free device number\n");
789 if ((dev_num = get_free_dev_num(bus)) == -1) {
790 PrintError("No more available PCI slots on bus %d\n", bus->bus_num);
795 PrintDebug("Checking for PCI Device\n");
797 if (get_device(bus, dev_num, fn_num) != NULL) {
798 PrintError("PCI Device already registered at slot %d on bus %d\n",
799 dev_num, bus->bus_num);
804 pci_dev = (struct pci_device *)V3_Malloc(sizeof(struct pci_device));
806 if (pci_dev == NULL) {
807 PrintError("Could not allocate pci device\n");
811 memset(pci_dev, 0, sizeof(struct pci_device));
816 pci_dev->config_header.header_type = 0x00;
818 case PCI_MULTIFUNCTION:
819 pci_dev->config_header.header_type = 0x80;
822 PrintError("Unhandled PCI Device Type: %d\n", dev_type);
826 pci_dev->bus_num = bus_num;
827 pci_dev->dev_num = dev_num;
828 pci_dev->fn_num = fn_num;
830 strncpy(pci_dev->name, name, sizeof(pci_dev->name));
831 pci_dev->vm_dev = dev;
833 // register update callbacks
834 pci_dev->config_update = config_update;
835 pci_dev->cmd_update = cmd_update;
836 pci_dev->ext_rom_update = ext_rom_update;
840 for (i = 0; i < 6; i ++) {
841 pci_dev->bar[i].type = bars[i].type;
843 if (pci_dev->bar[i].type == PCI_BAR_IO) {
844 pci_dev->bar[i].num_ports = bars[i].num_ports;
846 // This is a horrible HACK becaues the BIOS is supposed to set the PCI base ports
847 // And if the BIOS doesn't, Linux just happily overlaps device port assignments
848 if (bars[i].default_base_port != (uint16_t)-1) {
849 pci_dev->bar[i].default_base_port = bars[i].default_base_port;
851 pci_dev->bar[i].default_base_port = pci_state->dev_io_base;
852 pci_state->dev_io_base += ( 0x100 * ((bars[i].num_ports / 0x100) + 1) );
855 pci_dev->bar[i].io_read = bars[i].io_read;
856 pci_dev->bar[i].io_write = bars[i].io_write;
857 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
858 pci_dev->bar[i].num_pages = bars[i].num_pages;
859 pci_dev->bar[i].default_base_addr = bars[i].default_base_addr;
860 pci_dev->bar[i].mem_read = bars[i].mem_read;
861 pci_dev->bar[i].mem_write = bars[i].mem_write;
863 pci_dev->bar[i].num_pages = 0;
864 pci_dev->bar[i].default_base_addr = 0;
865 pci_dev->bar[i].mem_read = NULL;
866 pci_dev->bar[i].mem_write = NULL;
870 if (init_bars(pci_dev) == -1) {
871 PrintError("could not initialize bar registers\n");
876 add_device_to_bus(bus, pci_dev);
878 #ifdef CONFIG_DEBUG_PCI
879 pci_dump_state(pci_state);