2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2009, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2009, Lei Xia <lxia@northwestern.edu>
12 * Copyright (c) 2009, Chang Seok Bae <jhuell@gmail.com>
13 * Copyright (c) 2009, The V3VEE Project <http://www.v3vee.org>
14 * All rights reserved.
16 * Author: Jack Lange <jarusl@cs.northwestern.edu>
17 * Lei Xia <lxia@northwestern.edu>
18 * Chang Seok Bae <jhuell@gmail.com>
20 * This is free software. You are permitted to use,
21 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
26 #include <palacios/vmm.h>
27 #include <palacios/vmm_types.h>
28 #include <palacios/vmm_io.h>
29 #include <palacios/vmm_intr.h>
30 #include <palacios/vmm_rbtree.h>
31 #include <palacios/vmm_dev_mgr.h>
33 #include <devices/pci.h>
34 #include <devices/pci_types.h>
36 #include <palacios/vm_guest.h>
40 #ifndef CONFIG_DEBUG_PCI
42 #define PrintDebug(fmt, args...)
46 #define CONFIG_ADDR_PORT 0x0cf8
47 #define CONFIG_DATA_PORT 0x0cfc
49 #define PCI_DEV_IO_PORT_BASE 0xc000
51 #define PCI_BUS_COUNT 1
53 // This must always be a multiple of 8
54 #define MAX_BUS_DEVICES 32
67 } __attribute__((packed));
68 } __attribute__((packed));
69 } __attribute__((packed));
78 // Red Black tree containing all attached devices
79 struct rb_root devices;
81 // Bitmap of the allocated device numbers
82 uint8_t dev_map[MAX_BUS_DEVICES / 8];
85 int (*raise_pci_irq)(struct pci_device * pci_dev, void * dev_data);
86 int (*lower_pci_irq)(struct pci_device * pci_dev, void * dev_data);
93 // Configuration address register
94 struct pci_addr_reg addr_reg;
96 // Base IO Port which PCI devices will register with...
100 struct pci_bus bus_list[PCI_BUS_COUNT];
107 #ifdef CONFIG_DEBUG_PCI
109 static void pci_dump_state(struct pci_internal * pci_state) {
110 struct rb_node * node = v3_rb_first(&(pci_state->bus_list[0].devices));
111 struct pci_device * tmp_dev = NULL;
113 PrintDebug("===PCI: Dumping state Begin ==========\n");
116 tmp_dev = rb_entry(node, struct pci_device, dev_tree_node);
118 PrintDebug("PCI Device Number: %d (%s):\n", tmp_dev->dev_num, tmp_dev->name);
119 PrintDebug("irq = %d\n", tmp_dev->config_header.intr_line);
120 PrintDebug("Vend ID: 0x%x\n", tmp_dev->config_header.vendor_id);
121 PrintDebug("Device ID: 0x%x\n", tmp_dev->config_header.device_id);
123 } while ((node = v3_rb_next(node)));
125 PrintDebug("====PCI: Dumping state End==========\n");
133 // Scan the dev_map bitmap for the first '0' bit
134 static int get_free_dev_num(struct pci_bus * bus) {
137 for (i = 0; i < sizeof(bus->dev_map); i++) {
138 PrintDebug("i=%d\n", i);
139 if (bus->dev_map[i] != 0xff) {
141 for (j = 0; j < 8; j++) {
142 PrintDebug("\tj=%d\n", j);
143 if (!(bus->dev_map[i] & (0x1 << j))) {
144 return ((i * 8) + j);
153 static void allocate_dev_num(struct pci_bus * bus, int dev_num) {
154 int major = (dev_num / 8);
155 int minor = dev_num % 8;
157 bus->dev_map[major] |= (0x1 << minor);
163 struct pci_device * __add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
165 struct rb_node ** p = &(bus->devices.rb_node);
166 struct rb_node * parent = NULL;
167 struct pci_device * tmp_dev = NULL;
171 tmp_dev = rb_entry(parent, struct pci_device, dev_tree_node);
173 if (dev->devfn < tmp_dev->devfn) {
175 } else if (dev->devfn > tmp_dev->devfn) {
182 rb_link_node(&(dev->dev_tree_node), parent, p);
189 struct pci_device * add_device_to_bus(struct pci_bus * bus, struct pci_device * dev) {
191 struct pci_device * ret = NULL;
193 if ((ret = __add_device_to_bus(bus, dev))) {
197 v3_rb_insert_color(&(dev->dev_tree_node), &(bus->devices));
199 allocate_dev_num(bus, dev->dev_num);
205 static struct pci_device * get_device(struct pci_bus * bus, uint8_t dev_num, uint8_t fn_num) {
206 struct rb_node * n = bus->devices.rb_node;
207 struct pci_device * dev = NULL;
208 uint8_t devfn = ((dev_num & 0x1f) << 3) | (fn_num & 0x7);
211 dev = rb_entry(n, struct pci_device, dev_tree_node);
213 if (devfn < dev->devfn) {
215 } else if (devfn > dev->devfn) {
231 static int addr_port_read(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
232 struct pci_internal * pci_state = priv_data;
233 int reg_offset = port & 0x3;
234 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
236 PrintDebug("Reading PCI Address Port (%x): %x len=%d\n", port, pci_state->addr_reg.val, length);
239 if (reg_offset != 0) {
240 PrintError("Invalid Address Port Read\n");
243 *(uint32_t *)dst = *(uint32_t *)reg_addr;
244 } else if (length == 2) {
245 if (reg_offset > 2) {
246 PrintError("Invalid Address Port Read\n");
249 *(uint16_t *)dst = *(uint16_t *)reg_addr;
250 } else if (length == 1) {
251 *(uint8_t *)dst = *(uint8_t *)reg_addr;
253 PrintError("Invalid read length (%d) for PCI address register\n", length);
262 static int addr_port_write(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
263 struct pci_internal * pci_state = priv_data;
264 int reg_offset = port & 0x3;
265 uint8_t * reg_addr = ((uint8_t *)&(pci_state->addr_reg.val)) + reg_offset;
269 if (reg_offset != 0) {
270 PrintError("Invalid Address Port Write\n");
274 PrintDebug("Writing PCI 4 bytes Val=%x\n", *(uint32_t *)src);
276 *(uint32_t *)reg_addr = *(uint32_t *)src;
277 } else if (length == 2) {
278 if (reg_offset > 2) {
279 PrintError("Invalid Address Port Write\n");
283 PrintDebug("Writing PCI 2 byte Val=%x\n", *(uint16_t *)src);
285 *(uint16_t *)reg_addr = *(uint16_t *)src;
286 } else if (length == 1) {
287 PrintDebug("Writing PCI 1 byte Val=%x\n", *(uint8_t *)src);
288 *(uint8_t *)reg_addr = *(uint8_t *)src;
290 PrintError("Invalid write length (%d) for PCI address register\n", length);
294 PrintDebug("Writing PCI Address Port(%x): %x\n", port, pci_state->addr_reg.val);
300 static int data_port_read(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
301 struct pci_internal * pci_state = priv_data;
302 struct pci_device * pci_dev = NULL;
303 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
306 if (pci_state->addr_reg.bus_num != 0) {
308 for (i = 0; i < length; i++) {
309 *((uint8_t *)dst + i) = 0xff;
315 PrintDebug("Reading PCI Data register. bus = %d, dev = %d, reg = %d (%x), cfg_reg = %x\n",
316 pci_state->addr_reg.bus_num,
317 pci_state->addr_reg.dev_num,
319 pci_state->addr_reg.val);
321 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
323 if (pci_dev == NULL) {
324 for (i = 0; i < length; i++) {
325 *(uint8_t *)((uint8_t *)dst + i) = 0xff;
331 if (pci_dev->type == PCI_PASSTHROUGH) {
332 if (pci_dev->config_read(reg_num, dst, length, pci_dev->priv_data) == -1) {
333 PrintError("Failed to handle configuration update for passthrough pci_device\n");
340 for (i = 0; i < length; i++) {
341 *(uint8_t *)((uint8_t *)dst + i) = pci_dev->config_space[reg_num + i];
344 PrintDebug("\tVal=%x, len=%d\n", *(uint32_t *)dst, length);
350 static inline int is_cfg_reg_writable(uchar_t header_type, int reg_num) {
351 if (header_type == 0x00) {
369 } else if (header_type == 0x80) {
388 // PCI to PCI Bridge = 0x01
389 // CardBus Bridge = 0x02
392 PrintError("Invalid PCI Header type (0x%.2x)\n", header_type);
398 static int bar_update(struct guest_info * info, struct pci_device * pci, int bar_num, uint32_t new_val) {
399 struct v3_pci_bar * bar = &(pci->bar[bar_num]);
401 PrintDebug("Updating BAR Register (Dev=%s) (bar=%d) (old_val=0x%x) (new_val=0x%x)\n",
402 pci->name, bar_num, bar->val, new_val);
408 PrintDebug("\tRehooking %d IO ports from base 0x%x to 0x%x for %d ports\n",
409 bar->num_ports, PCI_IO_BASE(bar->val), PCI_IO_BASE(new_val),
412 // only do this if pci device is enabled....
413 if (!(pci->config_header.status & 0x1)) {
414 PrintError("PCI Device IO space not enabled\n");
417 for (i = 0; i < bar->num_ports; i++) {
419 PrintDebug("Rehooking PCI IO port (old port=%u) (new port=%u)\n",
420 PCI_IO_BASE(bar->val) + i, PCI_IO_BASE(new_val) + i);
422 v3_unhook_io_port(info->vm_info, PCI_IO_BASE(bar->val) + i);
424 if (v3_hook_io_port(info->vm_info, PCI_IO_BASE(new_val) + i,
425 bar->io_read, bar->io_write,
426 bar->private_data) == -1) {
428 PrintError("Could not hook PCI IO port (old port=%u) (new port=%u)\n",
429 PCI_IO_BASE(bar->val) + i, PCI_IO_BASE(new_val) + i);
430 v3_print_io_map(info->vm_info);
439 case PCI_BAR_MEM32: {
440 v3_unhook_mem(info->vm_info, V3_MEM_CORE_ANY, (addr_t)(bar->val));
443 v3_hook_full_mem(info->vm_info, V3_MEM_CORE_ANY, PCI_MEM32_BASE(new_val),
444 PCI_MEM32_BASE(new_val) + (bar->num_pages * PAGE_SIZE_4KB),
445 bar->mem_read, bar->mem_write, pci->priv_data);
447 PrintError("Write hooks not supported for PCI\n");
456 PrintDebug("Reprogramming an unsupported BAR register (Dev=%s) (bar=%d) (val=%x)\n",
457 pci->name, bar_num, new_val);
461 PrintError("Invalid Bar Reg updated (bar=%d)\n", bar_num);
469 static int data_port_write(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
470 struct pci_internal * pci_state = priv_data;
471 struct pci_device * pci_dev = NULL;
472 uint_t reg_num = (pci_state->addr_reg.reg_num << 2) + (port & 0x3);
476 if (pci_state->addr_reg.bus_num != 0) {
480 PrintDebug("Writing PCI Data register. bus = %d, dev = %d, fn = %d, reg = %d (0x%x) addr_reg = 0x%x (val=0x%x, len=%d)\n",
481 pci_state->addr_reg.bus_num,
482 pci_state->addr_reg.dev_num,
483 pci_state->addr_reg.fn_num,
485 pci_state->addr_reg.val,
486 *(uint32_t *)src, length);
489 pci_dev = get_device(&(pci_state->bus_list[0]), pci_state->addr_reg.dev_num, pci_state->addr_reg.fn_num);
491 if (pci_dev == NULL) {
492 PrintError("Writing configuration space for non-present device (dev_num=%d)\n",
493 pci_state->addr_reg.dev_num);
497 if (pci_dev->type == PCI_PASSTHROUGH) {
498 if (pci_dev->config_write(reg_num, src, length, pci_dev->priv_data) == -1) {
499 PrintError("Failed to handle configuration update for passthrough pci_device\n");
507 for (i = 0; i < length; i++) {
508 uint_t cur_reg = reg_num + i;
509 int writable = is_cfg_reg_writable(pci_dev->config_header.header_type, cur_reg);
511 if (writable == -1) {
512 PrintError("Invalid PCI configuration space\n");
517 pci_dev->config_space[cur_reg] = *(uint8_t *)((uint8_t *)src + i);
519 if ((cur_reg >= 0x10) && (cur_reg < 0x28)) {
520 // BAR Register Update
521 int bar_reg = ((cur_reg & ~0x3) - 0x10) / 4;
523 pci_dev->bar_update_flag = 1;
524 pci_dev->bar[bar_reg].updated = 1;
526 // PrintDebug("Updating BAR register %d\n", bar_reg);
528 } else if ((cur_reg >= 0x30) && (cur_reg < 0x34)) {
529 // Extension ROM update
531 pci_dev->exp_rom_update_flag = 1;
532 } else if (cur_reg == 0x04) {
534 uint8_t command = *((uint8_t *)src + i);
536 PrintError("command update for %s old=%x new=%x\n",
538 pci_dev->config_space[cur_reg],command);
540 pci_dev->config_space[cur_reg] = command;
542 if (pci_dev->cmd_update) {
543 pci_dev->cmd_update(pci_dev, (command & 0x01), (command & 0x02));
546 } else if (cur_reg == 0x0f) {
548 pci_dev->config_header.BIST = 0x00;
551 PrintError("PCI Write to read only register %d\n", cur_reg);
555 if (pci_dev->config_update) {
556 pci_dev->config_update(reg_num, src, length, pci_dev->priv_data);
559 // Scan for BAR updated
560 if (pci_dev->bar_update_flag) {
561 for (i = 0; i < 6; i++) {
562 if (pci_dev->bar[i].updated) {
563 int bar_offset = 0x10 + 4 * i;
566 if (pci_dev->bar[i].type == PCI_BAR_PASSTHROUGH) {
567 if (pci_dev->bar[i].bar_write(i, (uint32_t *)(pci_dev->config_space + bar_offset), pci_dev->bar[i].private_data) == -1) {
568 PrintError("Error in passthrough bar write operation\n");
573 *(uint32_t *)(pci_dev->config_space + bar_offset) &= pci_dev->bar[i].mask;
574 // check special flags....
577 if (bar_update(core, pci_dev, i, *(uint32_t *)(pci_dev->config_space + bar_offset)) == -1) {
578 PrintError("PCI Device %s: Bar update Error Bar=%d\n", pci_dev->name, i);
583 pci_dev->bar[i].updated = 0;
586 pci_dev->bar_update_flag = 0;
589 if ((pci_dev->exp_rom_update_flag) && (pci_dev->exp_rom_update)) {
590 pci_dev->exp_rom_update(pci_dev, &(pci_dev->config_header.expansion_rom_address), pci_dev->priv_data);
591 pci_dev->exp_rom_update_flag = 0;
602 static void init_pci_busses(struct pci_internal * pci_state) {
605 for (i = 0; i < PCI_BUS_COUNT; i++) {
606 pci_state->bus_list[i].bus_num = i;
607 pci_state->bus_list[i].devices.rb_node = NULL;
608 memset(pci_state->bus_list[i].dev_map, 0, sizeof(pci_state->bus_list[i].dev_map));
613 static int pci_free(struct pci_internal * pci_state) {
615 // cleanup devices (?)
622 static struct v3_device_ops dev_ops = {
623 .free = (int (*)(void *))pci_free,
630 static int pci_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
631 struct pci_internal * pci_state = V3_Malloc(sizeof(struct pci_internal));
633 char * dev_id = v3_cfg_val(cfg, "ID");
636 PrintDebug("PCI internal at %p\n",(void *)pci_state);
638 struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, pci_state);
641 PrintError("Could not attach device %s\n", dev_id);
647 pci_state->addr_reg.val = 0;
648 pci_state->dev_io_base = PCI_DEV_IO_PORT_BASE;
650 init_pci_busses(pci_state);
652 PrintDebug("Sizeof config header=%d\n", (int)sizeof(struct pci_config_header));
654 for (i = 0; i < 4; i++) {
655 ret |= v3_dev_hook_io(dev, CONFIG_ADDR_PORT + i, &addr_port_read, &addr_port_write);
656 ret |= v3_dev_hook_io(dev, CONFIG_DATA_PORT + i, &data_port_read, &data_port_write);
660 PrintError("Error hooking PCI IO ports\n");
661 v3_remove_device(dev);
669 device_register("PCI", pci_init)
672 static inline int init_bars(struct v3_vm_info * vm, struct pci_device * pci_dev) {
675 for (i = 0; i < 6; i++) {
676 int bar_offset = 0x10 + (4 * i);
678 if (pci_dev->bar[i].type == PCI_BAR_IO) {
680 pci_dev->bar[i].mask = (~((pci_dev->bar[i].num_ports) - 1)) | 0x01;
682 if (pci_dev->bar[i].default_base_port != 0xffff) {
683 pci_dev->bar[i].val = pci_dev->bar[i].default_base_port & pci_dev->bar[i].mask;
685 pci_dev->bar[i].val = 0;
688 pci_dev->bar[i].val |= 0x00000001;
690 for (j = 0; j < pci_dev->bar[i].num_ports; j++) {
692 if (pci_dev->bar[i].default_base_port != 0xffff) {
693 if (v3_hook_io_port(vm, pci_dev->bar[i].default_base_port + j,
694 pci_dev->bar[i].io_read, pci_dev->bar[i].io_write,
695 pci_dev->bar[i].private_data) == -1) {
696 PrintError("Could not hook default io port %x\n", pci_dev->bar[i].default_base_port + j);
702 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
704 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
705 pci_dev->bar[i].mask = ~((pci_dev->bar[i].num_pages << 12) - 1);
706 pci_dev->bar[i].mask |= 0xf; // preserve the configuration flags
708 if (pci_dev->bar[i].default_base_addr != 0xffffffff) {
709 pci_dev->bar[i].val = pci_dev->bar[i].default_base_addr & pci_dev->bar[i].mask;
711 pci_dev->bar[i].val = 0;
715 if (pci_dev->bar[i].mem_read) {
717 v3_hook_full_mem(vm, V3_MEM_CORE_ANY, pci_dev->bar[i].default_base_addr,
718 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
719 pci_dev->bar[i].mem_read, pci_dev->bar[i].mem_write, pci_dev->priv_data);
720 } else if (pci_dev->bar[i].mem_write) {
722 PrintError("Write hooks not supported for PCI devices\n");
725 v3_hook_write_mem(pci_dev->vm_dev->vm, pci_dev->bar[i].default_base_addr,
726 pci_dev->bar[i].default_base_addr + (pci_dev->bar[i].num_pages * PAGE_SIZE_4KB),
727 pci_dev->bar[i].mem_write, pci_dev->vm_dev);
730 // set the prefetchable flag...
731 pci_dev->bar[i].val |= 0x00000008;
735 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
737 } else if (pci_dev->bar[i].type == PCI_BAR_MEM24) {
738 PrintError("16 Bit memory ranges not supported (reg: %d)\n", i);
740 } else if (pci_dev->bar[i].type == PCI_BAR_NONE) {
741 pci_dev->bar[i].val = 0x00000000;
742 pci_dev->bar[i].mask = 0x00000000; // This ensures that all updates will be dropped
743 *(uint32_t *)(pci_dev->config_space + bar_offset) = pci_dev->bar[i].val;
744 } else if (pci_dev->bar[i].type == PCI_BAR_PASSTHROUGH) {
746 // Call the bar init function to get the local cached value
747 pci_dev->bar[i].bar_init(i, &(pci_dev->bar[i].val), pci_dev->bar[i].private_data);
750 PrintError("Invalid BAR type for bar #%d\n", i);
759 int v3_pci_set_irq_bridge(struct vm_device * pci_bus, int bus_num,
760 int (*raise_pci_irq)(struct pci_device * pci_dev, void * dev_data),
761 int (*lower_pci_irq)(struct pci_device * pci_dev, void * dev_data),
763 struct pci_internal * pci_state = (struct pci_internal *)pci_bus->private_data;
766 pci_state->bus_list[bus_num].raise_pci_irq = raise_pci_irq;
767 pci_state->bus_list[bus_num].lower_pci_irq = lower_pci_irq;
768 pci_state->bus_list[bus_num].irq_dev_data = priv_data;
773 int v3_pci_raise_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev) {
774 struct pci_internal * pci_state = (struct pci_internal *)pci_bus->private_data;
775 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
777 return bus->raise_pci_irq(dev, bus->irq_dev_data);
780 int v3_pci_lower_irq(struct vm_device * pci_bus, int bus_num, struct pci_device * dev) {
781 struct pci_internal * pci_state = (struct pci_internal *)pci_bus->private_data;
782 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
784 return bus->lower_pci_irq(dev, bus->irq_dev_data);
787 // if dev_num == -1, auto assign
788 struct pci_device * v3_pci_register_device(struct vm_device * pci,
789 pci_device_type_t dev_type,
794 struct v3_pci_bar * bars,
795 int (*config_update)(uint_t reg_num, void * src, uint_t length, void * priv_data),
796 int (*cmd_update)(struct pci_device * pci_dev, uchar_t io_enabled, uchar_t mem_enabled),
797 int (*exp_rom_update)(struct pci_device * pci_dev, uint32_t * src, void * priv_data),
800 struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
801 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
802 struct pci_device * pci_dev = NULL;
805 if (dev_num > MAX_BUS_DEVICES) {
806 PrintError("Requested Invalid device number (%d)\n", dev_num);
810 if (dev_num == PCI_AUTO_DEV_NUM) {
811 PrintDebug("Searching for free device number\n");
812 if ((dev_num = get_free_dev_num(bus)) == -1) {
813 PrintError("No more available PCI slots on bus %d\n", bus->bus_num);
818 PrintDebug("Checking for PCI Device\n");
820 if (get_device(bus, dev_num, fn_num) != NULL) {
821 PrintError("PCI Device already registered at slot %d on bus %d\n",
822 dev_num, bus->bus_num);
827 pci_dev = (struct pci_device *)V3_Malloc(sizeof(struct pci_device));
829 if (pci_dev == NULL) {
830 PrintError("Could not allocate pci device\n");
834 memset(pci_dev, 0, sizeof(struct pci_device));
837 pci_dev->type = dev_type;
839 switch (pci_dev->type) {
841 pci_dev->config_header.header_type = 0x00;
843 case PCI_MULTIFUNCTION:
844 pci_dev->config_header.header_type = 0x80;
847 PrintError("Unhandled PCI Device Type: %d\n", dev_type);
853 pci_dev->bus_num = bus_num;
854 pci_dev->dev_num = dev_num;
855 pci_dev->fn_num = fn_num;
857 strncpy(pci_dev->name, name, sizeof(pci_dev->name));
858 pci_dev->priv_data = priv_data;
860 // register update callbacks
861 pci_dev->config_update = config_update;
862 pci_dev->cmd_update = cmd_update;
863 pci_dev->exp_rom_update = exp_rom_update;
867 for (i = 0; i < 6; i ++) {
868 pci_dev->bar[i].type = bars[i].type;
869 pci_dev->bar[i].private_data = bars[i].private_data;
871 if (pci_dev->bar[i].type == PCI_BAR_IO) {
872 pci_dev->bar[i].num_ports = bars[i].num_ports;
874 // This is a horrible HACK becaues the BIOS is supposed to set the PCI base ports
875 // And if the BIOS doesn't, Linux just happily overlaps device port assignments
876 if (bars[i].default_base_port != (uint16_t)-1) {
877 pci_dev->bar[i].default_base_port = bars[i].default_base_port;
879 pci_dev->bar[i].default_base_port = pci_state->dev_io_base;
880 pci_state->dev_io_base += ( 0x100 * ((bars[i].num_ports / 0x100) + 1) );
883 pci_dev->bar[i].io_read = bars[i].io_read;
884 pci_dev->bar[i].io_write = bars[i].io_write;
885 } else if (pci_dev->bar[i].type == PCI_BAR_MEM32) {
886 pci_dev->bar[i].num_pages = bars[i].num_pages;
887 pci_dev->bar[i].default_base_addr = bars[i].default_base_addr;
888 pci_dev->bar[i].mem_read = bars[i].mem_read;
889 pci_dev->bar[i].mem_write = bars[i].mem_write;
890 } else if (pci_dev->bar[i].type == PCI_BAR_PASSTHROUGH) {
891 pci_dev->bar[i].bar_init = bars[i].bar_init;
892 pci_dev->bar[i].bar_write = bars[i].bar_write;
894 pci_dev->bar[i].num_pages = 0;
895 pci_dev->bar[i].default_base_addr = 0;
896 pci_dev->bar[i].mem_read = NULL;
897 pci_dev->bar[i].mem_write = NULL;
901 if (init_bars(pci->vm, pci_dev) == -1) {
902 PrintError("could not initialize bar registers\n");
907 add_device_to_bus(bus, pci_dev);
909 #ifdef CONFIG_DEBUG_PCI
910 pci_dump_state(pci_state);
918 // if dev_num == -1, auto assign
919 struct pci_device * v3_pci_register_passthrough_device(struct vm_device * pci,
924 int (*config_write)(uint_t reg_num, void * src, uint_t length, void * private_data),
925 int (*config_read)(uint_t reg_num, void * dst, uint_t length, void * private_data),
926 void * private_data) {
928 struct pci_internal * pci_state = (struct pci_internal *)pci->private_data;
929 struct pci_bus * bus = &(pci_state->bus_list[bus_num]);
930 struct pci_device * pci_dev = NULL;
932 if (dev_num > MAX_BUS_DEVICES) {
933 PrintError("Requested Invalid device number (%d)\n", dev_num);
937 if (dev_num == PCI_AUTO_DEV_NUM) {
938 PrintDebug("Searching for free device number\n");
939 if ((dev_num = get_free_dev_num(bus)) == -1) {
940 PrintError("No more available PCI slots on bus %d\n", bus->bus_num);
945 PrintDebug("Checking for PCI Device\n");
947 if (get_device(bus, dev_num, fn_num) != NULL) {
948 PrintError("PCI Device already registered at slot %d on bus %d\n",
949 dev_num, bus->bus_num);
954 pci_dev = (struct pci_device *)V3_Malloc(sizeof(struct pci_device));
956 if (pci_dev == NULL) {
957 PrintError("Could not allocate pci device\n");
961 memset(pci_dev, 0, sizeof(struct pci_device));
963 pci_dev->bus_num = bus_num;
964 pci_dev->dev_num = dev_num;
965 pci_dev->fn_num = fn_num;
967 strncpy(pci_dev->name, name, sizeof(pci_dev->name));
968 pci_dev->priv_data = private_data;
970 // register update callbacks
971 pci_dev->config_write = config_write;
972 pci_dev->config_read = config_read;
975 add_device_to_bus(bus, pci_dev);
977 #ifdef CONFIG_DEBUG_PCI
978 pci_dump_state(pci_state);