2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm.h>
21 #include <devices/ide.h>
22 #include <devices/pci.h>
23 #include "ide-types.h"
24 #include "atapi-types.h"
26 #define PRI_DEFAULT_IRQ 14
27 #define SEC_DEFAULT_IRQ 15
30 #define PRI_DATA_PORT 0x1f0
31 #define PRI_FEATURES_PORT 0x1f1
32 #define PRI_SECT_CNT_PORT 0x1f2
33 #define PRI_SECT_NUM_PORT 0x1f3
34 #define PRI_CYL_LOW_PORT 0x1f4
35 #define PRI_CYL_HIGH_PORT 0x1f5
36 #define PRI_DRV_SEL_PORT 0x1f6
37 #define PRI_CMD_PORT 0x1f7
38 #define PRI_CTRL_PORT 0x3f6
39 #define PRI_ADDR_REG_PORT 0x3f7
41 #define SEC_DATA_PORT 0x170
42 #define SEC_FEATURES_PORT 0x171
43 #define SEC_SECT_CNT_PORT 0x172
44 #define SEC_SECT_NUM_PORT 0x173
45 #define SEC_CYL_LOW_PORT 0x174
46 #define SEC_CYL_HIGH_PORT 0x175
47 #define SEC_DRV_SEL_PORT 0x176
48 #define SEC_CMD_PORT 0x177
49 #define SEC_CTRL_PORT 0x376
50 #define SEC_ADDR_REG_PORT 0x377
53 #define PRI_DMA_CMD_PORT 0xc000
54 #define PRI_DMA_STATUS_PORT 0xc002
55 #define PRI_DMA_PRD_PORT0 0xc004
56 #define PRI_DMA_PRD_PORT1 0xc005
57 #define PRI_DMA_PRD_PORT2 0xc006
58 #define PRI_DMA_PRD_PORT3 0xc007
60 #define SEC_DMA_CMD_PORT 0xc008
61 #define SEC_DMA_STATUS_PORT 0xc00a
62 #define SEC_DMA_PRD_PORT0 0xc00c
63 #define SEC_DMA_PRD_PORT1 0xc00d
64 #define SEC_DMA_PRD_PORT2 0xc00e
65 #define SEC_DMA_PRD_PORT3 0xc00f
67 #define DATA_BUFFER_SIZE 2048
69 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
70 "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD",
71 "PRI_CTRL", "PRI_ADDR_REG"};
74 static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM",
75 "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD",
76 "SEC_CTRL", "SEC_ADDR_REG"};
78 static const char * ide_dma_port_strs[] = {"PRI_DMA_CMD", NULL,
79 "PRI_DMA_STATUS", NULL,
80 "PRI_DMA_PRD0", "PRI_DMA_PRD1",
81 "PRI_DMA_PRD2", "PRI_DMA_PRD3",
83 "SEC_DMA_STATUS", NULL,
84 "SEC_DMA_PRD0","SEC_DMA_PRD1",
85 "SEC_DMA_PRD2","SEC_DMA_PRD3"};
89 static inline const char * io_port_to_str(uint16_t port) {
90 if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) {
91 return ide_pri_port_strs[port - PRI_DATA_PORT];
92 } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) {
93 return ide_sec_port_strs[port - SEC_DATA_PORT];
94 } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) {
95 return ide_pri_port_strs[port - PRI_CTRL_PORT + 8];
96 } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) {
97 return ide_sec_port_strs[port - SEC_CTRL_PORT + 8];
98 } else if ((port >= PRI_DMA_CMD_PORT) && (port <= SEC_DMA_PRD_PORT3)) {
99 return ide_dma_port_strs[port - PRI_DMA_CMD_PORT];
106 static const char * ide_dev_type_strs[] = {"HARDDISK", "CDROM", "NONE"};
109 static inline const char * device_type_to_str(v3_ide_dev_type_t type) {
114 return ide_dev_type_strs[type];
119 struct ide_cd_state {
120 struct atapi_sense_data sense;
123 struct atapi_error_recovery err_recovery;
126 struct ide_hd_state {
133 v3_ide_dev_type_t drive_type;
136 struct v3_ide_cd_ops * cd_ops;
137 struct v3_ide_hd_ops * hd_ops;
142 struct ide_cd_state cd_state;
143 struct ide_hd_state hd_state;
148 // Where we are in the data transfer
149 uint_t transfer_index;
151 // the length of a transfer
152 // calculated for easy access
153 uint_t transfer_length;
156 // We have a local data buffer that we use for IO port accesses
157 uint8_t data_buf[DATA_BUFFER_SIZE];
163 uint8_t sector_count; // 0x1f2,0x172
164 struct atapi_irq_flags irq_flags;
165 } __attribute__((packed));
168 uint8_t sector_num; // 0x1f3,0x173
178 uint8_t cylinder_low; // 0x1f4,0x174
179 uint8_t cylinder_high; // 0x1f5,0x175
180 } __attribute__((packed));
185 } __attribute__((packed));
188 // The transfer length requested by the CPU
190 } __attribute__((packed));
192 struct ide_dma_cmd_reg dma_cmd;
193 struct ide_dma_status_reg dma_status;
194 uint32_t dma_prd_addr;
201 struct ide_drive drives[2];
204 struct ide_error_reg error_reg; // [read] 0x1f1,0x171
206 struct ide_features_reg features;
208 struct ide_drive_head_reg drive_head; // 0x1f6,0x176
210 struct ide_status_reg status; // [read] 0x1f7,0x177
211 uint8_t cmd_reg; // [write] 0x1f7,0x177
213 int irq; // this is temporary until we add PCI support
215 struct pci_device * pci_dev;
218 struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
223 struct ide_internal {
224 struct ide_channel channels[2];
225 struct vm_device * pci;
226 struct pci_device * busmaster_pci;
231 static inline uint16_t be_to_le_16(const uint16_t val) {
232 uint8_t * buf = (uint8_t *)&val;
233 return (buf[0] << 8) | (buf[1]) ;
236 static inline uint16_t le_to_be_16(const uint16_t val) {
237 return be_to_le_16(val);
241 static inline uint32_t be_to_le_32(const uint32_t val) {
242 uint8_t * buf = (uint8_t *)&val;
243 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
246 static inline uint32_t le_to_be_32(const uint32_t val) {
247 return be_to_le_32(val);
251 static inline int get_channel_index(ushort_t port) {
252 if (((port & 0xfff8) == 0x1f0) ||
253 ((port & 0xfffe) == 0x3f6) ||
254 ((port & 0xfff8) == 0xc000)) {
256 } else if (((port & 0xfff8) == 0x170) ||
257 ((port & 0xfffe) == 0x376) ||
258 ((port & 0xfff8) == 0xc008)) {
265 static inline struct ide_channel * get_selected_channel(struct ide_internal * ide, ushort_t port) {
266 int channel_idx = get_channel_index(port);
267 return &(ide->channels[channel_idx]);
270 static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
271 return &(channel->drives[channel->drive_head.drive_sel]);
275 static inline int is_lba_enabled(struct ide_channel * channel) {
276 return channel->drive_head.lba_mode;
280 static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) {
281 if (channel->ctrl_reg.irq_disable == 0) {
282 v3_raise_irq(dev->vm, channel->irq);
287 static void drive_reset(struct ide_drive * drive) {
288 drive->sector_count = 0x01;
289 drive->sector_num = 0x01;
291 if (drive->drive_type == IDE_CDROM) {
292 drive->cylinder = 0xeb14;
294 drive->cylinder = 0x0000;
298 memset(drive->data_buf, 0, sizeof(drive->data_buf));
299 drive->transfer_index = 0;
301 // Send the reset signal to the connected device callbacks
302 // channel->drives[0].reset();
303 // channel->drives[1].reset();
306 static void channel_reset(struct ide_channel * channel) {
308 // set busy and seek complete flags
309 channel->status.val = 0x90;
312 channel->error_reg.val = 0x01;
315 channel->cmd_reg = 0x00;
317 channel->ctrl_reg.irq_disable = 0;
320 static void channel_reset_complete(struct ide_channel * channel) {
321 channel->status.busy = 0;
322 channel->status.ready = 1;
324 channel->drive_head.head_num = 0;
326 drive_reset(&(channel->drives[0]));
327 drive_reset(&(channel->drives[1]));
331 static void ide_abort_command(struct vm_device * dev, struct ide_channel * channel) {
332 channel->status.val = 0x41; // Error + ready
333 channel->error_reg.val = 0x04; // No idea...
335 ide_raise_irq(dev, channel);
339 // Include the ATAPI interface handlers
343 static int write_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
344 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
345 struct ide_channel * channel = get_selected_channel(ide, port);
346 struct ide_drive * drive = get_selected_drive(channel);
349 PrintError("IDE: Invalid Write length on IDE port %x\n", port);
353 PrintDebug("IDE: Writing DMA Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
356 case PRI_DMA_CMD_PORT:
357 case SEC_DMA_CMD_PORT:
358 drive->dma_cmd.val = *(uint8_t *)src;
361 case PRI_DMA_STATUS_PORT:
362 case SEC_DMA_STATUS_PORT:
363 drive->dma_status.val = *(uint8_t *)src;
366 case PRI_DMA_PRD_PORT0:
367 case PRI_DMA_PRD_PORT1:
368 case PRI_DMA_PRD_PORT2:
369 case PRI_DMA_PRD_PORT3:
370 case SEC_DMA_PRD_PORT0:
371 case SEC_DMA_PRD_PORT1:
372 case SEC_DMA_PRD_PORT2:
373 case SEC_DMA_PRD_PORT3: {
374 uint_t addr_index = port & 0x3;
375 uint8_t * addr_buf = (uint8_t *)&(drive->dma_prd_addr);
377 addr_buf[addr_index] = *(uint8_t *)src;
381 PrintError("IDE: Invalid DMA Port (%x)\n", port);
389 static int read_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
390 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
391 struct ide_channel * channel = get_selected_channel(ide, port);
392 struct ide_drive * drive = get_selected_drive(channel);
395 PrintError("IDE: Invalid Write length on IDE port %x\n", port);
402 case PRI_DMA_CMD_PORT:
403 case SEC_DMA_CMD_PORT:
404 *(uint8_t *)dst = drive->dma_cmd.val;
407 case PRI_DMA_STATUS_PORT:
408 case SEC_DMA_STATUS_PORT:
409 *(uint8_t *)dst = drive->dma_status.val;
412 case PRI_DMA_PRD_PORT0:
413 case PRI_DMA_PRD_PORT1:
414 case PRI_DMA_PRD_PORT2:
415 case PRI_DMA_PRD_PORT3:
416 case SEC_DMA_PRD_PORT0:
417 case SEC_DMA_PRD_PORT1:
418 case SEC_DMA_PRD_PORT2:
419 case SEC_DMA_PRD_PORT3: {
420 uint_t addr_index = port & 0x3;
421 uint8_t * addr_buf = (uint8_t *)&(drive->dma_prd_addr);
423 *(uint8_t *)dst = addr_buf[addr_index];
427 PrintError("IDE: Invalid DMA Port (%x)\n", port);
431 PrintDebug("IDE: Reading DMA Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)dst);
438 static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
439 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
440 struct ide_channel * channel = get_selected_channel(ide, port);
441 struct ide_drive * drive = get_selected_drive(channel);
444 PrintError("Invalid Write Length on IDE command Port %x\n", port);
448 PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
450 channel->cmd_reg = *(uint8_t *)src;
452 switch (channel->cmd_reg) {
454 case 0xa0: // ATAPI Command Packet
455 if (drive->drive_type != IDE_CDROM) {
456 ide_abort_command(dev, channel);
459 drive->sector_count = 1;
461 channel->status.busy = 0;
462 channel->status.write_fault = 0;
463 channel->status.data_req = 1;
464 channel->status.error = 0;
466 // reset the data buffer...
467 drive->transfer_length = ATAPI_PACKET_SIZE;
468 drive->transfer_index = 0;
471 case 0xa1: // ATAPI Identify Device Packet
472 atapi_identify_device(drive);
474 channel->error_reg.val = 0;
475 channel->status.val = 0x58; // ready, data_req, seek_complete
477 ide_raise_irq(dev, channel);
479 case 0xec: // Identify Device
480 if (drive->drive_type != IDE_DISK) {
483 // JRL: Should we abort here?
484 ide_abort_command(dev, channel);
486 PrintError("IDE Disks currently not implemented\n");
491 PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
499 static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
500 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
501 struct ide_channel * channel = get_selected_channel(ide, port);
502 struct ide_drive * drive = get_selected_drive(channel);
504 // PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n",
505 // port, *(uint32_t *)src, length);
507 memcpy(drive->data_buf + drive->transfer_index, src, length);
508 drive->transfer_index += length;
510 // Transfer is complete, dispatch the command
511 if (drive->transfer_index >= drive->transfer_length) {
512 switch (channel->cmd_reg) {
513 case 0x30: // Write Sectors
514 PrintError("Writing Data not yet implemented\n");
517 case 0xa0: // ATAPI packet command
518 if (atapi_handle_packet(dev, channel) == -1) {
519 PrintError("Error handling ATAPI packet\n");
524 PrintError("Unhandld IDE Command %x\n", channel->cmd_reg);
533 static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
534 PrintError("Harddrive data port read not implemented\n");
540 static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
541 struct ide_drive * drive = get_selected_drive(channel);
542 int data_offset = drive->transfer_index % DATA_BUFFER_SIZE;
543 int req_offset = drive->transfer_index % drive->req_len;
545 if (drive->cd_state.atapi_cmd != 0x28) {
546 PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len);
549 if (drive->transfer_index >= drive->transfer_length) {
550 PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n",
551 drive->transfer_length, drive->transfer_index,
552 drive->transfer_index + length);
558 if ((data_offset == 0) && (drive->transfer_index > 0)) {
560 if (drive->drive_type == IDE_CDROM) {
561 if (atapi_update_data_buf(dev, channel) == -1) {
562 PrintError("Could not update CDROM data buffer\n");
566 PrintError("IDE Harddrives not implemented\n");
571 memcpy(dst, drive->data_buf + data_offset, length);
573 drive->transfer_index += length;
575 if ((req_offset == 0) && (drive->transfer_index > 0)) {
576 if (drive->transfer_index < drive->transfer_length) {
577 // An increment is complete, but there is still more data to be transferred...
579 channel->status.data_req = 1;
581 drive->irq_flags.c_d = 0;
583 // Update the request length in the cylinder regs
584 if (atapi_update_req_len(dev, channel, drive->transfer_length - drive->transfer_index) == -1) {
585 PrintError("Could not update request length after completed increment\n");
589 // This was the final read of the request
590 channel->status.data_req = 0;
591 channel->status.ready = 1;
593 drive->irq_flags.c_d = 1;
594 drive->irq_flags.rel = 0;
597 drive->irq_flags.io_dir = 1;
598 channel->status.busy = 0;
600 ide_raise_irq(dev, channel);
607 static int read_drive_id(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
608 struct ide_drive * drive = get_selected_drive(channel);
610 channel->status.busy = 0;
611 channel->status.ready = 1;
612 channel->status.write_fault = 0;
613 channel->status.seek_complete = 1;
614 channel->status.corrected = 0;
615 channel->status.error = 0;
618 memcpy(dst, drive->data_buf + drive->transfer_index, length);
619 drive->transfer_index += length;
621 if (drive->transfer_index >= drive->transfer_length) {
622 channel->status.data_req = 0;
629 static int ide_read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
630 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
631 struct ide_channel * channel = get_selected_channel(ide, port);
632 struct ide_drive * drive = get_selected_drive(channel);
634 // PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length);
636 if ((channel->cmd_reg == 0xec) ||
637 (channel->cmd_reg == 0xa1)) {
638 return read_drive_id((uint8_t *)dst, length, dev, channel);
641 if (drive->drive_type == IDE_CDROM) {
642 if (read_cd_data((uint8_t *)dst, length, dev, channel) == -1) {
643 PrintError("IDE: Could not read CD Data\n");
646 } else if (drive->drive_type == IDE_DISK) {
647 if (read_hd_data((uint8_t *)dst, length, dev, channel) == -1) {
648 PrintError("IDE: Could not read HD Data\n");
652 memset((uint8_t *)dst, 0, length);
658 static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
659 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
660 struct ide_channel * channel = get_selected_channel(ide, port);
661 struct ide_drive * drive = get_selected_drive(channel);
664 PrintError("Invalid Write length on IDE port %x\n", port);
668 PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
672 // reset and interrupt enable
674 case SEC_CTRL_PORT: {
675 struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
677 // only reset channel on a 0->1 reset bit transition
678 if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
679 channel_reset(channel);
680 } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
681 channel_reset_complete(channel);
684 channel->ctrl_reg.val = tmp_ctrl->val;
687 case PRI_FEATURES_PORT:
688 case SEC_FEATURES_PORT:
689 channel->features.val = *(uint8_t *)src;
692 case PRI_SECT_CNT_PORT:
693 case SEC_SECT_CNT_PORT:
694 drive->sector_count = *(uint8_t *)src;
697 case PRI_SECT_NUM_PORT:
698 case SEC_SECT_NUM_PORT:
699 drive->sector_num = *(uint8_t *)src;
701 case PRI_CYL_LOW_PORT:
702 case SEC_CYL_LOW_PORT:
703 drive->cylinder_low = *(uint8_t *)src;
706 case PRI_CYL_HIGH_PORT:
707 case SEC_CYL_HIGH_PORT:
708 drive->cylinder_high = *(uint8_t *)src;
711 case PRI_DRV_SEL_PORT:
712 case SEC_DRV_SEL_PORT: {
713 channel->drive_head.val = *(uint8_t *)src;
715 // make sure the reserved bits are ok..
716 // JRL TODO: check with new ramdisk to make sure this is right...
717 channel->drive_head.val |= 0xa0;
719 drive = get_selected_drive(channel);
721 // Selecting a non-present device is a no-no
722 if (drive->drive_type == IDE_NONE) {
723 PrintDebug("Attempting to select a non-present drive\n");
724 channel->error_reg.abort = 1;
725 channel->status.error = 1;
731 PrintError("IDE: Write to unknown Port %x\n", port);
738 static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
739 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
740 struct ide_channel * channel = get_selected_channel(ide, port);
741 struct ide_drive * drive = get_selected_drive(channel);
744 PrintError("Invalid Read length on IDE port %x\n", port);
748 PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port));
751 if ((port == PRI_ADDR_REG_PORT) ||
752 (port == SEC_ADDR_REG_PORT)) {
753 // unused, return 0xff
754 *(uint8_t *)dst = 0xff;
759 // if no drive is present just return 0 + reserved bits
760 if (drive->drive_type == IDE_NONE) {
761 if ((port == PRI_DRV_SEL_PORT) ||
762 (port == SEC_DRV_SEL_PORT)) {
763 *(uint8_t *)dst = 0xa0;
773 // This is really the error register.
774 case PRI_FEATURES_PORT:
775 case SEC_FEATURES_PORT:
776 *(uint8_t *)dst = channel->error_reg.val;
779 case PRI_SECT_CNT_PORT:
780 case SEC_SECT_CNT_PORT:
781 *(uint8_t *)dst = drive->sector_count;
784 case PRI_SECT_NUM_PORT:
785 case SEC_SECT_NUM_PORT:
786 *(uint8_t *)dst = drive->sector_num;
789 case PRI_CYL_LOW_PORT:
790 case SEC_CYL_LOW_PORT:
791 *(uint8_t *)dst = drive->cylinder_low;
795 case PRI_CYL_HIGH_PORT:
796 case SEC_CYL_HIGH_PORT:
797 *(uint8_t *)dst = drive->cylinder_high;
800 case PRI_DRV_SEL_PORT:
801 case SEC_DRV_SEL_PORT: // hard disk drive and head register 0x1f6
802 *(uint8_t *)dst = channel->drive_head.val;
809 // Something about lowering interrupts here....
810 *(uint8_t *)dst = channel->status.val;
814 PrintError("Invalid Port: %x\n", port);
818 PrintDebug("\tVal=%x\n", *(uint8_t *)dst);
825 static void init_drive(struct ide_drive * drive) {
827 drive->sector_count = 0x01;
828 drive->sector_num = 0x01;
829 drive->cylinder = 0x0000;
831 drive->drive_type = IDE_NONE;
833 memset(drive->model, 0, sizeof(drive->model));
835 drive->transfer_index = 0;
836 drive->transfer_length = 0;
837 memset(drive->data_buf, 0, sizeof(drive->data_buf));
839 drive->dma_cmd.val = 0;
840 drive->dma_status.val = 0;
841 drive->dma_prd_addr = 0;
843 drive->private_data = NULL;
844 drive->cd_ops = NULL;
847 static void init_channel(struct ide_channel * channel) {
850 channel->error_reg.val = 0x01;
851 channel->drive_head.val = 0x00;
852 channel->status.val = 0x00;
853 channel->cmd_reg = 0x00;
854 channel->ctrl_reg.val = 0x08;
857 for (i = 0; i < 2; i++) {
858 init_drive(&(channel->drives[i]));
864 static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) {
865 PrintError("IDE does not handle PCI config updates\n");
870 static int pci_bar_update(struct pci_device * pci_dev, uint_t bar) {
871 PrintError("IDE does not support bar updates\n");
876 static int init_ide_state(struct vm_device * dev) {
877 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
878 struct v3_pci_bar bars[6];
879 struct pci_device * pci_dev = NULL;
882 for (i = 0; i < 2; i++) {
883 init_channel(&(ide->channels[i]));
885 // JRL: this is a terrible hack...
886 ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
888 for (j = 0; j < 6; j++) {
889 bars[j].type = PCI_BAR_NONE;
890 bars[j].mem_hook = 0;
891 bars[j].num_pages = 0;
892 bars[j].bar_update = NULL;
896 bars[4].type = PCI_BAR_IO;
897 bars[4].bar_update = pci_bar_update;
899 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "V3_IDE", -1, bars,
900 NULL, NULL, NULL, dev);
902 if (pci_dev == NULL) {
903 PrintError("Failed to register IDE BUS %d with PCI\n", i);
907 ide->channels[i].pci_dev = pci_dev;
909 pci_dev->config_header.vendor_id = 0x1095;
910 pci_dev->config_header.device_id = 0x0646;
911 pci_dev->config_header.revision = 0x8f07;
912 pci_dev->config_header.subclass = 0x01;
913 pci_dev->config_header.class = 0x01;
918 /* Register PIIX3 Busmaster PCI device */
919 for (j = 0; j < 6; j++) {
920 bars[j].type = PCI_BAR_NONE;
921 bars[j].mem_hook = 0;
922 bars[j].num_pages = 0;
923 bars[j].bar_update = NULL;
926 pci_dev = v3_pci_register_device(ide->pci, PCI_STD_DEVICE, 0, "PIIX3 IDE", -1, bars,
927 NULL, NULL, NULL, dev);
930 ide->busmaster_pci = pci_dev;
932 pci_dev->config_header.vendor_id = 0x8086;
933 pci_dev->config_header.device_id = 0x7010;
934 pci_dev->config_header.revision = 0x80;
935 pci_dev->config_header.subclass = 0x01;
936 pci_dev->config_header.class = 0x01;
944 static int init_ide(struct vm_device * dev) {
945 //struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
947 PrintDebug("IDE: Initializing IDE\n");
949 if (init_ide_state(dev) == -1) {
950 PrintError("Failed to initialize IDE state\n");
957 v3_dev_hook_io(dev, PRI_DATA_PORT,
958 &ide_read_data_port, &write_data_port);
959 v3_dev_hook_io(dev, PRI_FEATURES_PORT,
960 &read_port_std, &write_port_std);
961 v3_dev_hook_io(dev, PRI_SECT_CNT_PORT,
962 &read_port_std, &write_port_std);
963 v3_dev_hook_io(dev, PRI_SECT_NUM_PORT,
964 &read_port_std, &write_port_std);
965 v3_dev_hook_io(dev, PRI_CYL_LOW_PORT,
966 &read_port_std, &write_port_std);
967 v3_dev_hook_io(dev, PRI_CYL_HIGH_PORT,
968 &read_port_std, &write_port_std);
969 v3_dev_hook_io(dev, PRI_DRV_SEL_PORT,
970 &read_port_std, &write_port_std);
971 v3_dev_hook_io(dev, PRI_CMD_PORT,
972 &read_port_std, &write_cmd_port);
974 v3_dev_hook_io(dev, SEC_DATA_PORT,
975 &ide_read_data_port, &write_data_port);
976 v3_dev_hook_io(dev, SEC_FEATURES_PORT,
977 &read_port_std, &write_port_std);
978 v3_dev_hook_io(dev, SEC_SECT_CNT_PORT,
979 &read_port_std, &write_port_std);
980 v3_dev_hook_io(dev, SEC_SECT_NUM_PORT,
981 &read_port_std, &write_port_std);
982 v3_dev_hook_io(dev, SEC_CYL_LOW_PORT,
983 &read_port_std, &write_port_std);
984 v3_dev_hook_io(dev, SEC_CYL_HIGH_PORT,
985 &read_port_std, &write_port_std);
986 v3_dev_hook_io(dev, SEC_DRV_SEL_PORT,
987 &read_port_std, &write_port_std);
988 v3_dev_hook_io(dev, SEC_CMD_PORT,
989 &read_port_std, &write_cmd_port);
992 v3_dev_hook_io(dev, PRI_CTRL_PORT,
993 &read_port_std, &write_port_std);
995 v3_dev_hook_io(dev, SEC_CTRL_PORT,
996 &read_port_std, &write_port_std);
999 v3_dev_hook_io(dev, SEC_ADDR_REG_PORT,
1000 &read_port_std, &write_port_std);
1002 v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
1003 &read_port_std, &write_port_std);
1007 v3_dev_hook_io(dev, PRI_DMA_CMD_PORT,
1008 &read_dma_port, &write_dma_port);
1009 v3_dev_hook_io(dev, PRI_DMA_STATUS_PORT,
1010 &read_dma_port, &write_dma_port);
1011 v3_dev_hook_io(dev, PRI_DMA_PRD_PORT0,
1012 &read_dma_port, &write_dma_port);
1013 v3_dev_hook_io(dev, PRI_DMA_PRD_PORT0,
1014 &read_dma_port, &write_dma_port);
1015 v3_dev_hook_io(dev, PRI_DMA_PRD_PORT0,
1016 &read_dma_port, &write_dma_port);
1017 v3_dev_hook_io(dev, PRI_DMA_PRD_PORT0,
1018 &read_dma_port, &write_dma_port);
1021 v3_dev_hook_io(dev, SEC_DMA_CMD_PORT,
1022 &read_dma_port, &write_dma_port);
1023 v3_dev_hook_io(dev, SEC_DMA_STATUS_PORT,
1024 &read_dma_port, &write_dma_port);
1025 v3_dev_hook_io(dev, SEC_DMA_PRD_PORT0,
1026 &read_dma_port, &write_dma_port);
1027 v3_dev_hook_io(dev, SEC_DMA_PRD_PORT0,
1028 &read_dma_port, &write_dma_port);
1029 v3_dev_hook_io(dev, SEC_DMA_PRD_PORT0,
1030 &read_dma_port, &write_dma_port);
1031 v3_dev_hook_io(dev, SEC_DMA_PRD_PORT0,
1032 &read_dma_port, &write_dma_port);
1038 static int deinit_ide(struct vm_device * dev) {
1039 // unhook io ports....
1040 // deregister from PCI?
1045 static struct vm_device_ops dev_ops = {
1047 .deinit = deinit_ide,
1054 struct vm_device * v3_create_ide(struct vm_device * pci) {
1055 struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
1056 struct vm_device * device = v3_create_device("IDE", &dev_ops, ide);
1060 PrintDebug("IDE: Creating IDE bus x 2\n");
1069 int v3_ide_register_cdrom(struct vm_device * ide_dev,
1073 struct v3_ide_cd_ops * ops,
1074 void * private_data) {
1076 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1077 struct ide_channel * channel = NULL;
1078 struct ide_drive * drive = NULL;
1080 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1081 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1083 channel = &(ide->channels[bus_num]);
1084 drive = &(channel->drives[drive_num]);
1086 if (drive->drive_type != IDE_NONE) {
1087 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1091 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1093 while (strlen((char *)(drive->model)) < 40) {
1094 strcat((char*)(drive->model), " ");
1098 drive->drive_type = IDE_CDROM;
1100 drive->cd_ops = ops;
1102 drive->private_data = private_data;
1108 int v3_ide_register_harddisk(struct vm_device * ide_dev,
1112 struct v3_ide_hd_ops * ops,
1113 void * private_data) {
1115 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1116 struct ide_channel * channel = NULL;
1117 struct ide_drive * drive = NULL;
1119 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1120 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1122 channel = &(ide->channels[bus_num]);
1123 drive = &(channel->drives[drive_num]);
1125 if (drive->drive_type != IDE_NONE) {
1126 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1130 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1132 drive->drive_type = IDE_DISK;
1134 drive->hd_ops = ops;
1136 drive->private_data = private_data;