2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm.h>
21 #include <palacios/vm_guest_mem.h>
22 #include <devices/ide.h>
23 #include <devices/pci.h>
24 #include <devices/southbridge.h>
25 #include "ide-types.h"
26 #include "atapi-types.h"
30 #define PrintDebug(fmt, args...)
33 #define PRI_DEFAULT_IRQ 14
34 #define SEC_DEFAULT_IRQ 15
37 #define PRI_DATA_PORT 0x1f0
38 #define PRI_FEATURES_PORT 0x1f1
39 #define PRI_SECT_CNT_PORT 0x1f2
40 #define PRI_SECT_NUM_PORT 0x1f3
41 #define PRI_CYL_LOW_PORT 0x1f4
42 #define PRI_CYL_HIGH_PORT 0x1f5
43 #define PRI_DRV_SEL_PORT 0x1f6
44 #define PRI_CMD_PORT 0x1f7
45 #define PRI_CTRL_PORT 0x3f6
46 #define PRI_ADDR_REG_PORT 0x3f7
48 #define SEC_DATA_PORT 0x170
49 #define SEC_FEATURES_PORT 0x171
50 #define SEC_SECT_CNT_PORT 0x172
51 #define SEC_SECT_NUM_PORT 0x173
52 #define SEC_CYL_LOW_PORT 0x174
53 #define SEC_CYL_HIGH_PORT 0x175
54 #define SEC_DRV_SEL_PORT 0x176
55 #define SEC_CMD_PORT 0x177
56 #define SEC_CTRL_PORT 0x376
57 #define SEC_ADDR_REG_PORT 0x377
60 #define PRI_DEFAULT_DMA_PORT 0xc000
61 #define SEC_DEFAULT_DMA_PORT 0xc008
63 #define DATA_BUFFER_SIZE 2048
65 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
66 "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD",
67 "PRI_CTRL", "PRI_ADDR_REG"};
70 static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM",
71 "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD",
72 "SEC_CTRL", "SEC_ADDR_REG"};
74 static const char * ide_dma_port_strs[] = {"DMA_CMD", NULL, "DMA_STATUS", NULL,
75 "DMA_PRD0", "DMA_PRD1", "DMA_PRD2", "DMA_PRD3"};
79 static inline const char * io_port_to_str(uint16_t port) {
80 if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) {
81 return ide_pri_port_strs[port - PRI_DATA_PORT];
82 } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) {
83 return ide_sec_port_strs[port - SEC_DATA_PORT];
84 } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) {
85 return ide_pri_port_strs[port - PRI_CTRL_PORT + 8];
86 } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) {
87 return ide_sec_port_strs[port - SEC_CTRL_PORT + 8];
93 static inline const char * dma_port_to_str(uint16_t port) {
94 return ide_dma_port_strs[port & 0x7];
98 static const char * ide_dev_type_strs[] = {"NONE", "HARDDISK", "CDROM" };
101 static inline const char * device_type_to_str(v3_ide_dev_type_t type) {
106 return ide_dev_type_strs[type];
111 struct ide_cd_state {
112 struct atapi_sense_data sense;
115 struct atapi_error_recovery err_recovery;
118 struct ide_hd_state {
121 /* this is the multiple sector transfer size as configured for read/write multiple sectors*/
122 uint_t mult_sector_num;
124 /* This is the current op sector size:
125 * for multiple sector ops this equals mult_sector_num
126 * for standard ops this equals 1
128 uint_t cur_sector_num;
134 v3_ide_dev_type_t drive_type;
137 struct v3_ide_cd_ops * cd_ops;
138 struct v3_ide_hd_ops * hd_ops;
143 struct ide_cd_state cd_state;
144 struct ide_hd_state hd_state;
149 // Where we are in the data transfer
150 uint_t transfer_index;
152 // the length of a transfer
153 // calculated for easy access
154 uint_t transfer_length;
156 uint64_t current_lba;
158 // We have a local data buffer that we use for IO port accesses
159 uint8_t data_buf[DATA_BUFFER_SIZE];
162 uint32_t num_cylinders;
164 uint32_t num_sectors;
169 uint8_t sector_count; // 0x1f2,0x172
170 struct atapi_irq_flags irq_flags;
171 } __attribute__((packed));
174 uint8_t sector_num; // 0x1f3,0x173
176 } __attribute__((packed));
183 uint8_t cylinder_low; // 0x1f4,0x174
184 uint8_t cylinder_high; // 0x1f5,0x175
185 } __attribute__((packed));
190 } __attribute__((packed));
193 // The transfer length requested by the CPU
195 } __attribute__((packed));
202 struct ide_drive drives[2];
205 struct ide_error_reg error_reg; // [read] 0x1f1,0x171
207 struct ide_features_reg features;
209 struct ide_drive_head_reg drive_head; // 0x1f6,0x176
211 struct ide_status_reg status; // [read] 0x1f7,0x177
212 uint8_t cmd_reg; // [write] 0x1f7,0x177
214 int irq; // this is temporary until we add PCI support
217 struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
219 struct ide_dma_cmd_reg dma_cmd;
220 struct ide_dma_status_reg dma_status;
221 uint32_t dma_prd_addr;
222 uint_t dma_tbl_index;
227 struct ide_internal {
228 struct ide_channel channels[2];
230 struct v3_southbridge * southbridge;
231 struct vm_device * pci_bus;
233 struct pci_device * ide_pci;
240 /* Utility functions */
242 static inline uint16_t be_to_le_16(const uint16_t val) {
243 uint8_t * buf = (uint8_t *)&val;
244 return (buf[0] << 8) | (buf[1]) ;
247 static inline uint16_t le_to_be_16(const uint16_t val) {
248 return be_to_le_16(val);
252 static inline uint32_t be_to_le_32(const uint32_t val) {
253 uint8_t * buf = (uint8_t *)&val;
254 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
257 static inline uint32_t le_to_be_32(const uint32_t val) {
258 return be_to_le_32(val);
262 static inline int get_channel_index(ushort_t port) {
263 if (((port & 0xfff8) == 0x1f0) ||
264 ((port & 0xfffe) == 0x3f6) ||
265 ((port & 0xfff8) == 0xc000)) {
267 } else if (((port & 0xfff8) == 0x170) ||
268 ((port & 0xfffe) == 0x376) ||
269 ((port & 0xfff8) == 0xc008)) {
276 static inline struct ide_channel * get_selected_channel(struct ide_internal * ide, ushort_t port) {
277 int channel_idx = get_channel_index(port);
278 return &(ide->channels[channel_idx]);
281 static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
282 return &(channel->drives[channel->drive_head.drive_sel]);
286 static inline int is_lba_enabled(struct ide_channel * channel) {
287 return channel->drive_head.lba_mode;
292 static void ide_raise_irq(struct vm_device * dev, struct ide_channel * channel) {
293 if (channel->ctrl_reg.irq_disable == 0) {
294 PrintDebug("Raising IDE Interrupt %d\n", channel->irq);
295 channel->dma_status.int_gen = 1;
296 v3_raise_irq(dev->vm, channel->irq);
301 static void drive_reset(struct ide_drive * drive) {
302 drive->sector_count = 0x01;
303 drive->sector_num = 0x01;
305 PrintDebug("Resetting drive %s\n", drive->model);
307 if (drive->drive_type == IDE_CDROM) {
308 drive->cylinder = 0xeb14;
310 drive->cylinder = 0x0000;
311 //drive->hd_state.accessed = 0;
315 memset(drive->data_buf, 0, sizeof(drive->data_buf));
316 drive->transfer_index = 0;
318 // Send the reset signal to the connected device callbacks
319 // channel->drives[0].reset();
320 // channel->drives[1].reset();
323 static void channel_reset(struct ide_channel * channel) {
325 // set busy and seek complete flags
326 channel->status.val = 0x90;
329 channel->error_reg.val = 0x01;
332 channel->cmd_reg = 0x00;
334 channel->ctrl_reg.irq_disable = 0;
337 static void channel_reset_complete(struct ide_channel * channel) {
338 channel->status.busy = 0;
339 channel->status.ready = 1;
341 channel->drive_head.head_num = 0;
343 drive_reset(&(channel->drives[0]));
344 drive_reset(&(channel->drives[1]));
348 static void ide_abort_command(struct vm_device * dev, struct ide_channel * channel) {
349 channel->status.val = 0x41; // Error + ready
350 channel->error_reg.val = 0x04; // No idea...
352 ide_raise_irq(dev, channel);
356 static int dma_read(struct vm_device * dev, struct ide_channel * channel);
357 static int dma_write(struct vm_device * dev, struct ide_channel * channel);
360 /* ATAPI functions */
368 static void print_prd_table(struct vm_device * dev, struct ide_channel * channel) {
369 struct ide_dma_prd prd_entry;
372 PrintDebug("Dumping PRD table\n");
375 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * index);
378 ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
380 if (ret != sizeof(struct ide_dma_prd)) {
381 PrintError("Could not read PRD\n");
385 PrintDebug("\tPRD Addr: %x, PRD Len: %d, EOT: %d\n",
386 prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
388 if (prd_entry.end_of_table) {
400 static int dma_read(struct vm_device * dev, struct ide_channel * channel) {
401 struct ide_drive * drive = get_selected_drive(channel);
402 // This is at top level scope to do the EOT test at the end
403 struct ide_dma_prd prd_entry;
404 uint_t bytes_left = drive->transfer_length;
406 // Read in the data buffer....
407 // Read a sector/block at a time until the prd entry is full.
410 print_prd_table(dev, channel);
413 PrintDebug("DMA read for %d bytes\n", bytes_left);
415 // Loop through the disk data
416 while (bytes_left > 0) {
417 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
418 uint_t prd_bytes_left = 0;
419 uint_t prd_offset = 0;
422 PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
424 ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
426 if (ret != sizeof(struct ide_dma_prd)) {
427 PrintError("Could not read PRD\n");
431 PrintDebug("PRD Addr: %x, PRD Len: %d, EOT: %d\n",
432 prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
434 // loop through the PRD data....
436 prd_bytes_left = prd_entry.size;
439 while (prd_bytes_left > 0) {
440 uint_t bytes_to_write = 0;
442 if (drive->drive_type == IDE_DISK) {
443 bytes_to_write = (prd_bytes_left > IDE_SECTOR_SIZE) ? IDE_SECTOR_SIZE : prd_bytes_left;
446 if (ata_read(dev, channel, drive->data_buf, 1) == -1) {
447 PrintError("Failed to read next disk sector\n");
450 } else if (drive->drive_type == IDE_CDROM) {
451 if (atapi_cmd_is_data_op(drive->cd_state.atapi_cmd)) {
452 bytes_to_write = (prd_bytes_left > ATAPI_BLOCK_SIZE) ? ATAPI_BLOCK_SIZE : prd_bytes_left;
454 if (atapi_read_chunk(dev, channel) == -1) {
455 PrintError("Failed to read next disk sector\n");
459 PrintDebug("DMA of command packet\n");
460 PrintError("How does this work???\n");
462 bytes_to_write = (prd_bytes_left > bytes_left) ? bytes_left : prd_bytes_left;
463 prd_bytes_left = bytes_to_write;
467 PrintDebug("Writing DMA data to guest Memory ptr=%p, len=%d\n",
468 (void *)(addr_t)(prd_entry.base_addr + prd_offset), bytes_to_write);
470 drive->current_lba++;
472 ret = write_guest_pa_memory(dev->vm, prd_entry.base_addr + prd_offset, bytes_to_write, drive->data_buf);
474 if (ret != bytes_to_write) {
475 PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
479 PrintDebug("\t DMA ret=%d, (prd_bytes_left=%d) (bytes_left=%d)\n", ret, prd_bytes_left, bytes_left);
481 drive->transfer_index += ret;
482 prd_bytes_left -= ret;
487 channel->dma_tbl_index++;
489 if (drive->drive_type == IDE_DISK) {
490 if (drive->transfer_index % IDE_SECTOR_SIZE) {
491 PrintError("We currently don't handle sectors that span PRD descriptors\n");
494 } else if (drive->drive_type == IDE_CDROM) {
495 if (atapi_cmd_is_data_op(drive->cd_state.atapi_cmd)) {
496 if (drive->transfer_index % ATAPI_BLOCK_SIZE) {
497 PrintError("We currently don't handle ATAPI BLOCKS that span PRD descriptors\n");
498 PrintError("transfer_index=%d, transfer_length=%d\n",
499 drive->transfer_index, drive->transfer_length);
506 if ((prd_entry.end_of_table == 1) && (bytes_left > 0)) {
507 PrintError("DMA table not large enough for data transfer...\n");
513 drive->irq_flags.io_dir = 1;
514 drive->irq_flags.c_d = 1;
515 drive->irq_flags.rel = 0;
519 // Update to the next PRD entry
523 if (prd_entry.end_of_table) {
524 channel->status.busy = 0;
525 channel->status.ready = 1;
526 channel->status.data_req = 0;
527 channel->status.error = 0;
528 channel->status.seek_complete = 1;
530 channel->dma_status.active = 0;
531 channel->dma_status.err = 0;
534 ide_raise_irq(dev, channel);
540 static int dma_write(struct vm_device * dev, struct ide_channel * channel) {
541 struct ide_drive * drive = get_selected_drive(channel);
542 // This is at top level scope to do the EOT test at the end
543 struct ide_dma_prd prd_entry;
544 uint_t bytes_left = drive->transfer_length;
547 PrintDebug("DMA write from %d bytes\n", bytes_left);
549 // Loop through disk data
550 while (bytes_left > 0) {
551 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
552 uint_t prd_bytes_left = 0;
553 uint_t prd_offset = 0;
556 PrintDebug("PRD Table address = %x\n", channel->dma_prd_addr);
558 ret = read_guest_pa_memory(dev->vm, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
560 if (ret != sizeof(struct ide_dma_prd)) {
561 PrintError("Could not read PRD\n");
565 PrintDebug("PRD Addr: %x, PRD Len: %d, EOT: %d\n",
566 prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
568 prd_bytes_left = prd_entry.size;
570 while (prd_bytes_left > 0) {
571 uint_t bytes_to_write = 0;
574 bytes_to_write = (prd_bytes_left > IDE_SECTOR_SIZE) ? IDE_SECTOR_SIZE : prd_bytes_left;
577 ret = read_guest_pa_memory(dev->vm, prd_entry.base_addr + prd_offset, bytes_to_write, drive->data_buf);
579 if (ret != bytes_to_write) {
580 PrintError("Faild to copy data from guest memory... (ret=%d)\n", ret);
584 PrintDebug("\t DMA ret=%d (prd_bytes_left=%d) (bytes_left=%d)\n", ret, prd_bytes_left, bytes_left);
587 if (ata_write(dev, channel, drive->data_buf, 1) == -1) {
588 PrintError("Failed to write data to disk\n");
592 drive->current_lba++;
594 drive->transfer_index += ret;
595 prd_bytes_left -= ret;
600 channel->dma_tbl_index++;
602 if (drive->transfer_index % IDE_SECTOR_SIZE) {
603 PrintError("We currently don't handle sectors that span PRD descriptors\n");
607 if ((prd_entry.end_of_table == 1) && (bytes_left > 0)) {
608 PrintError("DMA table not large enough for data transfer...\n");
613 if (prd_entry.end_of_table) {
614 channel->status.busy = 0;
615 channel->status.ready = 1;
616 channel->status.data_req = 0;
617 channel->status.error = 0;
618 channel->status.seek_complete = 1;
620 channel->dma_status.active = 0;
621 channel->dma_status.err = 0;
624 ide_raise_irq(dev, channel);
631 #define DMA_CMD_PORT 0x00
632 #define DMA_STATUS_PORT 0x02
633 #define DMA_PRD_PORT0 0x04
634 #define DMA_PRD_PORT1 0x05
635 #define DMA_PRD_PORT2 0x06
636 #define DMA_PRD_PORT3 0x07
638 #define DMA_CHANNEL_FLAG 0x08
640 static int write_dma_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
641 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
642 uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
643 uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
644 struct ide_channel * channel = &(ide->channels[channel_flag]);
646 PrintDebug("IDE: Writing DMA Port %x (%s) (val=%x) (len=%d) (channel=%d)\n",
647 port, dma_port_to_str(port_offset), *(uint32_t *)src, length, channel_flag);
649 switch (port_offset) {
651 channel->dma_cmd.val = *(uint8_t *)src;
653 if (channel->dma_cmd.start == 0) {
654 channel->dma_tbl_index = 0;
656 channel->dma_status.active = 1;
658 if (channel->dma_cmd.read == 1) {
660 if (dma_read(dev, channel) == -1) {
661 PrintError("Failed DMA Read\n");
666 if (dma_write(dev, channel) == -1) {
667 PrintError("Failed DMA Write\n");
672 channel->dma_cmd.val &= 0x09;
677 case DMA_STATUS_PORT: {
678 uint8_t val = *(uint8_t *)src;
681 PrintError("Invalid read length for DMA status port\n");
686 channel->dma_status.val = ((val & 0x60) |
687 (channel->dma_status.val & 0x01) |
688 (channel->dma_status.val & ~val & 0x06));
695 case DMA_PRD_PORT3: {
696 uint_t addr_index = port_offset & 0x3;
697 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
700 if (addr_index + length > 4) {
701 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
705 for (i = 0; i < length; i++) {
706 addr_buf[addr_index + i] = *((uint8_t *)src + i);
709 PrintDebug("Writing PRD Port %x (val=%x)\n", port_offset, channel->dma_prd_addr);
714 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
722 static int read_dma_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
723 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
724 uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
725 uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
726 struct ide_channel * channel = &(ide->channels[channel_flag]);
728 PrintDebug("Reading DMA port %d (%x) (channel=%d)\n", port, port, channel_flag);
730 switch (port_offset) {
732 *(uint8_t *)dst = channel->dma_cmd.val;
735 case DMA_STATUS_PORT:
737 PrintError("Invalid read length for DMA status port\n");
741 *(uint8_t *)dst = channel->dma_status.val;
747 case DMA_PRD_PORT3: {
748 uint_t addr_index = port_offset & 0x3;
749 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
752 if (addr_index + length > 4) {
753 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
757 for (i = 0; i < length; i++) {
758 *((uint8_t *)dst + i) = addr_buf[addr_index + i];
764 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
768 PrintDebug("\tval=%x (len=%d)\n", *(uint32_t *)dst, length);
775 static int write_cmd_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
776 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
777 struct ide_channel * channel = get_selected_channel(ide, port);
778 struct ide_drive * drive = get_selected_drive(channel);
781 PrintError("Invalid Write Length on IDE command Port %x\n", port);
785 PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
787 channel->cmd_reg = *(uint8_t *)src;
789 switch (channel->cmd_reg) {
791 case 0xa1: // ATAPI Identify Device Packet
792 if (drive->drive_type != IDE_CDROM) {
795 // JRL: Should we abort here?
796 ide_abort_command(dev, channel);
799 atapi_identify_device(drive);
801 channel->error_reg.val = 0;
802 channel->status.val = 0x58; // ready, data_req, seek_complete
804 ide_raise_irq(dev, channel);
807 case 0xec: // Identify Device
808 if (drive->drive_type != IDE_DISK) {
811 // JRL: Should we abort here?
812 ide_abort_command(dev, channel);
814 ata_identify_device(drive);
816 channel->error_reg.val = 0;
817 channel->status.val = 0x58;
819 ide_raise_irq(dev, channel);
823 case 0xa0: // ATAPI Command Packet
824 if (drive->drive_type != IDE_CDROM) {
825 ide_abort_command(dev, channel);
828 drive->sector_count = 1;
830 channel->status.busy = 0;
831 channel->status.write_fault = 0;
832 channel->status.data_req = 1;
833 channel->status.error = 0;
835 // reset the data buffer...
836 drive->transfer_length = ATAPI_PACKET_SIZE;
837 drive->transfer_index = 0;
841 case 0x20: // Read Sectors with Retry
842 case 0x21: // Read Sectors without Retry
843 drive->hd_state.cur_sector_num = 1;
845 if (ata_read_sectors(dev, channel) == -1) {
846 PrintError("Error reading sectors\n");
851 case 0x24: // Read Sectors Extended
852 drive->hd_state.cur_sector_num = 1;
854 if (ata_read_sectors_ext(dev, channel) == -1) {
855 PrintError("Error reading extended sectors\n");
860 case 0xc8: // Read DMA with retry
861 case 0xc9: { // Read DMA
862 uint32_t sect_cnt = (drive->sector_count == 0) ? 256 : drive->sector_count;
864 if (ata_get_lba(dev, channel, &(drive->current_lba)) == -1) {
865 ide_abort_command(dev, channel);
869 drive->hd_state.cur_sector_num = 1;
871 drive->transfer_length = sect_cnt * IDE_SECTOR_SIZE;
872 drive->transfer_index = 0;
874 if (channel->dma_status.active == 1) {
876 if (dma_read(dev, channel) == -1) {
877 PrintError("Failed DMA Read\n");
884 case 0xca: { // Write DMA
885 uint32_t sect_cnt = (drive->sector_count == 0) ? 256 : drive->sector_count;
887 if (ata_get_lba(dev, channel, &(drive->current_lba)) == -1) {
888 ide_abort_command(dev, channel);
892 drive->hd_state.cur_sector_num = 1;
894 drive->transfer_length = sect_cnt * IDE_SECTOR_SIZE;
895 drive->transfer_index = 0;
897 if (channel->dma_status.active == 1) {
899 if (dma_write(dev, channel) == -1) {
900 PrintError("Failed DMA Write\n");
906 case 0xe0: // Standby Now 1
907 case 0xe1: // Set Idle Immediate
908 case 0xe2: // Standby
909 case 0xe3: // Set Idle 1
910 case 0xe6: // Sleep Now 1
911 case 0x94: // Standby Now 2
912 case 0x95: // Idle Immediate (CFA)
913 case 0x96: // Standby 2
914 case 0x97: // Set idle 2
915 case 0x99: // Sleep Now 2
916 channel->status.val = 0;
917 channel->status.ready = 1;
918 ide_raise_irq(dev, channel);
921 case 0xef: // Set Features
922 // Prior to this the features register has been written to.
923 // This command tells the drive to check if the new value is supported (the value is drive specific)
924 // Common is that bit0=DMA enable
925 // If valid the drive raises an interrupt, if not it aborts.
927 // Do some checking here...
929 channel->status.busy = 0;
930 channel->status.write_fault = 0;
931 channel->status.error = 0;
932 channel->status.ready = 1;
933 channel->status.seek_complete = 1;
935 ide_raise_irq(dev, channel);
938 case 0x91: // Initialize Drive Parameters
939 case 0x10: // recalibrate?
940 channel->status.error = 0;
941 channel->status.ready = 1;
942 channel->status.seek_complete = 1;
943 ide_raise_irq(dev, channel);
945 case 0xc6: { // Set multiple mode (IDE Block mode)
946 // This makes the drive transfer multiple sectors before generating an interrupt
947 uint32_t tmp_sect_num = drive->sector_num; // GCC SUCKS
949 if (tmp_sect_num > MAX_MULT_SECTORS) {
950 ide_abort_command(dev, channel);
954 if (drive->sector_count == 0) {
955 drive->hd_state.mult_sector_num= 1;
957 drive->hd_state.mult_sector_num = drive->sector_count;
960 channel->status.ready = 1;
961 channel->status.error = 0;
963 ide_raise_irq(dev, channel);
967 case 0xc4: // read multiple sectors
968 drive->hd_state.cur_sector_num = drive->hd_state.mult_sector_num;
970 PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
978 static int write_data_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
979 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
980 struct ide_channel * channel = get_selected_channel(ide, port);
981 struct ide_drive * drive = get_selected_drive(channel);
983 // PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n",
984 // port, *(uint32_t *)src, length);
986 memcpy(drive->data_buf + drive->transfer_index, src, length);
987 drive->transfer_index += length;
989 // Transfer is complete, dispatch the command
990 if (drive->transfer_index >= drive->transfer_length) {
991 switch (channel->cmd_reg) {
992 case 0x30: // Write Sectors
993 PrintError("Writing Data not yet implemented\n");
996 case 0xa0: // ATAPI packet command
997 if (atapi_handle_packet(dev, channel) == -1) {
998 PrintError("Error handling ATAPI packet\n");
1003 PrintError("Unhandld IDE Command %x\n", channel->cmd_reg);
1012 static int read_hd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
1013 struct ide_drive * drive = get_selected_drive(channel);
1014 int data_offset = drive->transfer_index % IDE_SECTOR_SIZE;
1018 if (drive->transfer_index >= drive->transfer_length) {
1019 PrintError("Buffer overrun... (xfer_len=%d) (cur_idx=%x) (post_idx=%d)\n",
1020 drive->transfer_length, drive->transfer_index,
1021 drive->transfer_index + length);
1026 if ((data_offset == 0) && (drive->transfer_index > 0)) {
1027 drive->current_lba++;
1029 if (ata_read(dev, channel, drive->data_buf, 1) == -1) {
1030 PrintError("Could not read next disk sector\n");
1036 PrintDebug("Reading HD Data (Val=%x), (len=%d) (offset=%d)\n",
1037 *(uint32_t *)(drive->data_buf + data_offset),
1038 length, data_offset);
1040 memcpy(dst, drive->data_buf + data_offset, length);
1042 drive->transfer_index += length;
1045 /* This is the trigger for interrupt injection.
1046 * For read single sector commands we interrupt after every sector
1047 * For multi sector reads we interrupt only at end of the cluster size (mult_sector_num)
1048 * cur_sector_num is configured depending on the operation we are currently running
1049 * We also trigger an interrupt if this is the last byte to transfer, regardless of sector count
1051 if (((drive->transfer_index % (IDE_SECTOR_SIZE * drive->hd_state.cur_sector_num)) == 0) ||
1052 (drive->transfer_index == drive->transfer_length)) {
1053 if (drive->transfer_index < drive->transfer_length) {
1054 // An increment is complete, but there is still more data to be transferred...
1055 PrintDebug("Integral Complete, still transferring more sectors\n");
1056 channel->status.data_req = 1;
1058 drive->irq_flags.c_d = 0;
1060 PrintDebug("Final Sector Transferred\n");
1061 // This was the final read of the request
1062 channel->status.data_req = 0;
1065 drive->irq_flags.c_d = 1;
1066 drive->irq_flags.rel = 0;
1069 channel->status.ready = 1;
1070 drive->irq_flags.io_dir = 1;
1071 channel->status.busy = 0;
1073 ide_raise_irq(dev, channel);
1082 static int read_cd_data(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
1083 struct ide_drive * drive = get_selected_drive(channel);
1084 int data_offset = drive->transfer_index % ATAPI_BLOCK_SIZE;
1085 int req_offset = drive->transfer_index % drive->req_len;
1087 if (drive->cd_state.atapi_cmd != 0x28) {
1088 PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len);
1091 if (drive->transfer_index >= drive->transfer_length) {
1092 PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n",
1093 drive->transfer_length, drive->transfer_index,
1094 drive->transfer_index + length);
1099 if ((data_offset == 0) && (drive->transfer_index > 0)) {
1100 if (atapi_update_data_buf(dev, channel) == -1) {
1101 PrintError("Could not update CDROM data buffer\n");
1106 memcpy(dst, drive->data_buf + data_offset, length);
1108 drive->transfer_index += length;
1111 // Should the req_offset be recalculated here?????
1112 if ((req_offset == 0) && (drive->transfer_index > 0)) {
1113 if (drive->transfer_index < drive->transfer_length) {
1114 // An increment is complete, but there is still more data to be transferred...
1116 channel->status.data_req = 1;
1118 drive->irq_flags.c_d = 0;
1120 // Update the request length in the cylinder regs
1121 if (atapi_update_req_len(dev, channel, drive->transfer_length - drive->transfer_index) == -1) {
1122 PrintError("Could not update request length after completed increment\n");
1126 // This was the final read of the request
1127 channel->status.data_req = 0;
1128 channel->status.ready = 1;
1130 drive->irq_flags.c_d = 1;
1131 drive->irq_flags.rel = 0;
1134 drive->irq_flags.io_dir = 1;
1135 channel->status.busy = 0;
1137 ide_raise_irq(dev, channel);
1144 static int read_drive_id(uint8_t * dst, uint_t length, struct vm_device * dev, struct ide_channel * channel) {
1145 struct ide_drive * drive = get_selected_drive(channel);
1147 channel->status.busy = 0;
1148 channel->status.ready = 1;
1149 channel->status.write_fault = 0;
1150 channel->status.seek_complete = 1;
1151 channel->status.corrected = 0;
1152 channel->status.error = 0;
1155 memcpy(dst, drive->data_buf + drive->transfer_index, length);
1156 drive->transfer_index += length;
1158 if (drive->transfer_index >= drive->transfer_length) {
1159 channel->status.data_req = 0;
1166 static int ide_read_data_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
1167 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1168 struct ide_channel * channel = get_selected_channel(ide, port);
1169 struct ide_drive * drive = get_selected_drive(channel);
1171 // PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length);
1173 if ((channel->cmd_reg == 0xec) ||
1174 (channel->cmd_reg == 0xa1)) {
1175 return read_drive_id((uint8_t *)dst, length, dev, channel);
1178 if (drive->drive_type == IDE_CDROM) {
1179 if (read_cd_data((uint8_t *)dst, length, dev, channel) == -1) {
1180 PrintError("IDE: Could not read CD Data\n");
1183 } else if (drive->drive_type == IDE_DISK) {
1184 if (read_hd_data((uint8_t *)dst, length, dev, channel) == -1) {
1185 PrintError("IDE: Could not read HD Data\n");
1189 memset((uint8_t *)dst, 0, length);
1195 static int write_port_std(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
1196 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1197 struct ide_channel * channel = get_selected_channel(ide, port);
1198 struct ide_drive * drive = get_selected_drive(channel);
1201 PrintError("Invalid Write length on IDE port %x\n", port);
1205 PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
1208 // reset and interrupt enable
1210 case SEC_CTRL_PORT: {
1211 struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
1213 // only reset channel on a 0->1 reset bit transition
1214 if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
1215 channel_reset(channel);
1216 } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
1217 channel_reset_complete(channel);
1220 channel->ctrl_reg.val = tmp_ctrl->val;
1223 case PRI_FEATURES_PORT:
1224 case SEC_FEATURES_PORT:
1225 channel->features.val = *(uint8_t *)src;
1228 case PRI_SECT_CNT_PORT:
1229 case SEC_SECT_CNT_PORT:
1230 channel->drives[0].sector_count = *(uint8_t *)src;
1231 channel->drives[1].sector_count = *(uint8_t *)src;
1234 case PRI_SECT_NUM_PORT:
1235 case SEC_SECT_NUM_PORT:
1236 channel->drives[0].sector_num = *(uint8_t *)src;
1237 channel->drives[1].sector_num = *(uint8_t *)src;
1239 case PRI_CYL_LOW_PORT:
1240 case SEC_CYL_LOW_PORT:
1241 channel->drives[0].cylinder_low = *(uint8_t *)src;
1242 channel->drives[1].cylinder_low = *(uint8_t *)src;
1245 case PRI_CYL_HIGH_PORT:
1246 case SEC_CYL_HIGH_PORT:
1247 channel->drives[0].cylinder_high = *(uint8_t *)src;
1248 channel->drives[1].cylinder_high = *(uint8_t *)src;
1251 case PRI_DRV_SEL_PORT:
1252 case SEC_DRV_SEL_PORT: {
1253 channel->drive_head.val = *(uint8_t *)src;
1255 // make sure the reserved bits are ok..
1256 // JRL TODO: check with new ramdisk to make sure this is right...
1257 channel->drive_head.val |= 0xa0;
1259 drive = get_selected_drive(channel);
1261 // Selecting a non-present device is a no-no
1262 if (drive->drive_type == IDE_NONE) {
1263 PrintDebug("Attempting to select a non-present drive\n");
1264 channel->error_reg.abort = 1;
1265 channel->status.error = 1;
1271 PrintError("IDE: Write to unknown Port %x\n", port);
1278 static int read_port_std(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
1279 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1280 struct ide_channel * channel = get_selected_channel(ide, port);
1281 struct ide_drive * drive = get_selected_drive(channel);
1284 PrintError("Invalid Read length on IDE port %x\n", port);
1288 PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port));
1290 if ((port == PRI_ADDR_REG_PORT) ||
1291 (port == SEC_ADDR_REG_PORT)) {
1292 // unused, return 0xff
1293 *(uint8_t *)dst = 0xff;
1298 // if no drive is present just return 0 + reserved bits
1299 if (drive->drive_type == IDE_NONE) {
1300 if ((port == PRI_DRV_SEL_PORT) ||
1301 (port == SEC_DRV_SEL_PORT)) {
1302 *(uint8_t *)dst = 0xa0;
1304 *(uint8_t *)dst = 0;
1312 // This is really the error register.
1313 case PRI_FEATURES_PORT:
1314 case SEC_FEATURES_PORT:
1315 *(uint8_t *)dst = channel->error_reg.val;
1318 case PRI_SECT_CNT_PORT:
1319 case SEC_SECT_CNT_PORT:
1320 *(uint8_t *)dst = drive->sector_count;
1323 case PRI_SECT_NUM_PORT:
1324 case SEC_SECT_NUM_PORT:
1325 *(uint8_t *)dst = drive->sector_num;
1328 case PRI_CYL_LOW_PORT:
1329 case SEC_CYL_LOW_PORT:
1330 *(uint8_t *)dst = drive->cylinder_low;
1334 case PRI_CYL_HIGH_PORT:
1335 case SEC_CYL_HIGH_PORT:
1336 *(uint8_t *)dst = drive->cylinder_high;
1339 case PRI_DRV_SEL_PORT:
1340 case SEC_DRV_SEL_PORT: // hard disk drive and head register 0x1f6
1341 *(uint8_t *)dst = channel->drive_head.val;
1348 // Something about lowering interrupts here....
1349 *(uint8_t *)dst = channel->status.val;
1353 PrintError("Invalid Port: %x\n", port);
1357 PrintDebug("\tVal=%x\n", *(uint8_t *)dst);
1364 static void init_drive(struct ide_drive * drive) {
1366 drive->sector_count = 0x01;
1367 drive->sector_num = 0x01;
1368 drive->cylinder = 0x0000;
1370 drive->drive_type = IDE_NONE;
1372 memset(drive->model, 0, sizeof(drive->model));
1374 drive->transfer_index = 0;
1375 drive->transfer_length = 0;
1376 memset(drive->data_buf, 0, sizeof(drive->data_buf));
1378 drive->num_cylinders = 0;
1379 drive->num_heads = 0;
1380 drive->num_sectors = 0;
1383 drive->private_data = NULL;
1384 drive->cd_ops = NULL;
1387 static void init_channel(struct ide_channel * channel) {
1390 channel->error_reg.val = 0x01;
1391 channel->drive_head.val = 0x00;
1392 channel->status.val = 0x00;
1393 channel->cmd_reg = 0x00;
1394 channel->ctrl_reg.val = 0x08;
1397 channel->dma_cmd.val = 0;
1398 channel->dma_status.val = 0;
1399 channel->dma_prd_addr = 0;
1400 channel->dma_tbl_index = 0;
1402 for (i = 0; i < 2; i++) {
1403 init_drive(&(channel->drives[i]));
1409 static int pci_config_update(struct pci_device * pci_dev, uint_t reg_num, int length) {
1410 PrintDebug("PCI Config Update\n");
1411 PrintDebug("\t\tInterupt register (Dev=%s), irq=%d\n", pci_dev->name, pci_dev->config_header.intr_line);
1416 static int init_ide_state(struct vm_device * dev) {
1417 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1421 * Check if the PIIX 3 actually represents both IDE channels in a single PCI entry
1424 for (i = 0; i < 1; i++) {
1425 init_channel(&(ide->channels[i]));
1427 // JRL: this is a terrible hack...
1428 ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
1437 static int init_ide(struct vm_device * dev) {
1438 struct ide_internal * ide = (struct ide_internal *)(dev->private_data);
1440 PrintDebug("IDE: Initializing IDE\n");
1442 if (init_ide_state(dev) == -1) {
1443 PrintError("Failed to initialize IDE state\n");
1447 PrintDebug("Connecting to IDE IO ports\n");
1449 v3_dev_hook_io(dev, PRI_DATA_PORT,
1450 &ide_read_data_port, &write_data_port);
1451 v3_dev_hook_io(dev, PRI_FEATURES_PORT,
1452 &read_port_std, &write_port_std);
1453 v3_dev_hook_io(dev, PRI_SECT_CNT_PORT,
1454 &read_port_std, &write_port_std);
1455 v3_dev_hook_io(dev, PRI_SECT_NUM_PORT,
1456 &read_port_std, &write_port_std);
1457 v3_dev_hook_io(dev, PRI_CYL_LOW_PORT,
1458 &read_port_std, &write_port_std);
1459 v3_dev_hook_io(dev, PRI_CYL_HIGH_PORT,
1460 &read_port_std, &write_port_std);
1461 v3_dev_hook_io(dev, PRI_DRV_SEL_PORT,
1462 &read_port_std, &write_port_std);
1463 v3_dev_hook_io(dev, PRI_CMD_PORT,
1464 &read_port_std, &write_cmd_port);
1466 v3_dev_hook_io(dev, SEC_DATA_PORT,
1467 &ide_read_data_port, &write_data_port);
1468 v3_dev_hook_io(dev, SEC_FEATURES_PORT,
1469 &read_port_std, &write_port_std);
1470 v3_dev_hook_io(dev, SEC_SECT_CNT_PORT,
1471 &read_port_std, &write_port_std);
1472 v3_dev_hook_io(dev, SEC_SECT_NUM_PORT,
1473 &read_port_std, &write_port_std);
1474 v3_dev_hook_io(dev, SEC_CYL_LOW_PORT,
1475 &read_port_std, &write_port_std);
1476 v3_dev_hook_io(dev, SEC_CYL_HIGH_PORT,
1477 &read_port_std, &write_port_std);
1478 v3_dev_hook_io(dev, SEC_DRV_SEL_PORT,
1479 &read_port_std, &write_port_std);
1480 v3_dev_hook_io(dev, SEC_CMD_PORT,
1481 &read_port_std, &write_cmd_port);
1484 v3_dev_hook_io(dev, PRI_CTRL_PORT,
1485 &read_port_std, &write_port_std);
1487 v3_dev_hook_io(dev, SEC_CTRL_PORT,
1488 &read_port_std, &write_port_std);
1491 v3_dev_hook_io(dev, SEC_ADDR_REG_PORT,
1492 &read_port_std, &write_port_std);
1494 v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
1495 &read_port_std, &write_port_std);
1501 struct v3_pci_bar bars[6];
1502 struct v3_southbridge * southbridge = (struct v3_southbridge *)(ide->southbridge);
1503 struct pci_device * sb_pci = (struct pci_device *)(southbridge->southbridge_pci);
1504 struct pci_device * pci_dev = NULL;
1507 PrintDebug("Connecting IDE to PCI bus\n");
1509 for (i = 0; i < 6; i++) {
1510 bars[i].type = PCI_BAR_NONE;
1513 bars[4].type = PCI_BAR_IO;
1514 bars[4].default_base_port = PRI_DEFAULT_DMA_PORT;
1515 bars[4].num_ports = 16;
1517 bars[4].io_read = read_dma_port;
1518 bars[4].io_write = write_dma_port;
1520 pci_dev = v3_pci_register_device(ide->pci_bus, PCI_STD_DEVICE, 0, sb_pci->dev_num, 1,
1522 pci_config_update, NULL, NULL, dev);
1524 if (pci_dev == NULL) {
1525 PrintError("Failed to register IDE BUS %d with PCI\n", i);
1529 /* This is for CMD646 devices
1530 pci_dev->config_header.vendor_id = 0x1095;
1531 pci_dev->config_header.device_id = 0x0646;
1532 pci_dev->config_header.revision = 0x8f07;
1535 pci_dev->config_header.vendor_id = 0x8086;
1536 pci_dev->config_header.device_id = 0x7010;
1537 pci_dev->config_header.revision = 0x00;
1539 pci_dev->config_header.prog_if = 0x80;
1540 pci_dev->config_header.subclass = 0x01;
1541 pci_dev->config_header.class = 0x01;
1543 pci_dev->config_header.command = 0;
1544 pci_dev->config_header.status = 0x0280;
1546 ide->ide_pci = pci_dev;
1551 PrintDebug("IDE Initialized\n");
1557 static int deinit_ide(struct vm_device * dev) {
1558 // unhook io ports....
1559 // deregister from PCI?
1564 static struct vm_device_ops dev_ops = {
1566 .deinit = deinit_ide,
1573 struct vm_device * v3_create_ide(struct vm_device * pci_bus, struct vm_device * southbridge_dev) {
1574 struct ide_internal * ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
1576 memset(ide, 0, sizeof(struct ide_internal));
1578 struct vm_device * device = v3_create_device("IDE", &dev_ops, ide);
1580 if (pci_bus != NULL) {
1581 if (southbridge_dev == NULL) {
1582 PrintError("PCI Enabled BUT southbridge is NULL\n");
1586 ide->pci_bus = pci_bus;
1587 ide->southbridge = (struct v3_southbridge *)(southbridge_dev->private_data);
1591 PrintDebug("IDE: Creating IDE bus x 2\n");
1598 int v3_ide_get_geometry(struct vm_device * ide_dev, int channel_num, int drive_num,
1599 uint32_t * cylinders, uint32_t * heads, uint32_t * sectors) {
1601 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1602 struct ide_channel * channel = &(ide->channels[channel_num]);
1603 struct ide_drive * drive = &(channel->drives[drive_num]);
1605 if (drive->drive_type == IDE_NONE) {
1609 *cylinders = drive->num_cylinders;
1610 *heads = drive->num_heads;
1611 *sectors = drive->num_sectors;
1619 int v3_ide_register_cdrom(struct vm_device * ide_dev,
1623 struct v3_ide_cd_ops * ops,
1624 void * private_data) {
1626 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1627 struct ide_channel * channel = NULL;
1628 struct ide_drive * drive = NULL;
1630 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1631 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1633 channel = &(ide->channels[bus_num]);
1634 drive = &(channel->drives[drive_num]);
1636 if (drive->drive_type != IDE_NONE) {
1637 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1641 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1643 while (strlen((char *)(drive->model)) < 40) {
1644 strcat((char*)(drive->model), " ");
1648 drive->drive_type = IDE_CDROM;
1650 drive->cd_ops = ops;
1653 // Hardcode this for now, but its not a good idea....
1654 ide->ide_pci->config_space[0x41 + (bus_num * 2)] = 0x80;
1657 drive->private_data = private_data;
1663 int v3_ide_register_harddisk(struct vm_device * ide_dev,
1667 struct v3_ide_hd_ops * ops,
1668 void * private_data) {
1670 struct ide_internal * ide = (struct ide_internal *)(ide_dev->private_data);
1671 struct ide_channel * channel = NULL;
1672 struct ide_drive * drive = NULL;
1674 V3_ASSERT((bus_num >= 0) && (bus_num < 2));
1675 V3_ASSERT((drive_num >= 0) && (drive_num < 2));
1677 channel = &(ide->channels[bus_num]);
1678 drive = &(channel->drives[drive_num]);
1680 if (drive->drive_type != IDE_NONE) {
1681 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1685 strncpy(drive->model, dev_name, sizeof(drive->model) - 1);
1687 drive->drive_type = IDE_DISK;
1689 drive->hd_state.accessed = 0;
1690 drive->hd_state.mult_sector_num = 1;
1692 drive->hd_ops = ops;
1694 /* this is something of a hack... */
1695 drive->num_sectors = 63;
1696 drive->num_heads = 16;
1697 drive->num_cylinders = ops->get_capacity(private_data) / (drive->num_sectors * drive->num_heads);
1700 // Hardcode this for now, but its not a good idea....
1701 ide->ide_pci->config_space[0x41 + (bus_num * 2)] = 0x80;
1706 drive->private_data = private_data;