2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <palacios/vmm.h>
21 #include <palacios/vmm_dev_mgr.h>
22 #include <palacios/vm_guest_mem.h>
23 #include <devices/ide.h>
24 #include <devices/pci.h>
25 #include <devices/southbridge.h>
26 #include "ide-types.h"
27 #include "atapi-types.h"
29 #ifndef CONFIG_DEBUG_IDE
31 #define PrintDebug(fmt, args...)
34 #define PRI_DEFAULT_IRQ 14
35 #define SEC_DEFAULT_IRQ 15
38 #define PRI_DATA_PORT 0x1f0
39 #define PRI_FEATURES_PORT 0x1f1
40 #define PRI_SECT_CNT_PORT 0x1f2
41 #define PRI_SECT_NUM_PORT 0x1f3
42 #define PRI_CYL_LOW_PORT 0x1f4
43 #define PRI_CYL_HIGH_PORT 0x1f5
44 #define PRI_DRV_SEL_PORT 0x1f6
45 #define PRI_CMD_PORT 0x1f7
46 #define PRI_CTRL_PORT 0x3f6
47 #define PRI_ADDR_REG_PORT 0x3f7
49 #define SEC_DATA_PORT 0x170
50 #define SEC_FEATURES_PORT 0x171
51 #define SEC_SECT_CNT_PORT 0x172
52 #define SEC_SECT_NUM_PORT 0x173
53 #define SEC_CYL_LOW_PORT 0x174
54 #define SEC_CYL_HIGH_PORT 0x175
55 #define SEC_DRV_SEL_PORT 0x176
56 #define SEC_CMD_PORT 0x177
57 #define SEC_CTRL_PORT 0x376
58 #define SEC_ADDR_REG_PORT 0x377
61 #define PRI_DEFAULT_DMA_PORT 0xc000
62 #define SEC_DEFAULT_DMA_PORT 0xc008
64 #define DATA_BUFFER_SIZE 2048
66 #define ATAPI_BLOCK_SIZE 2048
67 #define HD_SECTOR_SIZE 512
70 static const char * ide_pri_port_strs[] = {"PRI_DATA", "PRI_FEATURES", "PRI_SECT_CNT", "PRI_SECT_NUM",
71 "PRI_CYL_LOW", "PRI_CYL_HIGH", "PRI_DRV_SEL", "PRI_CMD",
72 "PRI_CTRL", "PRI_ADDR_REG"};
75 static const char * ide_sec_port_strs[] = {"SEC_DATA", "SEC_FEATURES", "SEC_SECT_CNT", "SEC_SECT_NUM",
76 "SEC_CYL_LOW", "SEC_CYL_HIGH", "SEC_DRV_SEL", "SEC_CMD",
77 "SEC_CTRL", "SEC_ADDR_REG"};
79 static const char * ide_dma_port_strs[] = {"DMA_CMD", NULL, "DMA_STATUS", NULL,
80 "DMA_PRD0", "DMA_PRD1", "DMA_PRD2", "DMA_PRD3"};
83 typedef enum {BLOCK_NONE, BLOCK_DISK, BLOCK_CDROM} v3_block_type_t;
85 static inline const char * io_port_to_str(uint16_t port) {
86 if ((port >= PRI_DATA_PORT) && (port <= PRI_CMD_PORT)) {
87 return ide_pri_port_strs[port - PRI_DATA_PORT];
88 } else if ((port >= SEC_DATA_PORT) && (port <= SEC_CMD_PORT)) {
89 return ide_sec_port_strs[port - SEC_DATA_PORT];
90 } else if ((port == PRI_CTRL_PORT) || (port == PRI_ADDR_REG_PORT)) {
91 return ide_pri_port_strs[port - PRI_CTRL_PORT + 8];
92 } else if ((port == SEC_CTRL_PORT) || (port == SEC_ADDR_REG_PORT)) {
93 return ide_sec_port_strs[port - SEC_CTRL_PORT + 8];
99 static inline const char * dma_port_to_str(uint16_t port) {
100 return ide_dma_port_strs[port & 0x7];
105 struct ide_cd_state {
106 struct atapi_sense_data sense;
109 struct atapi_error_recovery err_recovery;
112 struct ide_hd_state {
115 /* this is the multiple sector transfer size as configured for read/write multiple sectors*/
116 uint_t mult_sector_num;
118 /* This is the current op sector size:
119 * for multiple sector ops this equals mult_sector_num
120 * for standard ops this equals 1
122 uint_t cur_sector_num;
128 v3_block_type_t drive_type;
130 struct v3_dev_blk_ops * ops;
133 struct ide_cd_state cd_state;
134 struct ide_hd_state hd_state;
139 // Where we are in the data transfer
140 uint_t transfer_index;
142 // the length of a transfer
143 // calculated for easy access
144 uint_t transfer_length;
146 uint64_t current_lba;
148 // We have a local data buffer that we use for IO port accesses
149 uint8_t data_buf[DATA_BUFFER_SIZE];
152 uint32_t num_cylinders;
154 uint32_t num_sectors;
159 uint8_t sector_count; // 0x1f2,0x172
160 struct atapi_irq_flags irq_flags;
161 } __attribute__((packed));
164 uint8_t sector_num; // 0x1f3,0x173
166 } __attribute__((packed));
173 uint8_t cylinder_low; // 0x1f4,0x174
174 uint8_t cylinder_high; // 0x1f5,0x175
175 } __attribute__((packed));
180 } __attribute__((packed));
183 // The transfer length requested by the CPU
185 } __attribute__((packed));
192 struct ide_drive drives[2];
195 struct ide_error_reg error_reg; // [read] 0x1f1,0x171
197 struct ide_features_reg features;
199 struct ide_drive_head_reg drive_head; // 0x1f6,0x176
201 struct ide_status_reg status; // [read] 0x1f7,0x177
202 uint8_t cmd_reg; // [write] 0x1f7,0x177
204 int irq; // this is temporary until we add PCI support
207 struct ide_ctrl_reg ctrl_reg; // [write] 0x3f6,0x376
209 struct ide_dma_cmd_reg dma_cmd;
210 struct ide_dma_status_reg dma_status;
211 uint32_t dma_prd_addr;
212 uint_t dma_tbl_index;
217 struct ide_internal {
218 struct ide_channel channels[2];
220 struct v3_southbridge * southbridge;
221 struct vm_device * pci_bus;
223 struct pci_device * ide_pci;
225 struct v3_vm_info * vm;
232 /* Utility functions */
234 static inline uint16_t be_to_le_16(const uint16_t val) {
235 uint8_t * buf = (uint8_t *)&val;
236 return (buf[0] << 8) | (buf[1]) ;
239 static inline uint16_t le_to_be_16(const uint16_t val) {
240 return be_to_le_16(val);
244 static inline uint32_t be_to_le_32(const uint32_t val) {
245 uint8_t * buf = (uint8_t *)&val;
246 return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
249 static inline uint32_t le_to_be_32(const uint32_t val) {
250 return be_to_le_32(val);
254 static inline int get_channel_index(ushort_t port) {
255 if (((port & 0xfff8) == 0x1f0) ||
256 ((port & 0xfffe) == 0x3f6) ||
257 ((port & 0xfff8) == 0xc000)) {
259 } else if (((port & 0xfff8) == 0x170) ||
260 ((port & 0xfffe) == 0x376) ||
261 ((port & 0xfff8) == 0xc008)) {
268 static inline struct ide_channel * get_selected_channel(struct ide_internal * ide, ushort_t port) {
269 int channel_idx = get_channel_index(port);
270 return &(ide->channels[channel_idx]);
273 static inline struct ide_drive * get_selected_drive(struct ide_channel * channel) {
274 return &(channel->drives[channel->drive_head.drive_sel]);
278 static inline int is_lba_enabled(struct ide_channel * channel) {
279 return channel->drive_head.lba_mode;
284 static void ide_raise_irq(struct ide_internal * ide, struct ide_channel * channel) {
285 if (channel->ctrl_reg.irq_disable == 0) {
286 // PrintError("Raising IDE Interrupt %d\n", channel->irq);
287 channel->dma_status.int_gen = 1;
288 v3_raise_irq(ide->vm, channel->irq);
293 static void drive_reset(struct ide_drive * drive) {
294 drive->sector_count = 0x01;
295 drive->sector_num = 0x01;
297 PrintDebug("Resetting drive %s\n", drive->model);
299 if (drive->drive_type == BLOCK_CDROM) {
300 drive->cylinder = 0xeb14;
302 drive->cylinder = 0x0000;
303 //drive->hd_state.accessed = 0;
307 memset(drive->data_buf, 0, sizeof(drive->data_buf));
308 drive->transfer_index = 0;
310 // Send the reset signal to the connected device callbacks
311 // channel->drives[0].reset();
312 // channel->drives[1].reset();
315 static void channel_reset(struct ide_channel * channel) {
317 // set busy and seek complete flags
318 channel->status.val = 0x90;
321 channel->error_reg.val = 0x01;
324 channel->cmd_reg = 0x00;
326 channel->ctrl_reg.irq_disable = 0;
329 static void channel_reset_complete(struct ide_channel * channel) {
330 channel->status.busy = 0;
331 channel->status.ready = 1;
333 channel->drive_head.head_num = 0;
335 drive_reset(&(channel->drives[0]));
336 drive_reset(&(channel->drives[1]));
340 static void ide_abort_command(struct ide_internal * ide, struct ide_channel * channel) {
341 channel->status.val = 0x41; // Error + ready
342 channel->error_reg.val = 0x04; // No idea...
344 ide_raise_irq(ide, channel);
348 static int dma_read(struct guest_info * core, struct ide_internal * ide, struct ide_channel * channel);
349 static int dma_write(struct guest_info * core, struct ide_internal * ide, struct ide_channel * channel);
352 /* ATAPI functions */
359 #ifdef CONFIG_DEBUG_IDE
360 static void print_prd_table(struct ide_internal * ide, struct ide_channel * channel) {
361 struct ide_dma_prd prd_entry;
364 PrintDebug("Dumping PRD table\n");
367 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * index);
370 ret = v3_read_gpa_memory(&(ide->vm->cores[0]), prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
372 if (ret != sizeof(struct ide_dma_prd)) {
373 PrintError("Could not read PRD\n");
377 PrintDebug("\tPRD Addr: %x, PRD Len: %d, EOT: %d\n",
378 prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
380 if (prd_entry.end_of_table) {
392 static int dma_read(struct guest_info * core, struct ide_internal * ide, struct ide_channel * channel) {
393 struct ide_drive * drive = get_selected_drive(channel);
394 // This is at top level scope to do the EOT test at the end
395 struct ide_dma_prd prd_entry = {};
396 uint_t bytes_left = drive->transfer_length;
398 // Read in the data buffer....
399 // Read a sector/block at a time until the prd entry is full.
401 #ifdef CONFIG_DEBUG_IDE
402 print_prd_table(ide, channel);
405 PrintDebug("DMA read for %d bytes\n", bytes_left);
407 // Loop through the disk data
408 while (bytes_left > 0) {
409 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
410 uint_t prd_bytes_left = 0;
411 uint_t prd_offset = 0;
414 PrintDebug("PRD table address = %x\n", channel->dma_prd_addr);
416 ret = v3_read_gpa_memory(core, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
418 if (ret != sizeof(struct ide_dma_prd)) {
419 PrintError("Could not read PRD\n");
423 PrintDebug("PRD Addr: %x, PRD Len: %d, EOT: %d\n",
424 prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
426 // loop through the PRD data....
428 prd_bytes_left = prd_entry.size;
431 while (prd_bytes_left > 0) {
432 uint_t bytes_to_write = 0;
434 if (drive->drive_type == BLOCK_DISK) {
435 bytes_to_write = (prd_bytes_left > HD_SECTOR_SIZE) ? HD_SECTOR_SIZE : prd_bytes_left;
438 if (ata_read(ide, channel, drive->data_buf, 1) == -1) {
439 PrintError("Failed to read next disk sector\n");
442 } else if (drive->drive_type == BLOCK_CDROM) {
443 if (atapi_cmd_is_data_op(drive->cd_state.atapi_cmd)) {
444 bytes_to_write = (prd_bytes_left > ATAPI_BLOCK_SIZE) ? ATAPI_BLOCK_SIZE : prd_bytes_left;
446 if (atapi_read_chunk(ide, channel) == -1) {
447 PrintError("Failed to read next disk sector\n");
451 PrintDebug("DMA of command packet\n");
452 PrintError("How does this work???\n");
454 bytes_to_write = (prd_bytes_left > bytes_left) ? bytes_left : prd_bytes_left;
455 prd_bytes_left = bytes_to_write;
459 PrintDebug("Writing DMA data to guest Memory ptr=%p, len=%d\n",
460 (void *)(addr_t)(prd_entry.base_addr + prd_offset), bytes_to_write);
462 drive->current_lba++;
464 ret = v3_write_gpa_memory(core, prd_entry.base_addr + prd_offset, bytes_to_write, drive->data_buf);
466 if (ret != bytes_to_write) {
467 PrintError("Failed to copy data into guest memory... (ret=%d)\n", ret);
471 PrintDebug("\t DMA ret=%d, (prd_bytes_left=%d) (bytes_left=%d)\n", ret, prd_bytes_left, bytes_left);
473 drive->transfer_index += ret;
474 prd_bytes_left -= ret;
479 channel->dma_tbl_index++;
481 if (drive->drive_type == BLOCK_DISK) {
482 if (drive->transfer_index % HD_SECTOR_SIZE) {
483 PrintError("We currently don't handle sectors that span PRD descriptors\n");
486 } else if (drive->drive_type == BLOCK_CDROM) {
487 if (atapi_cmd_is_data_op(drive->cd_state.atapi_cmd)) {
488 if (drive->transfer_index % ATAPI_BLOCK_SIZE) {
489 PrintError("We currently don't handle ATAPI BLOCKS that span PRD descriptors\n");
490 PrintError("transfer_index=%d, transfer_length=%d\n",
491 drive->transfer_index, drive->transfer_length);
498 if ((prd_entry.end_of_table == 1) && (bytes_left > 0)) {
499 PrintError("DMA table not large enough for data transfer...\n");
505 drive->irq_flags.io_dir = 1;
506 drive->irq_flags.c_d = 1;
507 drive->irq_flags.rel = 0;
511 // Update to the next PRD entry
515 if (prd_entry.end_of_table) {
516 channel->status.busy = 0;
517 channel->status.ready = 1;
518 channel->status.data_req = 0;
519 channel->status.error = 0;
520 channel->status.seek_complete = 1;
522 channel->dma_status.active = 0;
523 channel->dma_status.err = 0;
526 ide_raise_irq(ide, channel);
532 static int dma_write(struct guest_info * core, struct ide_internal * ide, struct ide_channel * channel) {
533 struct ide_drive * drive = get_selected_drive(channel);
534 // This is at top level scope to do the EOT test at the end
535 struct ide_dma_prd prd_entry = {};
536 uint_t bytes_left = drive->transfer_length;
539 PrintDebug("DMA write from %d bytes\n", bytes_left);
541 // Loop through disk data
542 while (bytes_left > 0) {
543 uint32_t prd_entry_addr = channel->dma_prd_addr + (sizeof(struct ide_dma_prd) * channel->dma_tbl_index);
544 uint_t prd_bytes_left = 0;
545 uint_t prd_offset = 0;
548 PrintDebug("PRD Table address = %x\n", channel->dma_prd_addr);
550 ret = v3_read_gpa_memory(core, prd_entry_addr, sizeof(struct ide_dma_prd), (void *)&prd_entry);
552 if (ret != sizeof(struct ide_dma_prd)) {
553 PrintError("Could not read PRD\n");
557 PrintDebug("PRD Addr: %x, PRD Len: %d, EOT: %d\n",
558 prd_entry.base_addr, prd_entry.size, prd_entry.end_of_table);
560 prd_bytes_left = prd_entry.size;
562 while (prd_bytes_left > 0) {
563 uint_t bytes_to_write = 0;
566 bytes_to_write = (prd_bytes_left > HD_SECTOR_SIZE) ? HD_SECTOR_SIZE : prd_bytes_left;
569 ret = v3_read_gpa_memory(core, prd_entry.base_addr + prd_offset, bytes_to_write, drive->data_buf);
571 if (ret != bytes_to_write) {
572 PrintError("Faild to copy data from guest memory... (ret=%d)\n", ret);
576 PrintDebug("\t DMA ret=%d (prd_bytes_left=%d) (bytes_left=%d)\n", ret, prd_bytes_left, bytes_left);
579 if (ata_write(ide, channel, drive->data_buf, 1) == -1) {
580 PrintError("Failed to write data to disk\n");
584 drive->current_lba++;
586 drive->transfer_index += ret;
587 prd_bytes_left -= ret;
592 channel->dma_tbl_index++;
594 if (drive->transfer_index % HD_SECTOR_SIZE) {
595 PrintError("We currently don't handle sectors that span PRD descriptors\n");
599 if ((prd_entry.end_of_table == 1) && (bytes_left > 0)) {
600 PrintError("DMA table not large enough for data transfer...\n");
605 if (prd_entry.end_of_table) {
606 channel->status.busy = 0;
607 channel->status.ready = 1;
608 channel->status.data_req = 0;
609 channel->status.error = 0;
610 channel->status.seek_complete = 1;
612 channel->dma_status.active = 0;
613 channel->dma_status.err = 0;
616 ide_raise_irq(ide, channel);
623 #define DMA_CMD_PORT 0x00
624 #define DMA_STATUS_PORT 0x02
625 #define DMA_PRD_PORT0 0x04
626 #define DMA_PRD_PORT1 0x05
627 #define DMA_PRD_PORT2 0x06
628 #define DMA_PRD_PORT3 0x07
630 #define DMA_CHANNEL_FLAG 0x08
632 static int write_dma_port(struct guest_info * core, ushort_t port, void * src, uint_t length, void * private_data) {
633 struct ide_internal * ide = (struct ide_internal *)private_data;
634 uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
635 uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
636 struct ide_channel * channel = &(ide->channels[channel_flag]);
638 PrintDebug("IDE: Writing DMA Port %x (%s) (val=%x) (len=%d) (channel=%d)\n",
639 port, dma_port_to_str(port_offset), *(uint32_t *)src, length, channel_flag);
641 switch (port_offset) {
643 channel->dma_cmd.val = *(uint8_t *)src;
645 if (channel->dma_cmd.start == 0) {
646 channel->dma_tbl_index = 0;
648 channel->dma_status.active = 1;
650 if (channel->dma_cmd.read == 1) {
652 if (dma_read(core, ide, channel) == -1) {
653 PrintError("Failed DMA Read\n");
658 if (dma_write(core, ide, channel) == -1) {
659 PrintError("Failed DMA Write\n");
664 channel->dma_cmd.val &= 0x09;
669 case DMA_STATUS_PORT: {
670 uint8_t val = *(uint8_t *)src;
673 PrintError("Invalid read length for DMA status port\n");
678 channel->dma_status.val = ((val & 0x60) |
679 (channel->dma_status.val & 0x01) |
680 (channel->dma_status.val & ~val & 0x06));
687 case DMA_PRD_PORT3: {
688 uint_t addr_index = port_offset & 0x3;
689 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
692 if (addr_index + length > 4) {
693 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
697 for (i = 0; i < length; i++) {
698 addr_buf[addr_index + i] = *((uint8_t *)src + i);
701 PrintDebug("Writing PRD Port %x (val=%x)\n", port_offset, channel->dma_prd_addr);
706 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
714 static int read_dma_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * private_data) {
715 struct ide_internal * ide = (struct ide_internal *)private_data;
716 uint16_t port_offset = port & (DMA_CHANNEL_FLAG - 1);
717 uint_t channel_flag = (port & DMA_CHANNEL_FLAG) >> 3;
718 struct ide_channel * channel = &(ide->channels[channel_flag]);
720 PrintDebug("Reading DMA port %d (%x) (channel=%d)\n", port, port, channel_flag);
722 switch (port_offset) {
724 *(uint8_t *)dst = channel->dma_cmd.val;
727 case DMA_STATUS_PORT:
729 PrintError("Invalid read length for DMA status port\n");
733 *(uint8_t *)dst = channel->dma_status.val;
739 case DMA_PRD_PORT3: {
740 uint_t addr_index = port_offset & 0x3;
741 uint8_t * addr_buf = (uint8_t *)&(channel->dma_prd_addr);
744 if (addr_index + length > 4) {
745 PrintError("DMA Port space overrun port=%x len=%d\n", port_offset, length);
749 for (i = 0; i < length; i++) {
750 *((uint8_t *)dst + i) = addr_buf[addr_index + i];
756 PrintError("IDE: Invalid DMA Port (%s)\n", dma_port_to_str(port_offset));
760 PrintDebug("\tval=%x (len=%d)\n", *(uint32_t *)dst, length);
767 static int write_cmd_port(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
768 struct ide_internal * ide = priv_data;
769 struct ide_channel * channel = get_selected_channel(ide, port);
770 struct ide_drive * drive = get_selected_drive(channel);
773 PrintError("Invalid Write Length on IDE command Port %x\n", port);
777 PrintDebug("IDE: Writing Command Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
779 channel->cmd_reg = *(uint8_t *)src;
781 switch (channel->cmd_reg) {
783 case 0xa1: // ATAPI Identify Device Packet
784 if (drive->drive_type != BLOCK_CDROM) {
787 // JRL: Should we abort here?
788 ide_abort_command(ide, channel);
791 atapi_identify_device(drive);
793 channel->error_reg.val = 0;
794 channel->status.val = 0x58; // ready, data_req, seek_complete
796 ide_raise_irq(ide, channel);
799 case 0xec: // Identify Device
800 if (drive->drive_type != BLOCK_DISK) {
803 // JRL: Should we abort here?
804 ide_abort_command(ide, channel);
806 ata_identify_device(drive);
808 channel->error_reg.val = 0;
809 channel->status.val = 0x58;
811 ide_raise_irq(ide, channel);
815 case 0xa0: // ATAPI Command Packet
816 if (drive->drive_type != BLOCK_CDROM) {
817 ide_abort_command(ide, channel);
820 drive->sector_count = 1;
822 channel->status.busy = 0;
823 channel->status.write_fault = 0;
824 channel->status.data_req = 1;
825 channel->status.error = 0;
827 // reset the data buffer...
828 drive->transfer_length = ATAPI_PACKET_SIZE;
829 drive->transfer_index = 0;
833 case 0x20: // Read Sectors with Retry
834 case 0x21: // Read Sectors without Retry
835 drive->hd_state.cur_sector_num = 1;
837 if (ata_read_sectors(ide, channel) == -1) {
838 PrintError("Error reading sectors\n");
843 case 0x24: // Read Sectors Extended
844 drive->hd_state.cur_sector_num = 1;
846 if (ata_read_sectors_ext(ide, channel) == -1) {
847 PrintError("Error reading extended sectors\n");
852 case 0xc8: // Read DMA with retry
853 case 0xc9: { // Read DMA
854 uint32_t sect_cnt = (drive->sector_count == 0) ? 256 : drive->sector_count;
856 if (ata_get_lba(ide, channel, &(drive->current_lba)) == -1) {
857 ide_abort_command(ide, channel);
861 drive->hd_state.cur_sector_num = 1;
863 drive->transfer_length = sect_cnt * HD_SECTOR_SIZE;
864 drive->transfer_index = 0;
866 if (channel->dma_status.active == 1) {
868 if (dma_read(core, ide, channel) == -1) {
869 PrintError("Failed DMA Read\n");
876 case 0xca: { // Write DMA
877 uint32_t sect_cnt = (drive->sector_count == 0) ? 256 : drive->sector_count;
879 if (ata_get_lba(ide, channel, &(drive->current_lba)) == -1) {
880 ide_abort_command(ide, channel);
884 drive->hd_state.cur_sector_num = 1;
886 drive->transfer_length = sect_cnt * HD_SECTOR_SIZE;
887 drive->transfer_index = 0;
889 if (channel->dma_status.active == 1) {
891 if (dma_write(core, ide, channel) == -1) {
892 PrintError("Failed DMA Write\n");
898 case 0xe0: // Standby Now 1
899 case 0xe1: // Set Idle Immediate
900 case 0xe2: // Standby
901 case 0xe3: // Set Idle 1
902 case 0xe6: // Sleep Now 1
903 case 0x94: // Standby Now 2
904 case 0x95: // Idle Immediate (CFA)
905 case 0x96: // Standby 2
906 case 0x97: // Set idle 2
907 case 0x99: // Sleep Now 2
908 channel->status.val = 0;
909 channel->status.ready = 1;
910 ide_raise_irq(ide, channel);
913 case 0xef: // Set Features
914 // Prior to this the features register has been written to.
915 // This command tells the drive to check if the new value is supported (the value is drive specific)
916 // Common is that bit0=DMA enable
917 // If valid the drive raises an interrupt, if not it aborts.
919 // Do some checking here...
921 channel->status.busy = 0;
922 channel->status.write_fault = 0;
923 channel->status.error = 0;
924 channel->status.ready = 1;
925 channel->status.seek_complete = 1;
927 ide_raise_irq(ide, channel);
930 case 0x91: // Initialize Drive Parameters
931 case 0x10: // recalibrate?
932 channel->status.error = 0;
933 channel->status.ready = 1;
934 channel->status.seek_complete = 1;
935 ide_raise_irq(ide, channel);
937 case 0xc6: { // Set multiple mode (IDE Block mode)
938 // This makes the drive transfer multiple sectors before generating an interrupt
939 uint32_t tmp_sect_num = drive->sector_num; // GCC SUCKS
941 if (tmp_sect_num > MAX_MULT_SECTORS) {
942 ide_abort_command(ide, channel);
946 if (drive->sector_count == 0) {
947 drive->hd_state.mult_sector_num= 1;
949 drive->hd_state.mult_sector_num = drive->sector_count;
952 channel->status.ready = 1;
953 channel->status.error = 0;
955 ide_raise_irq(ide, channel);
960 case 0x08: // Reset Device
962 channel->error_reg.val = 0x01;
963 channel->status.busy = 0;
964 channel->status.ready = 1;
965 channel->status.seek_complete = 1;
966 channel->status.write_fault = 0;
967 channel->status.error = 0;
970 case 0xe5: // Check power mode
971 drive->sector_count = 0xff; /* 0x00=standby, 0x80=idle, 0xff=active or idle */
972 channel->status.busy = 0;
973 channel->status.ready = 1;
974 channel->status.write_fault = 0;
975 channel->status.data_req = 0;
976 channel->status.error = 0;
979 case 0xc4: // read multiple sectors
980 drive->hd_state.cur_sector_num = drive->hd_state.mult_sector_num;
982 PrintError("Unimplemented IDE command (%x)\n", channel->cmd_reg);
990 static int write_data_port(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
991 struct ide_internal * ide = priv_data;
992 struct ide_channel * channel = get_selected_channel(ide, port);
993 struct ide_drive * drive = get_selected_drive(channel);
995 // PrintDebug("IDE: Writing Data Port %x (val=%x, len=%d)\n",
996 // port, *(uint32_t *)src, length);
998 memcpy(drive->data_buf + drive->transfer_index, src, length);
999 drive->transfer_index += length;
1001 // Transfer is complete, dispatch the command
1002 if (drive->transfer_index >= drive->transfer_length) {
1003 switch (channel->cmd_reg) {
1004 case 0x30: // Write Sectors
1005 PrintError("Writing Data not yet implemented\n");
1008 case 0xa0: // ATAPI packet command
1009 if (atapi_handle_packet(core, ide, channel) == -1) {
1010 PrintError("Error handling ATAPI packet\n");
1015 PrintError("Unhandld IDE Command %x\n", channel->cmd_reg);
1024 static int read_hd_data(uint8_t * dst, uint_t length, struct ide_internal * ide, struct ide_channel * channel) {
1025 struct ide_drive * drive = get_selected_drive(channel);
1026 int data_offset = drive->transfer_index % HD_SECTOR_SIZE;
1030 if (drive->transfer_index >= drive->transfer_length) {
1031 PrintError("Buffer overrun... (xfer_len=%d) (cur_idx=%x) (post_idx=%d)\n",
1032 drive->transfer_length, drive->transfer_index,
1033 drive->transfer_index + length);
1038 if ((data_offset == 0) && (drive->transfer_index > 0)) {
1039 drive->current_lba++;
1041 if (ata_read(ide, channel, drive->data_buf, 1) == -1) {
1042 PrintError("Could not read next disk sector\n");
1048 PrintDebug("Reading HD Data (Val=%x), (len=%d) (offset=%d)\n",
1049 *(uint32_t *)(drive->data_buf + data_offset),
1050 length, data_offset);
1052 memcpy(dst, drive->data_buf + data_offset, length);
1054 drive->transfer_index += length;
1057 /* This is the trigger for interrupt injection.
1058 * For read single sector commands we interrupt after every sector
1059 * For multi sector reads we interrupt only at end of the cluster size (mult_sector_num)
1060 * cur_sector_num is configured depending on the operation we are currently running
1061 * We also trigger an interrupt if this is the last byte to transfer, regardless of sector count
1063 if (((drive->transfer_index % (HD_SECTOR_SIZE * drive->hd_state.cur_sector_num)) == 0) ||
1064 (drive->transfer_index == drive->transfer_length)) {
1065 if (drive->transfer_index < drive->transfer_length) {
1066 // An increment is complete, but there is still more data to be transferred...
1067 PrintDebug("Integral Complete, still transferring more sectors\n");
1068 channel->status.data_req = 1;
1070 drive->irq_flags.c_d = 0;
1072 PrintDebug("Final Sector Transferred\n");
1073 // This was the final read of the request
1074 channel->status.data_req = 0;
1077 drive->irq_flags.c_d = 1;
1078 drive->irq_flags.rel = 0;
1081 channel->status.ready = 1;
1082 drive->irq_flags.io_dir = 1;
1083 channel->status.busy = 0;
1085 ide_raise_irq(ide, channel);
1094 static int read_cd_data(uint8_t * dst, uint_t length, struct ide_internal * ide, struct ide_channel * channel) {
1095 struct ide_drive * drive = get_selected_drive(channel);
1096 int data_offset = drive->transfer_index % ATAPI_BLOCK_SIZE;
1097 int req_offset = drive->transfer_index % drive->req_len;
1099 if (drive->cd_state.atapi_cmd != 0x28) {
1100 PrintDebug("IDE: Reading CD Data (len=%d) (req_len=%d)\n", length, drive->req_len);
1103 if (drive->transfer_index >= drive->transfer_length) {
1104 PrintError("Buffer Overrun... (xfer_len=%d) (cur_idx=%d) (post_idx=%d)\n",
1105 drive->transfer_length, drive->transfer_index,
1106 drive->transfer_index + length);
1111 if ((data_offset == 0) && (drive->transfer_index > 0)) {
1112 if (atapi_update_data_buf(ide, channel) == -1) {
1113 PrintError("Could not update CDROM data buffer\n");
1118 memcpy(dst, drive->data_buf + data_offset, length);
1120 drive->transfer_index += length;
1123 // Should the req_offset be recalculated here?????
1124 if ((req_offset == 0) && (drive->transfer_index > 0)) {
1125 if (drive->transfer_index < drive->transfer_length) {
1126 // An increment is complete, but there is still more data to be transferred...
1128 channel->status.data_req = 1;
1130 drive->irq_flags.c_d = 0;
1132 // Update the request length in the cylinder regs
1133 if (atapi_update_req_len(ide, channel, drive->transfer_length - drive->transfer_index) == -1) {
1134 PrintError("Could not update request length after completed increment\n");
1138 // This was the final read of the request
1139 channel->status.data_req = 0;
1140 channel->status.ready = 1;
1142 drive->irq_flags.c_d = 1;
1143 drive->irq_flags.rel = 0;
1146 drive->irq_flags.io_dir = 1;
1147 channel->status.busy = 0;
1149 ide_raise_irq(ide, channel);
1156 static int read_drive_id( uint8_t * dst, uint_t length, struct ide_internal * ide, struct ide_channel * channel) {
1157 struct ide_drive * drive = get_selected_drive(channel);
1159 channel->status.busy = 0;
1160 channel->status.ready = 1;
1161 channel->status.write_fault = 0;
1162 channel->status.seek_complete = 1;
1163 channel->status.corrected = 0;
1164 channel->status.error = 0;
1167 memcpy(dst, drive->data_buf + drive->transfer_index, length);
1168 drive->transfer_index += length;
1170 if (drive->transfer_index >= drive->transfer_length) {
1171 channel->status.data_req = 0;
1178 static int ide_read_data_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
1179 struct ide_internal * ide = priv_data;
1180 struct ide_channel * channel = get_selected_channel(ide, port);
1181 struct ide_drive * drive = get_selected_drive(channel);
1183 PrintDebug("IDE: Reading Data Port %x (len=%d)\n", port, length);
1185 if ((channel->cmd_reg == 0xec) ||
1186 (channel->cmd_reg == 0xa1)) {
1187 return read_drive_id((uint8_t *)dst, length, ide, channel);
1190 if (drive->drive_type == BLOCK_CDROM) {
1191 if (read_cd_data((uint8_t *)dst, length, ide, channel) == -1) {
1192 PrintError("IDE: Could not read CD Data\n");
1195 } else if (drive->drive_type == BLOCK_DISK) {
1196 if (read_hd_data((uint8_t *)dst, length, ide, channel) == -1) {
1197 PrintError("IDE: Could not read HD Data\n");
1201 memset((uint8_t *)dst, 0, length);
1207 static int write_port_std(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
1208 struct ide_internal * ide = priv_data;
1209 struct ide_channel * channel = get_selected_channel(ide, port);
1210 struct ide_drive * drive = get_selected_drive(channel);
1213 PrintError("Invalid Write length on IDE port %x\n", port);
1217 PrintDebug("IDE: Writing Standard Port %x (%s) (val=%x)\n", port, io_port_to_str(port), *(uint8_t *)src);
1220 // reset and interrupt enable
1222 case SEC_CTRL_PORT: {
1223 struct ide_ctrl_reg * tmp_ctrl = (struct ide_ctrl_reg *)src;
1225 // only reset channel on a 0->1 reset bit transition
1226 if ((!channel->ctrl_reg.soft_reset) && (tmp_ctrl->soft_reset)) {
1227 channel_reset(channel);
1228 } else if ((channel->ctrl_reg.soft_reset) && (!tmp_ctrl->soft_reset)) {
1229 channel_reset_complete(channel);
1232 channel->ctrl_reg.val = tmp_ctrl->val;
1235 case PRI_FEATURES_PORT:
1236 case SEC_FEATURES_PORT:
1237 channel->features.val = *(uint8_t *)src;
1240 case PRI_SECT_CNT_PORT:
1241 case SEC_SECT_CNT_PORT:
1242 channel->drives[0].sector_count = *(uint8_t *)src;
1243 channel->drives[1].sector_count = *(uint8_t *)src;
1246 case PRI_SECT_NUM_PORT:
1247 case SEC_SECT_NUM_PORT:
1248 channel->drives[0].sector_num = *(uint8_t *)src;
1249 channel->drives[1].sector_num = *(uint8_t *)src;
1251 case PRI_CYL_LOW_PORT:
1252 case SEC_CYL_LOW_PORT:
1253 channel->drives[0].cylinder_low = *(uint8_t *)src;
1254 channel->drives[1].cylinder_low = *(uint8_t *)src;
1257 case PRI_CYL_HIGH_PORT:
1258 case SEC_CYL_HIGH_PORT:
1259 channel->drives[0].cylinder_high = *(uint8_t *)src;
1260 channel->drives[1].cylinder_high = *(uint8_t *)src;
1263 case PRI_DRV_SEL_PORT:
1264 case SEC_DRV_SEL_PORT: {
1265 channel->drive_head.val = *(uint8_t *)src;
1267 // make sure the reserved bits are ok..
1268 // JRL TODO: check with new ramdisk to make sure this is right...
1269 channel->drive_head.val |= 0xa0;
1271 drive = get_selected_drive(channel);
1273 // Selecting a non-present device is a no-no
1274 if (drive->drive_type == BLOCK_NONE) {
1275 PrintDebug("Attempting to select a non-present drive\n");
1276 channel->error_reg.abort = 1;
1277 channel->status.error = 1;
1283 PrintError("IDE: Write to unknown Port %x\n", port);
1290 static int read_port_std(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
1291 struct ide_internal * ide = priv_data;
1292 struct ide_channel * channel = get_selected_channel(ide, port);
1293 struct ide_drive * drive = get_selected_drive(channel);
1296 PrintError("Invalid Read length on IDE port %x\n", port);
1300 PrintDebug("IDE: Reading Standard Port %x (%s)\n", port, io_port_to_str(port));
1302 if ((port == PRI_ADDR_REG_PORT) ||
1303 (port == SEC_ADDR_REG_PORT)) {
1304 // unused, return 0xff
1305 *(uint8_t *)dst = 0xff;
1310 // if no drive is present just return 0 + reserved bits
1311 if (drive->drive_type == BLOCK_NONE) {
1312 if ((port == PRI_DRV_SEL_PORT) ||
1313 (port == SEC_DRV_SEL_PORT)) {
1314 *(uint8_t *)dst = 0xa0;
1316 *(uint8_t *)dst = 0;
1324 // This is really the error register.
1325 case PRI_FEATURES_PORT:
1326 case SEC_FEATURES_PORT:
1327 *(uint8_t *)dst = channel->error_reg.val;
1330 case PRI_SECT_CNT_PORT:
1331 case SEC_SECT_CNT_PORT:
1332 *(uint8_t *)dst = drive->sector_count;
1335 case PRI_SECT_NUM_PORT:
1336 case SEC_SECT_NUM_PORT:
1337 *(uint8_t *)dst = drive->sector_num;
1340 case PRI_CYL_LOW_PORT:
1341 case SEC_CYL_LOW_PORT:
1342 *(uint8_t *)dst = drive->cylinder_low;
1346 case PRI_CYL_HIGH_PORT:
1347 case SEC_CYL_HIGH_PORT:
1348 *(uint8_t *)dst = drive->cylinder_high;
1351 case PRI_DRV_SEL_PORT:
1352 case SEC_DRV_SEL_PORT: // hard disk drive and head register 0x1f6
1353 *(uint8_t *)dst = channel->drive_head.val;
1360 // Something about lowering interrupts here....
1361 *(uint8_t *)dst = channel->status.val;
1365 PrintError("Invalid Port: %x\n", port);
1369 PrintDebug("\tVal=%x\n", *(uint8_t *)dst);
1376 static void init_drive(struct ide_drive * drive) {
1378 drive->sector_count = 0x01;
1379 drive->sector_num = 0x01;
1380 drive->cylinder = 0x0000;
1382 drive->drive_type = BLOCK_NONE;
1384 memset(drive->model, 0, sizeof(drive->model));
1386 drive->transfer_index = 0;
1387 drive->transfer_length = 0;
1388 memset(drive->data_buf, 0, sizeof(drive->data_buf));
1390 drive->num_cylinders = 0;
1391 drive->num_heads = 0;
1392 drive->num_sectors = 0;
1395 drive->private_data = NULL;
1399 static void init_channel(struct ide_channel * channel) {
1402 channel->error_reg.val = 0x01;
1403 channel->drive_head.val = 0x00;
1404 channel->status.val = 0x00;
1405 channel->cmd_reg = 0x00;
1406 channel->ctrl_reg.val = 0x08;
1409 channel->dma_cmd.val = 0;
1410 channel->dma_status.val = 0;
1411 channel->dma_prd_addr = 0;
1412 channel->dma_tbl_index = 0;
1414 for (i = 0; i < 2; i++) {
1415 init_drive(&(channel->drives[i]));
1421 static int pci_config_update(uint_t reg_num, void * src, uint_t length, void * private_data) {
1422 PrintDebug("PCI Config Update\n");
1424 struct ide_internal * ide = (struct ide_internal *)(private_data);
1426 PrintDebug("\t\tInterupt register (Dev=%s), irq=%d\n", ide->ide_pci->name, ide->ide_pci->config_header.intr_line);
1432 static int init_ide_state(struct ide_internal * ide) {
1436 * Check if the PIIX 3 actually represents both IDE channels in a single PCI entry
1439 for (i = 0; i < 1; i++) {
1440 init_channel(&(ide->channels[i]));
1442 // JRL: this is a terrible hack...
1443 ide->channels[i].irq = PRI_DEFAULT_IRQ + i;
1453 static int ide_free(struct ide_internal * ide) {
1455 // deregister from PCI?
1463 static struct v3_device_ops dev_ops = {
1464 .free = (int (*)(void *))ide_free,
1471 static int connect_fn(struct v3_vm_info * vm,
1472 void * frontend_data,
1473 struct v3_dev_blk_ops * ops,
1474 v3_cfg_tree_t * cfg,
1475 void * private_data) {
1476 struct ide_internal * ide = (struct ide_internal *)(frontend_data);
1477 struct ide_channel * channel = NULL;
1478 struct ide_drive * drive = NULL;
1480 char * bus_str = v3_cfg_val(cfg, "bus_num");
1481 char * drive_str = v3_cfg_val(cfg, "drive_num");
1482 char * type_str = v3_cfg_val(cfg, "type");
1483 char * model_str = v3_cfg_val(cfg, "model");
1485 uint_t drive_num = 0;
1488 if ((!type_str) || (!drive_str) || (!bus_str)) {
1489 PrintError("Incomplete IDE Configuration\n");
1493 bus_num = atoi(bus_str);
1494 drive_num = atoi(drive_str);
1496 channel = &(ide->channels[bus_num]);
1497 drive = &(channel->drives[drive_num]);
1499 if (drive->drive_type != BLOCK_NONE) {
1500 PrintError("Device slot (bus=%d, drive=%d) already occupied\n", bus_num, drive_num);
1504 strncpy(drive->model, model_str, sizeof(drive->model) - 1);
1506 if (strcasecmp(type_str, "cdrom") == 0) {
1507 drive->drive_type = BLOCK_CDROM;
1509 while (strlen((char *)(drive->model)) < 40) {
1510 strcat((char*)(drive->model), " ");
1513 } else if (strcasecmp(type_str, "hd") == 0) {
1514 drive->drive_type = BLOCK_DISK;
1516 drive->hd_state.accessed = 0;
1517 drive->hd_state.mult_sector_num = 1;
1519 drive->num_sectors = 63;
1520 drive->num_heads = 16;
1521 drive->num_cylinders = (ops->get_capacity(private_data) / HD_SECTOR_SIZE) / (drive->num_sectors * drive->num_heads);
1523 PrintError("invalid IDE drive type\n");
1530 // Hardcode this for now, but its not a good idea....
1531 ide->ide_pci->config_space[0x41 + (bus_num * 2)] = 0x80;
1534 drive->private_data = private_data;
1542 static int ide_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1543 struct ide_internal * ide = NULL;
1544 char * dev_id = v3_cfg_val(cfg, "ID");
1547 PrintDebug("IDE: Initializing IDE\n");
1549 ide = (struct ide_internal *)V3_Malloc(sizeof(struct ide_internal));
1552 PrintError("Error allocating IDE state\n");
1556 memset(ide, 0, sizeof(struct ide_internal));
1559 ide->pci_bus = v3_find_dev(vm, v3_cfg_val(cfg, "bus"));
1561 if (ide->pci_bus != NULL) {
1562 struct vm_device * southbridge = v3_find_dev(vm, v3_cfg_val(cfg, "controller"));
1565 PrintError("Could not find southbridge\n");
1570 ide->southbridge = (struct v3_southbridge *)(southbridge->private_data);
1573 PrintDebug("IDE: Creating IDE bus x 2\n");
1575 struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, ide);
1578 PrintError("Could not attach device %s\n", dev_id);
1583 if (init_ide_state(ide) == -1) {
1584 PrintError("Failed to initialize IDE state\n");
1585 v3_remove_device(dev);
1589 PrintDebug("Connecting to IDE IO ports\n");
1591 ret |= v3_dev_hook_io(dev, PRI_DATA_PORT,
1592 &ide_read_data_port, &write_data_port);
1593 ret |= v3_dev_hook_io(dev, PRI_FEATURES_PORT,
1594 &read_port_std, &write_port_std);
1595 ret |= v3_dev_hook_io(dev, PRI_SECT_CNT_PORT,
1596 &read_port_std, &write_port_std);
1597 ret |= v3_dev_hook_io(dev, PRI_SECT_NUM_PORT,
1598 &read_port_std, &write_port_std);
1599 ret |= v3_dev_hook_io(dev, PRI_CYL_LOW_PORT,
1600 &read_port_std, &write_port_std);
1601 ret |= v3_dev_hook_io(dev, PRI_CYL_HIGH_PORT,
1602 &read_port_std, &write_port_std);
1603 ret |= v3_dev_hook_io(dev, PRI_DRV_SEL_PORT,
1604 &read_port_std, &write_port_std);
1605 ret |= v3_dev_hook_io(dev, PRI_CMD_PORT,
1606 &read_port_std, &write_cmd_port);
1608 ret |= v3_dev_hook_io(dev, SEC_DATA_PORT,
1609 &ide_read_data_port, &write_data_port);
1610 ret |= v3_dev_hook_io(dev, SEC_FEATURES_PORT,
1611 &read_port_std, &write_port_std);
1612 ret |= v3_dev_hook_io(dev, SEC_SECT_CNT_PORT,
1613 &read_port_std, &write_port_std);
1614 ret |= v3_dev_hook_io(dev, SEC_SECT_NUM_PORT,
1615 &read_port_std, &write_port_std);
1616 ret |= v3_dev_hook_io(dev, SEC_CYL_LOW_PORT,
1617 &read_port_std, &write_port_std);
1618 ret |= v3_dev_hook_io(dev, SEC_CYL_HIGH_PORT,
1619 &read_port_std, &write_port_std);
1620 ret |= v3_dev_hook_io(dev, SEC_DRV_SEL_PORT,
1621 &read_port_std, &write_port_std);
1622 ret |= v3_dev_hook_io(dev, SEC_CMD_PORT,
1623 &read_port_std, &write_cmd_port);
1626 ret |= v3_dev_hook_io(dev, PRI_CTRL_PORT,
1627 &read_port_std, &write_port_std);
1629 ret |= v3_dev_hook_io(dev, SEC_CTRL_PORT,
1630 &read_port_std, &write_port_std);
1633 ret |= v3_dev_hook_io(dev, SEC_ADDR_REG_PORT,
1634 &read_port_std, &write_port_std);
1636 ret |= v3_dev_hook_io(dev, PRI_ADDR_REG_PORT,
1637 &read_port_std, &write_port_std);
1641 PrintError("Error hooking IDE IO port\n");
1642 v3_remove_device(dev);
1648 struct v3_pci_bar bars[6];
1649 struct v3_southbridge * southbridge = (struct v3_southbridge *)(ide->southbridge);
1650 struct pci_device * sb_pci = (struct pci_device *)(southbridge->southbridge_pci);
1651 struct pci_device * pci_dev = NULL;
1654 PrintDebug("Connecting IDE to PCI bus\n");
1656 for (i = 0; i < 6; i++) {
1657 bars[i].type = PCI_BAR_NONE;
1660 bars[4].type = PCI_BAR_IO;
1661 // bars[4].default_base_port = PRI_DEFAULT_DMA_PORT;
1662 bars[4].default_base_port = -1;
1663 bars[4].num_ports = 16;
1665 bars[4].io_read = read_dma_port;
1666 bars[4].io_write = write_dma_port;
1667 bars[4].private_data = ide;
1669 pci_dev = v3_pci_register_device(ide->pci_bus, PCI_STD_DEVICE, 0, sb_pci->dev_num, 1,
1671 pci_config_update, NULL, NULL, ide);
1673 if (pci_dev == NULL) {
1674 PrintError("Failed to register IDE BUS %d with PCI\n", i);
1675 v3_remove_device(dev);
1679 /* This is for CMD646 devices
1680 pci_dev->config_header.vendor_id = 0x1095;
1681 pci_dev->config_header.device_id = 0x0646;
1682 pci_dev->config_header.revision = 0x8f07;
1685 pci_dev->config_header.vendor_id = 0x8086;
1686 pci_dev->config_header.device_id = 0x7010;
1687 pci_dev->config_header.revision = 0x00;
1689 pci_dev->config_header.prog_if = 0x80; // Master IDE device
1690 pci_dev->config_header.subclass = PCI_STORAGE_SUBCLASS_IDE;
1691 pci_dev->config_header.class = PCI_CLASS_STORAGE;
1693 pci_dev->config_header.command = 0;
1694 pci_dev->config_header.status = 0x0280;
1696 ide->ide_pci = pci_dev;
1701 if (v3_dev_add_blk_frontend(vm, dev_id, connect_fn, (void *)ide) == -1) {
1702 PrintError("Could not register %s as frontend\n", dev_id);
1703 v3_remove_device(dev);
1708 PrintDebug("IDE Initialized\n");
1714 device_register("IDE", ide_init)
1719 int v3_ide_get_geometry(void * ide_data, int channel_num, int drive_num,
1720 uint32_t * cylinders, uint32_t * heads, uint32_t * sectors) {
1722 struct ide_internal * ide = ide_data;
1723 struct ide_channel * channel = &(ide->channels[channel_num]);
1724 struct ide_drive * drive = &(channel->drives[drive_num]);
1726 if (drive->drive_type == BLOCK_NONE) {
1730 *cylinders = drive->num_cylinders;
1731 *heads = drive->num_heads;
1732 *sectors = drive->num_sectors;