2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <palacios/vmm.h>
24 #include <palacios/vmm_msr.h>
27 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
28 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
30 #define APIC_FIXED_DELIVERY 0x0
31 #define APIC_SMI_DELIVERY 0x2
32 #define APIC_NMI_DELIVERY 0x4
33 #define APIC_INIT_DELIVERY 0x5
34 #define APIC_EXTINT_DELIVERY 0x7
37 #define BASE_ADDR_MSR 0x0000001B
38 #define DEFAULT_BASE_ADDR 0xfee00000
40 #define APIC_ID_OFFSET 0x020
41 #define APIC_VERSION_OFFSET 0x030
42 #define TPR_OFFSET 0x080
43 #define APR_OFFSET 0x090
44 #define PPR_OFFSET 0x0a0
45 #define EOI_OFFSET 0x0b0
46 #define REMOTE_READ_OFFSET 0x0c0
47 #define LDR_OFFSET 0x0d0
48 #define DFR_OFFSET 0x0e0
49 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
51 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
52 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
53 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
54 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
55 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
56 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
57 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
58 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
60 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
61 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
62 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
63 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
64 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
65 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
66 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
67 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
70 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
71 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
72 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
73 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
74 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
75 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
76 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
77 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
80 #define ESR_OFFSET 0x280
81 #define INT_CMD_LO_OFFSET 0x300
82 #define INT_CMD_HI_OFFSET 0x310
83 #define TMR_LOC_VEC_TBL_OFFSET 0x320
84 #define THERM_LOC_VEC_TBL_OFFSET 0x330
85 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
86 #define LINT0_VEC_TBL_OFFSET 0x350
87 #define LINT1_VEC_TBL_OFFSET 0x360
88 #define ERR_VEC_TBL_OFFSET 0x370
89 #define TMR_INIT_CNT_OFFSET 0x380
90 #define TMR_CUR_CNT_OFFSET 0x390
91 #define TMR_DIV_CFG_OFFSET 0x3e0
92 #define EXT_APIC_FEATURE_OFFSET 0x400
93 #define EXT_APIC_CMD_OFFSET 0x410
94 #define SEOI_OFFSET 0x420
96 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
97 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
98 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
99 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
100 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
101 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
102 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
103 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
105 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
106 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
107 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
108 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
117 uint_t bootstrap_cpu : 1;
119 uint_t apic_enable : 1;
120 ullong_t base_addr : 40;
122 } __attribute__((packed));
123 } __attribute__((packed));
124 } __attribute__((packed));
133 v3_msr_t base_addr_msr;
136 /* memory map registers */
138 struct lapic_id_reg lapic_id;
139 struct apic_ver_reg apic_ver;
140 struct ext_apic_ctrl_reg ext_apic_ctrl;
141 struct local_vec_tbl_reg local_vec_tbl;
142 struct tmr_vec_tbl_reg tmr_vec_tbl;
143 struct tmr_div_cfg_reg tmr_div_cfg;
144 struct lint_vec_tbl_reg lint0_vec_tbl;
145 struct lint_vec_tbl_reg lint1_vec_tbl;
146 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
147 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
148 struct err_vec_tbl_reg err_vec_tbl;
149 struct err_status_reg err_status;
150 struct spurious_int_reg spurious_int;
151 struct int_cmd_reg int_cmd;
152 struct log_dst_reg log_dst;
153 struct dst_fmt_reg dst_fmt;
154 struct arb_prio_reg arb_prio;
155 struct task_prio_reg task_prio;
156 struct proc_prio_reg proc_prio;
157 struct ext_apic_feature_reg ext_apic_feature;
158 struct spec_eoi_reg spec_eoi;
161 uint32_t tmr_cur_cnt;
162 uint32_t tmr_init_cnt;
166 uint32_t rem_rd_data;
169 uchar_t int_req_reg[32];
170 uchar_t int_svc_reg[32];
171 uchar_t int_en_reg[32];
172 uchar_t trig_mode_reg[32];
180 static void init_apic_state(struct apic_state * apic) {
181 apic->base_addr = DEFAULT_BASE_ADDR;
182 apic->base_addr_msr.value = 0x0000000000000900LL;
183 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
185 PrintDebug("Sizeof Interrupt Request Register %d, should be 32\n",
186 (uint_t)sizeof(apic->int_req_reg));
188 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
189 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
190 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
191 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
193 apic->eoi = 0x00000000;
194 apic->rem_rd_data = 0x00000000;
195 apic->tmr_init_cnt = 0x00000000;
196 apic->tmr_cur_cnt = 0x00000000;
199 // We need to figure out what the APIC ID is....
200 apic->lapic_id.val = 0x00000000;
202 // The P6 has 6 LVT entries, so we set the value to (6-1)...
203 apic->apic_ver.val = 0x80050010;
205 apic->task_prio.val = 0x00000000;
206 apic->arb_prio.val = 0x00000000;
207 apic->proc_prio.val = 0x00000000;
208 apic->log_dst.val = 0x00000000;
209 apic->dst_fmt.val = 0xffffffff;
210 apic->spurious_int.val = 0x000000ff;
211 apic->err_status.val = 0x00000000;
212 apic->int_cmd.val = 0x0000000000000000LL;
213 apic->tmr_vec_tbl.val = 0x00010000;
214 apic->therm_loc_vec_tbl.val = 0x00010000;
215 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
216 apic->lint0_vec_tbl.val = 0x00010000;
217 apic->lint1_vec_tbl.val = 0x00010000;
218 apic->err_vec_tbl.val = 0x00010000;
219 apic->tmr_div_cfg.val = 0x00000000;
220 apic->ext_apic_feature.val = 0x00040007;
221 apic->ext_apic_ctrl.val = 0x00000000;
222 apic->spec_eoi.val = 0x00000000;
228 static int read_apic_msr(uint_t msr, v3_msr_t * dst, void * priv_data) {
229 struct vm_device * dev = (struct vm_device *)priv_data;
230 struct apic_state * apic = (struct apic_state *)dev->private_data;
231 PrintDebug("READING APIC BASE ADDR: HI=%x LO=%x\n", apic->base_addr_msr.hi, apic->base_addr_msr.lo);
237 static int write_apic_msr(uint_t msr, v3_msr_t src, void * priv_data) {
238 // struct vm_device * dev = (struct vm_device *)priv_data;
239 // struct apic_state * apic = (struct apic_state *)dev->private_data;
241 PrintDebug("WRITING APIC BASE ADDR: HI=%x LO=%x\n", src.hi, src.lo);
247 // irq_num is the bit offset into a 256 bit buffer...
248 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
249 int major_offset = irq_num & ~0x00000007;
250 int minor_offset = irq_num & 0x00000007;
251 uchar_t * req_location = apic->int_req_reg + major_offset;
252 uchar_t * en_location = apic->int_en_reg + major_offset;
253 uchar_t flag = 0x1 << minor_offset;
256 PrintError("Attempting to raise an invalid interrupt: %d\n", irq_num);
260 if (*en_location & flag) {
261 *req_location |= flag;
270 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
271 uint32_t vec_num = 0;
272 uint32_t del_mode = 0;
278 vec_num = apic->tmr_vec_tbl.vec;
279 del_mode = APIC_FIXED_DELIVERY;
280 masked = apic->tmr_vec_tbl.mask;
283 vec_num = apic->therm_loc_vec_tbl.vec;
284 del_mode = apic->therm_loc_vec_tbl.msg_type;
285 masked = apic->therm_loc_vec_tbl.mask;
288 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
289 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
290 masked = apic->perf_ctr_loc_vec_tbl.mask;
293 vec_num = apic->lint0_vec_tbl.vec;
294 del_mode = apic->lint0_vec_tbl.msg_type;
295 masked = apic->lint0_vec_tbl.mask;
298 vec_num = apic->lint1_vec_tbl.vec;
299 del_mode = apic->lint1_vec_tbl.msg_type;
300 masked = apic->lint1_vec_tbl.mask;
303 vec_num = apic->err_vec_tbl.vec;
304 del_mode = APIC_FIXED_DELIVERY;
305 masked = apic->err_vec_tbl.mask;
308 PrintError("Invalid APIC interrupt type\n");
312 // interrupt is masked, don't send
317 if (del_mode == APIC_FIXED_DELIVERY) {
318 PrintDebug("Activating internal APIC IRQ\n");
319 return activate_apic_irq(apic, vec_num);
321 PrintError("Unhandled Delivery Mode\n");
327 static int apic_read(addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
328 struct vm_device * dev = (struct vm_device *)priv_data;
329 struct apic_state * apic = (struct apic_state *)dev->private_data;
330 addr_t reg_addr = guest_addr - apic->base_addr;
331 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
332 uint32_t * val_ptr = (uint32_t *)dst;
334 PrintDebug("Read apic address space (%p)\n",
337 if (msr->apic_enable == 0) {
338 PrintError("Write to APIC address space with disabled APIC\n");
344 PrintError("Invalid apic readlength\n");
350 PrintError("Attempting to read from write only register\n");
356 *val_ptr = apic->lapic_id.val;
358 case APIC_VERSION_OFFSET:
359 *val_ptr = apic->apic_ver.val;
362 *val_ptr = apic->task_prio.val;
365 *val_ptr = apic->arb_prio.val;
368 *val_ptr = apic->proc_prio.val;
370 case REMOTE_READ_OFFSET:
371 *val_ptr = apic->rem_rd_data;
374 *val_ptr = apic->log_dst.val;
377 *val_ptr = apic->dst_fmt.val;
379 case SPURIOUS_INT_VEC_OFFSET:
380 *val_ptr = apic->spurious_int.val;
383 *val_ptr = apic->err_status.val;
385 case TMR_LOC_VEC_TBL_OFFSET:
386 *val_ptr = apic->tmr_vec_tbl.val;
388 case LINT0_VEC_TBL_OFFSET:
389 *val_ptr = apic->lint0_vec_tbl.val;
391 case LINT1_VEC_TBL_OFFSET:
392 *val_ptr = apic->lint1_vec_tbl.val;
394 case ERR_VEC_TBL_OFFSET:
395 *val_ptr = apic->err_vec_tbl.val;
397 case TMR_INIT_CNT_OFFSET:
398 *val_ptr = apic->tmr_init_cnt;
400 case TMR_DIV_CFG_OFFSET:
401 *val_ptr = apic->tmr_div_cfg.val;
405 *val_ptr = *(uint32_t *)(apic->int_en_reg);
408 *val_ptr = *(uint32_t *)(apic->int_en_reg + 4);
411 *val_ptr = *(uint32_t *)(apic->int_en_reg + 8);
414 *val_ptr = *(uint32_t *)(apic->int_en_reg + 12);
417 *val_ptr = *(uint32_t *)(apic->int_en_reg + 16);
420 *val_ptr = *(uint32_t *)(apic->int_en_reg + 20);
423 *val_ptr = *(uint32_t *)(apic->int_en_reg + 24);
426 *val_ptr = *(uint32_t *)(apic->int_en_reg + 28);
430 *val_ptr = *(uint32_t *)(apic->int_svc_reg);
433 *val_ptr = *(uint32_t *)(apic->int_svc_reg + 4);
436 *val_ptr = *(uint32_t *)(apic->int_svc_reg + 8);
439 *val_ptr = *(uint32_t *)(apic->int_svc_reg + 12);
442 *val_ptr = *(uint32_t *)(apic->int_svc_reg + 16);
445 *val_ptr = *(uint32_t *)(apic->int_svc_reg + 20);
448 *val_ptr = *(uint32_t *)(apic->int_svc_reg + 24);
451 *val_ptr = *(uint32_t *)(apic->int_svc_reg + 28);
455 *val_ptr = *(uint32_t *)(apic->trig_mode_reg);
458 *val_ptr = *(uint32_t *)(apic->trig_mode_reg + 4);
461 *val_ptr = *(uint32_t *)(apic->trig_mode_reg + 8);
464 *val_ptr = *(uint32_t *)(apic->trig_mode_reg + 12);
467 *val_ptr = *(uint32_t *)(apic->trig_mode_reg + 16);
470 *val_ptr = *(uint32_t *)(apic->trig_mode_reg + 20);
473 *val_ptr = *(uint32_t *)(apic->trig_mode_reg + 24);
476 *val_ptr = *(uint32_t *)(apic->trig_mode_reg + 28);
480 *val_ptr = *(uint32_t *)(apic->int_req_reg);
483 *val_ptr = *(uint32_t *)(apic->int_req_reg + 4);
486 *val_ptr = *(uint32_t *)(apic->int_req_reg + 8);
489 *val_ptr = *(uint32_t *)(apic->int_req_reg + 12);
492 *val_ptr = *(uint32_t *)(apic->int_req_reg + 16);
495 *val_ptr = *(uint32_t *)(apic->int_req_reg + 20);
498 *val_ptr = *(uint32_t *)(apic->int_req_reg + 24);
501 *val_ptr = *(uint32_t *)(apic->int_req_reg + 28);
503 case TMR_CUR_CNT_OFFSET:
504 *val_ptr = apic->tmr_cur_cnt;
507 // We are not going to implement these....
508 case THERM_LOC_VEC_TBL_OFFSET:
509 *val_ptr = apic->therm_loc_vec_tbl.val;
511 case PERF_CTR_LOC_VEC_TBL_OFFSET:
512 *val_ptr = apic->perf_ctr_loc_vec_tbl.val;
518 case INT_CMD_LO_OFFSET:
519 *val_ptr = apic->int_cmd.lo;
521 case INT_CMD_HI_OFFSET:
522 *val_ptr = apic->int_cmd.hi;
525 // handle current timer count
527 // Unhandled Registers
528 case EXT_INT_LOC_VEC_TBL_OFFSET0:
529 case EXT_INT_LOC_VEC_TBL_OFFSET1:
530 case EXT_INT_LOC_VEC_TBL_OFFSET2:
531 case EXT_INT_LOC_VEC_TBL_OFFSET3:
532 case EXT_APIC_FEATURE_OFFSET:
533 case EXT_APIC_CMD_OFFSET:
537 PrintError("Read from Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
541 PrintDebug("Read finished (val=%x)\n", *(uint32_t *)dst);
547 static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_data) {
548 struct vm_device * dev = (struct vm_device *)priv_data;
549 struct apic_state * apic = (struct apic_state *)dev->private_data;
550 addr_t reg_addr = guest_addr - apic->base_addr;
551 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
552 uint32_t op_val = *(uint32_t *)src;
554 PrintDebug("Write to apic address space (%p) (val=%x)\n",
555 (void *)guest_addr, *(uint32_t *)src);
557 if (msr->apic_enable == 0) {
558 PrintError("Write to APIC address space with disabled APIC\n");
564 PrintError("Invalid apic write length\n");
569 case REMOTE_READ_OFFSET:
570 case APIC_VERSION_OFFSET:
597 case EXT_APIC_FEATURE_OFFSET:
598 PrintError("Attempting to write to read only register\n");
604 apic->lapic_id.val = op_val;
607 apic->task_prio.val = op_val;
610 apic->log_dst.val = op_val;
613 apic->dst_fmt.val = op_val;
615 case SPURIOUS_INT_VEC_OFFSET:
616 apic->spurious_int.val = op_val;
619 apic->err_status.val = op_val;
621 case TMR_LOC_VEC_TBL_OFFSET:
622 apic->tmr_vec_tbl.val = op_val;
624 case THERM_LOC_VEC_TBL_OFFSET:
625 apic->therm_loc_vec_tbl.val = op_val;
627 case PERF_CTR_LOC_VEC_TBL_OFFSET:
628 apic->perf_ctr_loc_vec_tbl.val = op_val;
630 case LINT0_VEC_TBL_OFFSET:
631 apic->lint0_vec_tbl.val = op_val;
633 case LINT1_VEC_TBL_OFFSET:
634 apic->lint1_vec_tbl.val = op_val;
636 case ERR_VEC_TBL_OFFSET:
637 apic->err_vec_tbl.val = op_val;
639 case TMR_INIT_CNT_OFFSET:
640 apic->tmr_init_cnt = op_val;
641 apic->tmr_cur_cnt = op_val;
643 case TMR_CUR_CNT_OFFSET:
644 apic->tmr_cur_cnt = op_val;
646 case TMR_DIV_CFG_OFFSET:
647 apic->tmr_div_cfg.val = op_val;
651 // Enable mask (256 bits)
653 *(uint32_t *)(apic->int_en_reg) = op_val;
656 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
659 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
662 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
665 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
668 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
671 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
674 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
679 case INT_CMD_LO_OFFSET:
680 case INT_CMD_HI_OFFSET:
684 // Unhandled Registers
685 case EXT_INT_LOC_VEC_TBL_OFFSET0:
686 case EXT_INT_LOC_VEC_TBL_OFFSET1:
687 case EXT_INT_LOC_VEC_TBL_OFFSET2:
688 case EXT_INT_LOC_VEC_TBL_OFFSET3:
689 case EXT_APIC_CMD_OFFSET:
692 PrintError("Write to Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
696 PrintDebug("Write finished\n");
703 /* Interrupt Controller Functions */
705 static int apic_intr_pending(void * private_data) {
706 struct vm_device * dev = (struct vm_device *)private_data;
707 struct apic_state * apic = (struct apic_state *)dev->private_data;
710 // just scan the request register looking for any set bit
711 // we should probably just do this with uint64 casts
712 for (i = 0; i < 32; i++) {
713 if (apic->int_req_reg[i] & 0xff) {
721 static int apic_get_intr_number(void * private_data) {
722 struct vm_device * dev = (struct vm_device *)private_data;
723 struct apic_state * apic = (struct apic_state *)dev->private_data;
727 // We iterate backwards to find the highest priority
728 for (i = 31; i >= 0; i--) {
729 uchar_t req_major = apic->int_req_reg[i];
731 if (req_major & 0xff) {
732 for (j = 7; j >= 0; j--) {
733 if ((req_major >> j) == 0x1) {
743 static int apic_raise_intr(void * private_data, int irq) {
744 struct vm_device * dev = (struct vm_device *)private_data;
745 struct apic_state * apic = (struct apic_state *)dev->private_data;
747 return activate_apic_irq(apic, irq);
750 static int apic_lower_intr(void * private_data, int irq) {
751 struct vm_device * dev = (struct vm_device *)private_data;
752 struct apic_state * apic = (struct apic_state *)dev->private_data;
753 int major_offset = irq & ~0x00000007;
754 int minor_offset = irq & 0x00000007;
755 uchar_t * req_location = apic->int_req_reg + major_offset;
756 uchar_t flag = 0x01 << minor_offset;
758 *req_location &= ~flag;
763 static int apic_begin_irq(void * private_data, int irq) {
764 struct vm_device * dev = (struct vm_device *)private_data;
765 struct apic_state * apic = (struct apic_state *)dev->private_data;
766 int major_offset = irq & ~0x00000007;
767 int minor_offset = irq & 0x00000007;
768 uchar_t * req_location = apic->int_req_reg + major_offset;
769 uchar_t * svc_location = apic->int_svc_reg + major_offset;
770 uchar_t flag = 0x01 << minor_offset;
772 *svc_location |= flag;
773 *req_location &= ~flag;
780 /* Timer Functions */
781 static void apic_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * priv_data) {
782 struct vm_device * dev = (struct vm_device *)priv_data;
783 struct apic_state * apic = (struct apic_state *)dev->private_data;
784 // The 32 bit GCC runtime is a pile of shit
786 uint64_t tmr_ticks = 0;
788 uint32_t tmr_ticks = 0;
791 uchar_t tmr_div = *(uchar_t *)&(apic->tmr_div_cfg.val);
792 uint_t shift_num = 0;
795 // Check whether this is true:
796 // -> If the Init count is zero then the timer is disabled
797 // and doesn't just blitz interrupts to the CPU
798 if ((apic->tmr_init_cnt == 0) ||
799 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
800 (apic->tmr_cur_cnt == 0))) {
801 //PrintDebug("APIC timer not yet initialized\n");
828 case APIC_TMR_DIV128:
832 PrintError("Invalid Timer Divider configuration\n");
836 tmr_ticks = cpu_cycles >> shift_num;
837 PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
839 if (tmr_ticks <= apic->tmr_cur_cnt) {
840 apic->tmr_cur_cnt -= tmr_ticks;
842 tmr_ticks -= apic->tmr_cur_cnt;
843 apic->tmr_cur_cnt = 0;
846 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
847 PrintError("Could not raise Timer interrupt\n");
851 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
852 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
853 apic->tmr_init_cnt = apic->tmr_init_cnt - tmr_ticks;
859 static struct intr_ctrl_ops intr_ops = {
860 .intr_pending = apic_intr_pending,
861 .get_intr_number = apic_get_intr_number,
862 .raise_intr = apic_raise_intr,
863 .begin_irq = apic_begin_irq,
864 .lower_intr = apic_lower_intr,
868 static struct vm_timer_ops timer_ops = {
869 .update_time = apic_update_time,
873 static int apic_init(struct vm_device * dev) {
874 struct guest_info * info = dev->vm;
875 struct apic_state * apic = (struct apic_state *)(dev->private_data);
877 v3_set_intr_controller(dev->vm, &intr_ops, dev);
878 v3_add_timer(dev->vm, &timer_ops, dev);
880 init_apic_state(apic);
882 v3_hook_msr(info, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, dev);
884 v3_hook_full_mem(info, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev);
889 static int apic_deinit(struct vm_device * dev) {
890 struct guest_info * info = dev->vm;
892 v3_unhook_msr(info, BASE_ADDR_MSR);
898 static struct vm_device_ops dev_ops = {
900 .deinit = apic_deinit,
907 struct vm_device * v3_create_apic() {
908 PrintDebug("Creating APIC\n");
910 struct apic_state * apic = (struct apic_state *)V3_Malloc(sizeof(struct apic_state));
912 struct vm_device * device = v3_create_device("APIC", &dev_ops, apic);