2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <devices/icc_bus.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmm_msr.h>
26 #include <palacios/vmm_sprintf.h>
27 #include <palacios/vm_guest.h>
30 #ifndef CONFIG_DEBUG_APIC
32 #define PrintDebug(fmt, args...)
36 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
37 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
39 #define APIC_FIXED_DELIVERY 0x0
40 #define APIC_SMI_DELIVERY 0x2
41 #define APIC_NMI_DELIVERY 0x4
42 #define APIC_INIT_DELIVERY 0x5
43 #define APIC_EXTINT_DELIVERY 0x7
46 #define BASE_ADDR_MSR 0x0000001B
47 #define DEFAULT_BASE_ADDR 0xfee00000
49 #define APIC_ID_OFFSET 0x020
50 #define APIC_VERSION_OFFSET 0x030
51 #define TPR_OFFSET 0x080
52 #define APR_OFFSET 0x090
53 #define PPR_OFFSET 0x0a0
54 #define EOI_OFFSET 0x0b0
55 #define REMOTE_READ_OFFSET 0x0c0
56 #define LDR_OFFSET 0x0d0
57 #define DFR_OFFSET 0x0e0
58 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
60 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
61 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
62 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
63 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
64 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
65 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
66 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
67 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
69 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
70 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
71 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
72 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
73 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
74 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
75 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
76 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
79 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
80 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
81 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
82 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
83 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
84 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
85 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
86 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
89 #define ESR_OFFSET 0x280
90 #define INT_CMD_LO_OFFSET 0x300
91 #define INT_CMD_HI_OFFSET 0x310
92 #define TMR_LOC_VEC_TBL_OFFSET 0x320
93 #define THERM_LOC_VEC_TBL_OFFSET 0x330
94 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
95 #define LINT0_VEC_TBL_OFFSET 0x350
96 #define LINT1_VEC_TBL_OFFSET 0x360
97 #define ERR_VEC_TBL_OFFSET 0x370
98 #define TMR_INIT_CNT_OFFSET 0x380
99 #define TMR_CUR_CNT_OFFSET 0x390
100 #define TMR_DIV_CFG_OFFSET 0x3e0
101 #define EXT_APIC_FEATURE_OFFSET 0x400
102 #define EXT_APIC_CMD_OFFSET 0x410
103 #define SEOI_OFFSET 0x420
105 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
106 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
107 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
108 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
109 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
110 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
111 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
112 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
114 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
115 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
116 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
117 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
126 uint_t bootstrap_cpu : 1;
128 uint_t apic_enable : 1;
129 ullong_t base_addr : 40;
131 } __attribute__((packed));
132 } __attribute__((packed));
133 } __attribute__((packed));
142 v3_msr_t base_addr_msr;
145 /* memory map registers */
147 struct lapic_id_reg lapic_id;
148 struct apic_ver_reg apic_ver;
149 struct ext_apic_ctrl_reg ext_apic_ctrl;
150 struct local_vec_tbl_reg local_vec_tbl;
151 struct tmr_vec_tbl_reg tmr_vec_tbl;
152 struct tmr_div_cfg_reg tmr_div_cfg;
153 struct lint_vec_tbl_reg lint0_vec_tbl;
154 struct lint_vec_tbl_reg lint1_vec_tbl;
155 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
156 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
157 struct err_vec_tbl_reg err_vec_tbl;
158 struct err_status_reg err_status;
159 struct spurious_int_reg spurious_int;
160 struct int_cmd_reg int_cmd;
161 struct log_dst_reg log_dst;
162 struct dst_fmt_reg dst_fmt;
163 struct arb_prio_reg arb_prio;
164 struct task_prio_reg task_prio;
165 struct proc_prio_reg proc_prio;
166 struct ext_apic_feature_reg ext_apic_feature;
167 struct spec_eoi_reg spec_eoi;
170 uint32_t tmr_cur_cnt;
171 uint32_t tmr_init_cnt;
174 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
176 uint32_t rem_rd_data;
179 uchar_t int_req_reg[32];
180 uchar_t int_svc_reg[32];
181 uchar_t int_en_reg[32];
182 uchar_t trig_mode_reg[32];
186 struct vm_device * icc_bus;
191 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
192 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
194 static void init_apic_state(struct apic_state * apic, uint32_t id) {
195 apic->base_addr = DEFAULT_BASE_ADDR;
196 apic->base_addr_msr.value = 0x0000000000000900LL;
197 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
199 PrintDebug("Sizeof Interrupt Request Register %d, should be 32\n",
200 (uint_t)sizeof(apic->int_req_reg));
202 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
203 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
204 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
205 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
207 apic->eoi = 0x00000000;
208 apic->rem_rd_data = 0x00000000;
209 apic->tmr_init_cnt = 0x00000000;
210 apic->tmr_cur_cnt = 0x00000000;
212 apic->lapic_id.val = id;
214 // The P6 has 6 LVT entries, so we set the value to (6-1)...
215 apic->apic_ver.val = 0x80050010;
217 apic->task_prio.val = 0x00000000;
218 apic->arb_prio.val = 0x00000000;
219 apic->proc_prio.val = 0x00000000;
220 apic->log_dst.val = 0x00000000;
221 apic->dst_fmt.val = 0xffffffff;
222 apic->spurious_int.val = 0x000000ff;
223 apic->err_status.val = 0x00000000;
224 apic->int_cmd.val = 0x0000000000000000LL;
225 apic->tmr_vec_tbl.val = 0x00010000;
226 apic->therm_loc_vec_tbl.val = 0x00010000;
227 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
228 apic->lint0_vec_tbl.val = 0x00010000;
229 apic->lint1_vec_tbl.val = 0x00010000;
230 apic->err_vec_tbl.val = 0x00010000;
231 apic->tmr_div_cfg.val = 0x00000000;
232 //apic->ext_apic_feature.val = 0x00000007;
233 apic->ext_apic_feature.val = 0x00040007;
234 apic->ext_apic_ctrl.val = 0x00000000;
235 apic->spec_eoi.val = 0x00000000;
237 v3_lock_init(&(apic->lock));
243 static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
244 struct vm_device * dev = (struct vm_device *)priv_data;
245 struct apic_state * apics = (struct apic_state *)(dev->private_data);
246 struct apic_state * apic = &(apics[core->cpu_id]);
249 dst->value = apic->base_addr;
250 v3_unlock(apic->lock);
255 static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
256 struct vm_device * dev = (struct vm_device *)priv_data;
257 struct apic_state * apics = (struct apic_state *)(dev->private_data);
258 struct apic_state * apic = &(apics[core->cpu_id]);
259 struct v3_mem_region * old_reg = v3_get_mem_region(dev->vm, core->cpu_id, apic->base_addr);
262 if (old_reg == NULL) {
264 PrintError("APIC Base address region does not exit...\n");
270 v3_delete_mem_region(dev->vm, old_reg);
272 apic->base_addr = src.value;
274 if (v3_hook_full_mem(dev->vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev) == -1) {
275 PrintError("Could not hook new APIC Base address\n");
276 v3_unlock(apic->lock);
280 v3_unlock(apic->lock);
285 // irq_num is the bit offset into a 256 bit buffer...
286 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
287 int major_offset = (irq_num & ~0x00000007) >> 3;
288 int minor_offset = irq_num & 0x00000007;
289 uchar_t * req_location = apic->int_req_reg + major_offset;
290 uchar_t * en_location = apic->int_en_reg + major_offset;
291 uchar_t flag = 0x1 << minor_offset;
294 PrintError("Attempting to raise an invalid interrupt: %d\n", irq_num);
298 PrintDebug("Raising APIC IRQ %d\n", irq_num);
300 if (*req_location & flag) {
301 //V3_Print("Interrupts coallescing\n");
304 if (*en_location & flag) {
305 *req_location |= flag;
307 PrintDebug("Interrupt not enabled... %.2x\n", *en_location);
316 static int get_highest_isr(struct apic_state * apic) {
319 // We iterate backwards to find the highest priority
320 for (i = 31; i >= 0; i--) {
321 uchar_t * svc_major = apic->int_svc_reg + i;
323 if ((*svc_major) & 0xff) {
324 for (j = 7; j >= 0; j--) {
325 uchar_t flag = 0x1 << j;
326 if ((*svc_major) & flag) {
327 return ((i * 8) + j);
338 static int get_highest_irr(struct apic_state * apic) {
341 // We iterate backwards to find the highest priority
342 for (i = 31; i >= 0; i--) {
343 uchar_t * req_major = apic->int_req_reg + i;
345 if ((*req_major) & 0xff) {
346 for (j = 7; j >= 0; j--) {
347 uchar_t flag = 0x1 << j;
348 if ((*req_major) & flag) {
349 return ((i * 8) + j);
361 static int apic_do_eoi(struct apic_state * apic) {
362 int isr_irq = get_highest_isr(apic);
365 int major_offset = (isr_irq & ~0x00000007) >> 3;
366 int minor_offset = isr_irq & 0x00000007;
367 uchar_t flag = 0x1 << minor_offset;
368 uchar_t * svc_location = apic->int_svc_reg + major_offset;
370 PrintDebug("Received APIC EOI for IRQ %d\n", isr_irq);
372 *svc_location &= ~flag;
374 #ifdef CONFIG_CRAY_XT
376 if ((isr_irq == 238) ||
378 PrintError("Acking IRQ %d\n", isr_irq);
381 if (isr_irq == 238) {
386 //PrintError("Spurious EOI...\n");
393 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
394 uint32_t vec_num = 0;
395 uint32_t del_mode = 0;
401 vec_num = apic->tmr_vec_tbl.vec;
402 del_mode = APIC_FIXED_DELIVERY;
403 masked = apic->tmr_vec_tbl.mask;
406 vec_num = apic->therm_loc_vec_tbl.vec;
407 del_mode = apic->therm_loc_vec_tbl.msg_type;
408 masked = apic->therm_loc_vec_tbl.mask;
411 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
412 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
413 masked = apic->perf_ctr_loc_vec_tbl.mask;
416 vec_num = apic->lint0_vec_tbl.vec;
417 del_mode = apic->lint0_vec_tbl.msg_type;
418 masked = apic->lint0_vec_tbl.mask;
421 vec_num = apic->lint1_vec_tbl.vec;
422 del_mode = apic->lint1_vec_tbl.msg_type;
423 masked = apic->lint1_vec_tbl.mask;
426 vec_num = apic->err_vec_tbl.vec;
427 del_mode = APIC_FIXED_DELIVERY;
428 masked = apic->err_vec_tbl.mask;
431 PrintError("Invalid APIC interrupt type\n");
435 // interrupt is masked, don't send
437 PrintDebug("Inerrupt is masked\n");
441 if (del_mode == APIC_FIXED_DELIVERY) {
442 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
443 return activate_apic_irq(apic, vec_num);
445 PrintError("Unhandled Delivery Mode\n");
451 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
452 struct apic_state * apic = (struct apic_state *)priv_data;
453 addr_t reg_addr = guest_addr - apic->base_addr;
454 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
458 PrintDebug("Read apic address space (%p)\n",
461 if (msr->apic_enable == 0) {
462 PrintError("Write to APIC address space with disabled APIC\n");
467 /* Because "May not be supported" doesn't matter to Linux developers... */
468 /* if (length != 4) { */
469 /* PrintError("Invalid apic read length (%d)\n", length); */
473 switch (reg_addr & ~0x3) {
475 // Well, only an idiot would read from a architectural write only register
477 // PrintError("Attempting to read from write only register\n");
483 val = apic->lapic_id.val;
485 case APIC_VERSION_OFFSET:
486 val = apic->apic_ver.val;
489 val = apic->task_prio.val;
492 val = apic->arb_prio.val;
495 val = apic->proc_prio.val;
497 case REMOTE_READ_OFFSET:
498 val = apic->rem_rd_data;
501 val = apic->log_dst.val;
504 val = apic->dst_fmt.val;
506 case SPURIOUS_INT_VEC_OFFSET:
507 val = apic->spurious_int.val;
510 val = apic->err_status.val;
512 case TMR_LOC_VEC_TBL_OFFSET:
513 val = apic->tmr_vec_tbl.val;
515 case LINT0_VEC_TBL_OFFSET:
516 val = apic->lint0_vec_tbl.val;
518 case LINT1_VEC_TBL_OFFSET:
519 val = apic->lint1_vec_tbl.val;
521 case ERR_VEC_TBL_OFFSET:
522 val = apic->err_vec_tbl.val;
524 case TMR_INIT_CNT_OFFSET:
525 val = apic->tmr_init_cnt;
527 case TMR_DIV_CFG_OFFSET:
528 val = apic->tmr_div_cfg.val;
532 val = *(uint32_t *)(apic->int_en_reg);
535 val = *(uint32_t *)(apic->int_en_reg + 4);
538 val = *(uint32_t *)(apic->int_en_reg + 8);
541 val = *(uint32_t *)(apic->int_en_reg + 12);
544 val = *(uint32_t *)(apic->int_en_reg + 16);
547 val = *(uint32_t *)(apic->int_en_reg + 20);
550 val = *(uint32_t *)(apic->int_en_reg + 24);
553 val = *(uint32_t *)(apic->int_en_reg + 28);
557 val = *(uint32_t *)(apic->int_svc_reg);
560 val = *(uint32_t *)(apic->int_svc_reg + 4);
563 val = *(uint32_t *)(apic->int_svc_reg + 8);
566 val = *(uint32_t *)(apic->int_svc_reg + 12);
569 val = *(uint32_t *)(apic->int_svc_reg + 16);
572 val = *(uint32_t *)(apic->int_svc_reg + 20);
575 val = *(uint32_t *)(apic->int_svc_reg + 24);
578 val = *(uint32_t *)(apic->int_svc_reg + 28);
582 val = *(uint32_t *)(apic->trig_mode_reg);
585 val = *(uint32_t *)(apic->trig_mode_reg + 4);
588 val = *(uint32_t *)(apic->trig_mode_reg + 8);
591 val = *(uint32_t *)(apic->trig_mode_reg + 12);
594 val = *(uint32_t *)(apic->trig_mode_reg + 16);
597 val = *(uint32_t *)(apic->trig_mode_reg + 20);
600 val = *(uint32_t *)(apic->trig_mode_reg + 24);
603 val = *(uint32_t *)(apic->trig_mode_reg + 28);
607 val = *(uint32_t *)(apic->int_req_reg);
610 val = *(uint32_t *)(apic->int_req_reg + 4);
613 val = *(uint32_t *)(apic->int_req_reg + 8);
616 val = *(uint32_t *)(apic->int_req_reg + 12);
619 val = *(uint32_t *)(apic->int_req_reg + 16);
622 val = *(uint32_t *)(apic->int_req_reg + 20);
625 val = *(uint32_t *)(apic->int_req_reg + 24);
628 val = *(uint32_t *)(apic->int_req_reg + 28);
630 case TMR_CUR_CNT_OFFSET:
631 val = apic->tmr_cur_cnt;
634 // We are not going to implement these....
635 case THERM_LOC_VEC_TBL_OFFSET:
636 val = apic->therm_loc_vec_tbl.val;
638 case PERF_CTR_LOC_VEC_TBL_OFFSET:
639 val = apic->perf_ctr_loc_vec_tbl.val;
645 case INT_CMD_LO_OFFSET:
646 val = apic->int_cmd.lo;
648 case INT_CMD_HI_OFFSET:
649 val = apic->int_cmd.hi;
652 // handle current timer count
654 // Unhandled Registers
655 case EXT_INT_LOC_VEC_TBL_OFFSET0:
656 val = apic->ext_intr_vec_tbl[0].val;
658 case EXT_INT_LOC_VEC_TBL_OFFSET1:
659 val = apic->ext_intr_vec_tbl[1].val;
661 case EXT_INT_LOC_VEC_TBL_OFFSET2:
662 val = apic->ext_intr_vec_tbl[2].val;
664 case EXT_INT_LOC_VEC_TBL_OFFSET3:
665 val = apic->ext_intr_vec_tbl[3].val;
669 case EXT_APIC_FEATURE_OFFSET:
670 case EXT_APIC_CMD_OFFSET:
674 PrintError("Read from Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
680 uint_t byte_addr = reg_addr & 0x3;
681 uint8_t * val_ptr = (uint8_t *)dst;
683 *val_ptr = *(((uint8_t *)&val) + byte_addr);
685 } else if ((length == 2) &&
686 ((reg_addr & 0x3) == 0x3)) {
687 uint_t byte_addr = reg_addr & 0x3;
688 uint16_t * val_ptr = (uint16_t *)dst;
689 *val_ptr = *(((uint16_t *)&val) + byte_addr);
691 } else if (length == 4) {
692 uint32_t * val_ptr = (uint32_t *)dst;
696 PrintError("Invalid apic read length (%d)\n", length);
700 PrintDebug("Read finished (val=%x)\n", *(uint32_t *)dst);
709 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
710 struct apic_state * apic = (struct apic_state *)priv_data;
711 addr_t reg_addr = guest_addr - apic->base_addr;
712 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
713 uint32_t op_val = *(uint32_t *)src;
715 PrintDebug("Write to apic address space (%p) (val=%x)\n",
716 (void *)guest_addr, *(uint32_t *)src);
718 if (msr->apic_enable == 0) {
719 PrintError("Write to APIC address space with disabled APIC\n");
725 PrintError("Invalid apic write length (%d)\n", length);
730 case REMOTE_READ_OFFSET:
731 case APIC_VERSION_OFFSET:
758 case EXT_APIC_FEATURE_OFFSET:
760 PrintError("Attempting to write to read only register %p (ignored)\n", (void *)reg_addr);
762 PrintError("Attempting to write to read only register %p (error)\n", (void *)reg_addr);
769 apic->lapic_id.val = op_val;
772 apic->task_prio.val = op_val;
775 apic->log_dst.val = op_val;
778 apic->dst_fmt.val = op_val;
780 case SPURIOUS_INT_VEC_OFFSET:
781 apic->spurious_int.val = op_val;
784 apic->err_status.val = op_val;
786 case TMR_LOC_VEC_TBL_OFFSET:
787 apic->tmr_vec_tbl.val = op_val;
789 case THERM_LOC_VEC_TBL_OFFSET:
790 apic->therm_loc_vec_tbl.val = op_val;
792 case PERF_CTR_LOC_VEC_TBL_OFFSET:
793 apic->perf_ctr_loc_vec_tbl.val = op_val;
795 case LINT0_VEC_TBL_OFFSET:
796 apic->lint0_vec_tbl.val = op_val;
798 case LINT1_VEC_TBL_OFFSET:
799 apic->lint1_vec_tbl.val = op_val;
801 case ERR_VEC_TBL_OFFSET:
802 apic->err_vec_tbl.val = op_val;
804 case TMR_INIT_CNT_OFFSET:
805 apic->tmr_init_cnt = op_val;
806 apic->tmr_cur_cnt = op_val;
808 case TMR_CUR_CNT_OFFSET:
809 apic->tmr_cur_cnt = op_val;
811 case TMR_DIV_CFG_OFFSET:
812 apic->tmr_div_cfg.val = op_val;
816 // Enable mask (256 bits)
818 *(uint32_t *)(apic->int_en_reg) = op_val;
821 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
824 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
827 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
830 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
833 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
836 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
839 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
842 case EXT_INT_LOC_VEC_TBL_OFFSET0:
843 apic->ext_intr_vec_tbl[0].val = op_val;
845 case EXT_INT_LOC_VEC_TBL_OFFSET1:
846 apic->ext_intr_vec_tbl[1].val = op_val;
848 case EXT_INT_LOC_VEC_TBL_OFFSET2:
849 apic->ext_intr_vec_tbl[2].val = op_val;
851 case EXT_INT_LOC_VEC_TBL_OFFSET3:
852 apic->ext_intr_vec_tbl[3].val = op_val;
862 case INT_CMD_LO_OFFSET:
863 apic->int_cmd.lo = op_val;
865 v3_icc_send_irq(apic->icc_bus, apic->int_cmd.dst, apic->int_cmd.val);
867 case INT_CMD_HI_OFFSET:
868 apic->int_cmd.hi = op_val;
870 // Unhandled Registers
872 case EXT_APIC_CMD_OFFSET:
875 PrintError("Write to Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
879 PrintDebug("Write finished\n");
886 /* Interrupt Controller Functions */
888 // returns 1 if an interrupt is pending, 0 otherwise
889 static int apic_intr_pending(struct guest_info * info, void * private_data) {
890 struct apic_state * apic = (struct apic_state *)private_data;
891 int req_irq = get_highest_irr(apic);
892 int svc_irq = get_highest_isr(apic);
894 if ((req_irq >= 0) &&
895 (req_irq > svc_irq)) {
902 static int apic_get_intr_number(struct guest_info * info, void * private_data) {
903 struct apic_state * apic = (struct apic_state *)private_data;
904 int req_irq = get_highest_irr(apic);
905 int svc_irq = get_highest_isr(apic);
909 } else if (svc_irq < req_irq) {
917 static int apic_raise_intr(struct guest_info * info, int irq, void * private_data) {
918 struct apic_state * apic = (struct apic_state *)private_data;
920 return activate_apic_irq(apic, irq);
925 static int apic_begin_irq(struct guest_info * info, void * private_data, int irq) {
926 struct apic_state * apic = (struct apic_state *)private_data;
927 int major_offset = (irq & ~0x00000007) >> 3;
928 int minor_offset = irq & 0x00000007;
929 uchar_t * req_location = apic->int_req_reg + major_offset;
930 uchar_t * svc_location = apic->int_svc_reg + major_offset;
931 uchar_t flag = 0x01 << minor_offset;
933 *svc_location |= flag;
934 *req_location &= ~flag;
944 /* Timer Functions */
945 static void apic_update_time(struct guest_info * info, ullong_t cpu_cycles, ullong_t cpu_freq, void * priv_data) {
946 struct apic_state * apic = (struct apic_state *)priv_data;
947 // The 32 bit GCC runtime is a pile of shit
949 uint64_t tmr_ticks = 0;
951 uint32_t tmr_ticks = 0;
954 uchar_t tmr_div = *(uchar_t *)&(apic->tmr_div_cfg.val);
955 uint_t shift_num = 0;
958 // Check whether this is true:
959 // -> If the Init count is zero then the timer is disabled
960 // and doesn't just blitz interrupts to the CPU
961 if ((apic->tmr_init_cnt == 0) ||
962 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
963 (apic->tmr_cur_cnt == 0))) {
964 //PrintDebug("APIC timer not yet initialized\n");
991 case APIC_TMR_DIV128:
995 PrintError("Invalid Timer Divider configuration\n");
999 tmr_ticks = cpu_cycles >> shift_num;
1000 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1002 if (tmr_ticks < apic->tmr_cur_cnt) {
1003 apic->tmr_cur_cnt -= tmr_ticks;
1005 tmr_ticks -= apic->tmr_cur_cnt;
1006 apic->tmr_cur_cnt = 0;
1009 PrintDebug("Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
1010 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1012 if (apic_intr_pending(info, priv_data)) {
1013 PrintDebug("Overriding pending IRQ %d\n", apic_get_intr_number(info, priv_data));
1016 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1017 PrintError("Could not raise Timer interrupt\n");
1020 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1021 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1022 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1030 static struct intr_ctrl_ops intr_ops = {
1031 .intr_pending = apic_intr_pending,
1032 .get_intr_number = apic_get_intr_number,
1033 .begin_irq = apic_begin_irq,
1037 static struct vm_timer_ops timer_ops = {
1038 .update_time = apic_update_time,
1044 static int apic_free(struct vm_device * dev) {
1045 // struct apic_state * apic = (struct apic_state *)dev->private_data;
1047 v3_unhook_msr(dev->vm, BASE_ADDR_MSR);
1053 static struct v3_device_ops dev_ops = {
1062 static struct v3_icc_ops icc_ops = {
1063 .raise_intr = apic_raise_intr,
1068 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1069 PrintDebug("Creating an APIC for each core\n");
1070 char * name = v3_cfg_val(cfg, "name");
1071 char * icc_name = v3_cfg_val(cfg,"bus");
1072 struct vm_device * icc = v3_find_dev(vm, icc_name);
1076 PrintError("Cannot find ICC Bus (%s)\n", icc_name);
1080 // We allocate one apic per core
1081 // APICs are accessed via index which correlates with the core's cpu_id
1082 // 0..num_cores-1 at num_cores is the ioapic (one only)
1083 struct apic_state * apic = (struct apic_state *)V3_Malloc(sizeof(struct apic_state) * vm->num_cores);
1085 struct vm_device * dev = v3_allocate_device(name, &dev_ops, apic);
1087 if (v3_attach_device(vm, dev) == -1) {
1088 PrintError("Could not attach device %s\n", name);
1093 for (i = 0; i < vm->num_cores; i++) {
1094 struct guest_info * core = &(vm->cores[i]);
1096 init_apic_state(&(apic[i]),i);
1098 v3_register_intr_controller(core, &intr_ops, &(apic[i]));
1100 v3_add_timer(core, &timer_ops, &(apic[i]));
1102 v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, &(apic[i]));
1104 v3_icc_register_apic(core, icc, i, &icc_ops, &(apic[i]));
1110 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, dev);
1117 device_register("LAPIC", apic_init)