2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Authors: Jack Lange <jarusl@cs.northwestern.edu>
15 * Peter Dinda <pdinda@northwestern.edu> (SMP)
17 * This is free software. You are permitted to use,
18 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
22 #include <devices/apic.h>
23 #include <devices/apic_regs.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmm_msr.h>
26 #include <palacios/vmm_sprintf.h>
27 #include <palacios/vm_guest.h>
28 #include <palacios/vmm_types.h>
32 // MUST DO APIC SCAN FOR PHYSICAL DELIVERY
37 #ifndef CONFIG_DEBUG_APIC
39 #define PrintDebug(fmt, args...)
42 static char * shorthand_str[] = {
49 static char * deliverymode_str[] = {
63 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
64 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
66 #define APIC_FIXED_DELIVERY 0x0
67 #define APIC_LOWEST_DELIVERY 0x1
68 #define APIC_SMI_DELIVERY 0x2
69 #define APIC_RES1_DELIVERY 0x3
70 #define APIC_NMI_DELIVERY 0x4
71 #define APIC_INIT_DELIVERY 0x5
72 #define APIC_SIPI_DELIVERY 0x6
73 #define APIC_EXTINT_DELIVERY 0x7
75 #define APIC_SHORTHAND_NONE 0x0
76 #define APIC_SHORTHAND_SELF 0x1
77 #define APIC_SHORTHAND_ALL 0x2
78 #define APIC_SHORTHAND_ALL_BUT_ME 0x3
80 #define APIC_DEST_PHYSICAL 0x0
81 #define APIC_DEST_LOGICAL 0x1
84 #define BASE_ADDR_MSR 0x0000001B
85 #define DEFAULT_BASE_ADDR 0xfee00000
87 #define APIC_ID_OFFSET 0x020
88 #define APIC_VERSION_OFFSET 0x030
89 #define TPR_OFFSET 0x080
90 #define APR_OFFSET 0x090
91 #define PPR_OFFSET 0x0a0
92 #define EOI_OFFSET 0x0b0
93 #define REMOTE_READ_OFFSET 0x0c0
94 #define LDR_OFFSET 0x0d0
95 #define DFR_OFFSET 0x0e0
96 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
98 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
99 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
100 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
101 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
102 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
103 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
104 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
105 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
107 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
108 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
109 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
110 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
111 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
112 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
113 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
114 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
117 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
118 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
119 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
120 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
121 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
122 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
123 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
124 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
127 #define ESR_OFFSET 0x280
128 #define INT_CMD_LO_OFFSET 0x300
129 #define INT_CMD_HI_OFFSET 0x310
130 #define TMR_LOC_VEC_TBL_OFFSET 0x320
131 #define THERM_LOC_VEC_TBL_OFFSET 0x330
132 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
133 #define LINT0_VEC_TBL_OFFSET 0x350
134 #define LINT1_VEC_TBL_OFFSET 0x360
135 #define ERR_VEC_TBL_OFFSET 0x370
136 #define TMR_INIT_CNT_OFFSET 0x380
137 #define TMR_CUR_CNT_OFFSET 0x390
138 #define TMR_DIV_CFG_OFFSET 0x3e0
139 #define EXT_APIC_FEATURE_OFFSET 0x400
140 #define EXT_APIC_CMD_OFFSET 0x410
141 #define SEOI_OFFSET 0x420
143 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
144 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
145 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
146 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
147 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
148 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
149 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
150 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
152 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
153 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
154 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
155 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
162 uint8_t bootstrap_cpu : 1;
164 uint8_t apic_enable : 1;
165 uint64_t base_addr : 40;
167 } __attribute__((packed));
168 } __attribute__((packed));
169 } __attribute__((packed));
173 typedef enum {INIT_ST,
175 STARTED} ipi_state_t;
177 struct apic_dev_state;
183 struct apic_msr base_addr_msr;
186 /* memory map registers */
188 struct lapic_id_reg lapic_id;
189 struct apic_ver_reg apic_ver;
190 struct ext_apic_ctrl_reg ext_apic_ctrl;
191 struct local_vec_tbl_reg local_vec_tbl;
192 struct tmr_vec_tbl_reg tmr_vec_tbl;
193 struct tmr_div_cfg_reg tmr_div_cfg;
194 struct lint_vec_tbl_reg lint0_vec_tbl;
195 struct lint_vec_tbl_reg lint1_vec_tbl;
196 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
197 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
198 struct err_vec_tbl_reg err_vec_tbl;
199 struct err_status_reg err_status;
200 struct spurious_int_reg spurious_int;
201 struct int_cmd_reg int_cmd;
202 struct log_dst_reg log_dst;
203 struct dst_fmt_reg dst_fmt;
204 struct arb_prio_reg arb_prio;
205 struct task_prio_reg task_prio;
206 struct proc_prio_reg proc_prio;
207 struct ext_apic_feature_reg ext_apic_feature;
208 struct spec_eoi_reg spec_eoi;
211 uint32_t tmr_cur_cnt;
212 uint32_t tmr_init_cnt;
215 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
217 uint32_t rem_rd_data;
220 ipi_state_t ipi_state;
222 uint8_t int_req_reg[32];
223 uint8_t int_svc_reg[32];
224 uint8_t int_en_reg[32];
225 uint8_t trig_mode_reg[32];
227 struct guest_info * core;
229 void * controller_handle;
231 struct v3_timer * timer;
241 struct apic_dev_state {
244 struct apic_state apics[0];
245 } __attribute__((packed));
251 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
252 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
255 static void init_apic_state(struct apic_state * apic, uint32_t id) {
256 apic->base_addr = DEFAULT_BASE_ADDR;
259 // boot processor, enabled
260 apic->base_addr_msr.value = 0x0000000000000900LL;
262 // ap processor, enabled
263 apic->base_addr_msr.value = 0x0000000000000800LL;
266 // same base address regardless of ap or main
267 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
269 PrintDebug("apic %u: (init_apic_state): msr=0x%llx\n",id, apic->base_addr_msr.value);
271 PrintDebug("apic %u: (init_apic_state): Sizeof Interrupt Request Register %d, should be 32\n",
272 id, (uint_t)sizeof(apic->int_req_reg));
274 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
275 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
276 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
277 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
279 apic->eoi = 0x00000000;
280 apic->rem_rd_data = 0x00000000;
281 apic->tmr_init_cnt = 0x00000000;
282 apic->tmr_cur_cnt = 0x00000000;
284 apic->lapic_id.val = id;
286 apic->ipi_state = INIT_ST;
288 // The P6 has 6 LVT entries, so we set the value to (6-1)...
289 apic->apic_ver.val = 0x80050010;
291 apic->task_prio.val = 0x00000000;
292 apic->arb_prio.val = 0x00000000;
293 apic->proc_prio.val = 0x00000000;
294 apic->log_dst.val = 0x00000000;
295 apic->dst_fmt.val = 0xffffffff;
296 apic->spurious_int.val = 0x000000ff;
297 apic->err_status.val = 0x00000000;
298 apic->int_cmd.val = 0x0000000000000000LL;
299 apic->tmr_vec_tbl.val = 0x00010000;
300 apic->therm_loc_vec_tbl.val = 0x00010000;
301 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
302 apic->lint0_vec_tbl.val = 0x00010000;
303 apic->lint1_vec_tbl.val = 0x00010000;
304 apic->err_vec_tbl.val = 0x00010000;
305 apic->tmr_div_cfg.val = 0x00000000;
306 //apic->ext_apic_feature.val = 0x00000007;
307 apic->ext_apic_feature.val = 0x00040007;
308 apic->ext_apic_ctrl.val = 0x00000000;
309 apic->spec_eoi.val = 0x00000000;
318 static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
319 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
320 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
322 PrintDebug("apic %u: core %u: MSR read\n", apic->lapic_id.val, core->cpu_id);
324 dst->value = apic->base_addr;
330 static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
331 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
332 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
333 struct v3_mem_region * old_reg = v3_get_mem_region(core->vm_info, core->cpu_id, apic->base_addr);
336 PrintDebug("apic %u: core %u: MSR write\n", apic->lapic_id.val, core->cpu_id);
338 if (old_reg == NULL) {
340 PrintError("apic %u: core %u: APIC Base address region does not exit...\n",
341 apic->lapic_id.val, core->cpu_id);
347 v3_delete_mem_region(core->vm_info, old_reg);
349 apic->base_addr = src.value;
351 if (v3_hook_full_mem(core->vm_info, core->cpu_id, apic->base_addr,
352 apic->base_addr + PAGE_SIZE_4KB,
353 apic_read, apic_write, apic_dev) == -1) {
354 PrintError("apic %u: core %u: Could not hook new APIC Base address\n",
355 apic->lapic_id.val, core->cpu_id);
365 // irq_num is the bit offset into a 256 bit buffer...
368 // 0 = OK, no interrupt needed now
369 // 1 = OK, interrupt needed now
370 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
371 int major_offset = (irq_num & ~0x00000007) >> 3;
372 int minor_offset = irq_num & 0x00000007;
373 uint8_t * req_location = apic->int_req_reg + major_offset;
374 uint8_t * en_location = apic->int_en_reg + major_offset;
375 uint8_t flag = 0x1 << minor_offset;
378 if (irq_num <= 15 || irq_num>255) {
379 PrintError("apic %u: core %d: Attempting to raise an invalid interrupt: %d\n",
380 apic->lapic_id.val, apic->core->cpu_id, irq_num);
385 PrintDebug("apic %u: core %d: Raising APIC IRQ %d\n", apic->lapic_id.val, apic->core->cpu_id, irq_num);
387 if (*req_location & flag) {
388 PrintDebug("Interrupt %d coallescing\n", irq_num);
392 if (*en_location & flag) {
393 *req_location |= flag;
396 PrintDebug("apic %u: core %d: Interrupt not enabled... %.2x\n",
397 apic->lapic_id.val, apic->core->cpu_id,*en_location);
405 static int get_highest_isr(struct apic_state * apic) {
408 // We iterate backwards to find the highest priority
409 for (i = 31; i >= 0; i--) {
410 uint8_t * svc_major = apic->int_svc_reg + i;
412 if ((*svc_major) & 0xff) {
413 for (j = 7; j >= 0; j--) {
414 uint8_t flag = 0x1 << j;
415 if ((*svc_major) & flag) {
416 return ((i * 8) + j);
427 static int get_highest_irr(struct apic_state * apic) {
430 // We iterate backwards to find the highest priority
431 for (i = 31; i >= 0; i--) {
432 uint8_t * req_major = apic->int_req_reg + i;
434 if ((*req_major) & 0xff) {
435 for (j = 7; j >= 0; j--) {
436 uint8_t flag = 0x1 << j;
437 if ((*req_major) & flag) {
438 return ((i * 8) + j);
450 static int apic_do_eoi(struct apic_state * apic) {
451 int isr_irq = get_highest_isr(apic);
454 int major_offset = (isr_irq & ~0x00000007) >> 3;
455 int minor_offset = isr_irq & 0x00000007;
456 uint8_t flag = 0x1 << minor_offset;
457 uint8_t * svc_location = apic->int_svc_reg + major_offset;
459 PrintDebug("apic %u: core ?: Received APIC EOI for IRQ %d\n", apic->lapic_id.val,isr_irq);
461 *svc_location &= ~flag;
463 #ifdef CONFIG_CRAY_XT
465 if ((isr_irq == 238) ||
467 PrintDebug("apic %u: core ?: Acking IRQ %d\n", apic->lapic_id.val,isr_irq);
470 if (isr_irq == 238) {
475 //PrintError("apic %u: core ?: Spurious EOI...\n",apic->lapic_id.val);
482 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
483 uint32_t vec_num = 0;
484 uint32_t del_mode = 0;
490 vec_num = apic->tmr_vec_tbl.vec;
491 del_mode = APIC_FIXED_DELIVERY;
492 masked = apic->tmr_vec_tbl.mask;
495 vec_num = apic->therm_loc_vec_tbl.vec;
496 del_mode = apic->therm_loc_vec_tbl.msg_type;
497 masked = apic->therm_loc_vec_tbl.mask;
500 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
501 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
502 masked = apic->perf_ctr_loc_vec_tbl.mask;
505 vec_num = apic->lint0_vec_tbl.vec;
506 del_mode = apic->lint0_vec_tbl.msg_type;
507 masked = apic->lint0_vec_tbl.mask;
510 vec_num = apic->lint1_vec_tbl.vec;
511 del_mode = apic->lint1_vec_tbl.msg_type;
512 masked = apic->lint1_vec_tbl.mask;
515 vec_num = apic->err_vec_tbl.vec;
516 del_mode = APIC_FIXED_DELIVERY;
517 masked = apic->err_vec_tbl.mask;
520 PrintError("apic %u: core ?: Invalid APIC interrupt type\n", apic->lapic_id.val);
524 // interrupt is masked, don't send
526 PrintDebug("apic %u: core ?: Inerrupt is masked\n", apic->lapic_id.val);
530 if (del_mode == APIC_FIXED_DELIVERY) {
531 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
532 return activate_apic_irq(apic, vec_num);
534 PrintError("apic %u: core ?: Unhandled Delivery Mode\n", apic->lapic_id.val);
541 static inline int should_deliver_cluster_ipi(struct guest_info * dst_core,
542 struct apic_state * dst_apic, uint8_t mda) {
544 if ( ((mda & 0xf0) == (dst_apic->log_dst.dst_log_id & 0xf0)) && /* (I am in the cluster and */
545 ((mda & 0x0f) & (dst_apic->log_dst.dst_log_id & 0x0f)) ) { /* I am in the set) */
547 PrintDebug("apic %u core %u: accepting clustered IRQ (mda 0x%x == log_dst 0x%x)\n",
548 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
549 dst_apic->log_dst.dst_log_id);
553 PrintDebug("apic %u core %u: rejecting clustered IRQ (mda 0x%x != log_dst 0x%x)\n",
554 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
555 dst_apic->log_dst.dst_log_id);
560 static inline int should_deliver_flat_ipi(struct guest_info * dst_core,
561 struct apic_state * dst_apic, uint8_t mda) {
563 if (dst_apic->log_dst.dst_log_id & mda) { // I am in the set
565 PrintDebug("apic %u core %u: accepting flat IRQ (mda 0x%x == log_dst 0x%x)\n",
566 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
567 dst_apic->log_dst.dst_log_id);
573 PrintDebug("apic %u core %u: rejecting flat IRQ (mda 0x%x != log_dst 0x%x)\n",
574 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
575 dst_apic->log_dst.dst_log_id);
582 static int should_deliver_ipi(struct guest_info * dst_core,
583 struct apic_state * dst_apic, uint8_t mda) {
586 if (dst_apic->dst_fmt.model == 0xf) {
589 /* always deliver broadcast */
593 return should_deliver_flat_ipi(dst_core, dst_apic, mda);
595 } else if (dst_apic->dst_fmt.model == 0x0) {
598 /* always deliver broadcast */
602 return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
605 PrintError("apic %u core %u: invalid destination format register value 0x%x for logical mode delivery.\n",
606 dst_apic->lapic_id.val, dst_core->cpu_id, dst_apic->dst_fmt.model);
612 // Only the src_apic pointer is used
613 static int deliver_ipi(struct apic_state * src_apic,
614 struct apic_state * dst_apic,
615 uint32_t vector, uint8_t del_mode) {
618 struct guest_info * dst_core = dst_apic->core;
623 case APIC_FIXED_DELIVERY:
624 case APIC_LOWEST_DELIVERY: {
626 // caller needs to have decided which apic to deliver to!
630 PrintDebug("delivering IRQ %d to core %u\n", vector, dst_core->cpu_id);
632 do_xcall = activate_apic_irq(dst_apic, vector);
635 PrintError("Failed to activate apic irq!\n");
639 if (do_xcall && (dst_apic != src_apic)) {
640 // Assume core # is same as logical processor for now
641 // TODO FIX THIS FIX THIS
642 // THERE SHOULD BE: guestapicid->virtualapicid map,
643 // cpu_id->logical processor map
644 // host maitains logical proc->phsysical proc
645 PrintDebug(" non-local core with new interrupt, forcing it to exit now\n");
647 #ifdef CONFIG_MULTITHREAD_OS
648 v3_interrupt_cpu(dst_core->vm_info, dst_core->cpu_id, 0);
656 case APIC_INIT_DELIVERY: {
658 PrintDebug(" INIT delivery to core %u\n", dst_core->cpu_id);
660 // TODO: any APIC reset on dest core (shouldn't be needed, but not sure...)
663 if (dst_apic->ipi_state != INIT_ST) {
664 PrintError(" Warning: core %u is not in INIT state (mode = %d), ignored (assuming this is the deassert)\n",
665 dst_core->cpu_id, dst_apic->ipi_state);
666 // Only a warning, since INIT INIT SIPI is common
670 // We transition the target core to SIPI state
671 dst_apic->ipi_state = SIPI; // note: locking should not be needed here
673 // That should be it since the target core should be
674 // waiting in host on this transition
675 // either it's on another core or on a different preemptive thread
676 // in both cases, it will quickly notice this transition
677 // in particular, we should not need to force an exit here
679 PrintDebug(" INIT delivery done\n");
683 case APIC_SIPI_DELIVERY: {
686 if (dst_apic->ipi_state != SIPI) {
687 PrintError(" core %u is not in SIPI state (mode = %d), ignored!\n",
688 dst_core->cpu_id, dst_apic->ipi_state);
692 // Write the RIP, CS, and descriptor
693 // assume the rest is already good to go
695 // vector VV -> rip at 0
697 // This means we start executing at linear address VV000
699 // So the selector needs to be VV00
700 // and the base needs to be VV000
703 dst_core->segments.cs.selector = vector << 8;
704 dst_core->segments.cs.limit = 0xffff;
705 dst_core->segments.cs.base = vector << 12;
707 PrintDebug(" SIPI delivery (0x%x -> 0x%x:0x0) to core %u\n",
708 vector, dst_core->segments.cs.selector, dst_core->cpu_id);
709 // Maybe need to adjust the APIC?
711 // We transition the target core to SIPI state
712 dst_core->core_run_state = CORE_RUNNING; // note: locking should not be needed here
713 dst_apic->ipi_state = STARTED;
715 // As with INIT, we should not need to do anything else
717 PrintDebug(" SIPI delivery done\n");
721 case APIC_SMI_DELIVERY:
722 case APIC_RES1_DELIVERY: // reserved
723 case APIC_NMI_DELIVERY:
724 case APIC_EXTINT_DELIVERY: // ExtInt
726 PrintError("IPI %d delivery is unsupported\n", del_mode);
735 static int route_ipi(struct apic_dev_state * apic_dev,
736 struct apic_state * src_apic,
737 struct int_cmd_reg * icr) {
738 struct apic_state * dest_apic = NULL;
741 PrintDebug("apic: IPI %s %u from apic %p to %s %s %u (icr=0x%llx)\n",
742 deliverymode_str[icr->del_mode],
745 (icr->dst_mode == 0) ? "(physical)" : "(logical)",
746 shorthand_str[icr->dst_shorthand],
750 switch (icr->dst_shorthand) {
752 case APIC_SHORTHAND_NONE: // no shorthand
753 if (icr->dst_mode == APIC_DEST_PHYSICAL) {
755 if (icr->dst >= apic_dev->num_apics) {
756 PrintError("apic: Attempted send to unregistered apic id=%u\n", icr->dst);
760 dest_apic = &(apic_dev->apics[icr->dst]);
762 V3_Print("apic: phsyical destination of %u (apic %u at 0x%p)\n", icr->dst,dest_apic->lapic_id.val,dest_apic);
764 if (deliver_ipi(src_apic, dest_apic,
765 icr->vec, icr->del_mode) == -1) {
766 PrintError("apic: Could not deliver IPI\n");
770 V3_Print("apic: done\n");
772 } else if (icr->dst_mode == APIC_DEST_LOGICAL) {
774 if (icr->del_mode!=APIC_LOWEST_DELIVERY ) {
775 // logical, but not lowest priority
776 // we immediately trigger
777 // fixed, smi, reserved, nmi, init, sipi, etc
780 uint8_t mda = icr->dst;
782 for (i = 0; i < apic_dev->num_apics; i++) {
784 dest_apic = &(apic_dev->apics[i]);
786 int del_flag = should_deliver_ipi(dest_apic->core, dest_apic, mda);
788 if (del_flag == -1) {
789 PrintError("apic: Error checking delivery mode\n");
791 } else if (del_flag == 1) {
792 if (deliver_ipi(src_apic, dest_apic,
793 icr->vec, icr->del_mode) == -1) {
794 PrintError("apic: Error: Could not deliver IPI\n");
799 } else { //APIC_LOWEST_DELIVERY
800 // logical, lowest priority
802 struct apic_state * cur_best_apic = NULL;
803 uint8_t mda = icr->dst;
805 for (i = 0; i < apic_dev->num_apics; i++) {
808 dest_apic = &(apic_dev->apics[i]);
810 del_flag = should_deliver_ipi(dest_apic->core, dest_apic, mda);
812 if (del_flag == -1) {
813 PrintError("apic: Error checking delivery mode\n");
816 } else if (del_flag == 1) {
817 // update priority for lowest priority scan
818 if (!cur_best_apic) {
819 cur_best_apic = dest_apic;
820 } else if (dest_apic->task_prio.val < cur_best_apic->task_prio.val) {
821 cur_best_apic = dest_apic;
826 // now we will deliver to the best one if it exists
827 if (!cur_best_apic) {
828 PrintDebug("apic: lowest priority deliver, but no destinations!\n");
830 if (deliver_ipi(src_apic, cur_best_apic,
831 icr->vec, icr->del_mode) == -1) {
832 PrintError("apic: Error: Could not deliver IPI\n");
835 //V3_Print("apic: logical, lowest priority delivery to apic %u\n",cur_best_apic->lapic_id.val);
842 case APIC_SHORTHAND_SELF: // self
844 if (src_apic == NULL) { /* this is not an apic, but it's trying to send to itself??? */
845 PrintError("apic: Sending IPI to self from generic IPI sender\n");
851 if (icr->dst_mode == APIC_DEST_PHYSICAL) { /* physical delivery */
852 if (deliver_ipi(src_apic, src_apic, icr->vec, icr->del_mode) == -1) {
853 PrintError("apic: Could not deliver IPI to self (physical)\n");
856 } else if (icr->dst_mode == APIC_DEST_LOGICAL) { /* logical delivery */
857 PrintError("apic: use of logical delivery in self (untested)\n");
858 if (deliver_ipi(src_apic, src_apic, icr->vec, icr->del_mode) == -1) {
859 PrintError("apic: Could not deliver IPI to self (logical)\n");
866 case APIC_SHORTHAND_ALL:
867 case APIC_SHORTHAND_ALL_BUT_ME: { /* all and all-but-me */
868 /* assuming that logical verus physical doesn't matter
869 although it is odd that both are used */
872 for (i = 0; i < apic_dev->num_apics; i++) {
873 dest_apic = &(apic_dev->apics[i]);
875 if ((dest_apic != src_apic) || (icr->dst_shorthand == APIC_SHORTHAND_ALL)) {
876 if (deliver_ipi(src_apic, dest_apic, icr->vec, icr->del_mode) == -1) {
877 PrintError("apic: Error: Could not deliver IPI\n");
886 PrintError("apic: Error routing IPI, invalid Mode (%d)\n", icr->dst_shorthand);
894 // External function, expected to acquire lock on apic
895 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
896 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
897 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
898 addr_t reg_addr = guest_addr - apic->base_addr;
899 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
903 PrintDebug("apic %u: core %u: at %p: Read apic address space (%p)\n",
904 apic->lapic_id.val, core->cpu_id, apic, (void *)guest_addr);
906 if (msr->apic_enable == 0) {
907 PrintError("apic %u: core %u: Read from APIC address space with disabled APIC, apic msr=0x%llx\n",
908 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
913 /* Because "May not be supported" doesn't matter to Linux developers... */
914 /* if (length != 4) { */
915 /* PrintError("Invalid apic read length (%d)\n", length); */
919 switch (reg_addr & ~0x3) {
921 // Well, only an idiot would read from a architectural write only register
923 // PrintError("Attempting to read from write only register\n");
929 val = apic->lapic_id.val;
931 case APIC_VERSION_OFFSET:
932 val = apic->apic_ver.val;
935 val = apic->task_prio.val;
938 val = apic->arb_prio.val;
941 val = apic->proc_prio.val;
943 case REMOTE_READ_OFFSET:
944 val = apic->rem_rd_data;
947 val = apic->log_dst.val;
950 val = apic->dst_fmt.val;
952 case SPURIOUS_INT_VEC_OFFSET:
953 val = apic->spurious_int.val;
956 val = apic->err_status.val;
958 case TMR_LOC_VEC_TBL_OFFSET:
959 val = apic->tmr_vec_tbl.val;
961 case LINT0_VEC_TBL_OFFSET:
962 val = apic->lint0_vec_tbl.val;
964 case LINT1_VEC_TBL_OFFSET:
965 val = apic->lint1_vec_tbl.val;
967 case ERR_VEC_TBL_OFFSET:
968 val = apic->err_vec_tbl.val;
970 case TMR_INIT_CNT_OFFSET:
971 val = apic->tmr_init_cnt;
973 case TMR_DIV_CFG_OFFSET:
974 val = apic->tmr_div_cfg.val;
978 val = *(uint32_t *)(apic->int_en_reg);
981 val = *(uint32_t *)(apic->int_en_reg + 4);
984 val = *(uint32_t *)(apic->int_en_reg + 8);
987 val = *(uint32_t *)(apic->int_en_reg + 12);
990 val = *(uint32_t *)(apic->int_en_reg + 16);
993 val = *(uint32_t *)(apic->int_en_reg + 20);
996 val = *(uint32_t *)(apic->int_en_reg + 24);
999 val = *(uint32_t *)(apic->int_en_reg + 28);
1003 val = *(uint32_t *)(apic->int_svc_reg);
1006 val = *(uint32_t *)(apic->int_svc_reg + 4);
1009 val = *(uint32_t *)(apic->int_svc_reg + 8);
1012 val = *(uint32_t *)(apic->int_svc_reg + 12);
1015 val = *(uint32_t *)(apic->int_svc_reg + 16);
1018 val = *(uint32_t *)(apic->int_svc_reg + 20);
1021 val = *(uint32_t *)(apic->int_svc_reg + 24);
1024 val = *(uint32_t *)(apic->int_svc_reg + 28);
1028 val = *(uint32_t *)(apic->trig_mode_reg);
1031 val = *(uint32_t *)(apic->trig_mode_reg + 4);
1034 val = *(uint32_t *)(apic->trig_mode_reg + 8);
1037 val = *(uint32_t *)(apic->trig_mode_reg + 12);
1040 val = *(uint32_t *)(apic->trig_mode_reg + 16);
1043 val = *(uint32_t *)(apic->trig_mode_reg + 20);
1046 val = *(uint32_t *)(apic->trig_mode_reg + 24);
1049 val = *(uint32_t *)(apic->trig_mode_reg + 28);
1053 val = *(uint32_t *)(apic->int_req_reg);
1056 val = *(uint32_t *)(apic->int_req_reg + 4);
1059 val = *(uint32_t *)(apic->int_req_reg + 8);
1062 val = *(uint32_t *)(apic->int_req_reg + 12);
1065 val = *(uint32_t *)(apic->int_req_reg + 16);
1068 val = *(uint32_t *)(apic->int_req_reg + 20);
1071 val = *(uint32_t *)(apic->int_req_reg + 24);
1074 val = *(uint32_t *)(apic->int_req_reg + 28);
1076 case TMR_CUR_CNT_OFFSET:
1077 val = apic->tmr_cur_cnt;
1080 // We are not going to implement these....
1081 case THERM_LOC_VEC_TBL_OFFSET:
1082 val = apic->therm_loc_vec_tbl.val;
1084 case PERF_CTR_LOC_VEC_TBL_OFFSET:
1085 val = apic->perf_ctr_loc_vec_tbl.val;
1090 // handled registers
1091 case INT_CMD_LO_OFFSET:
1092 val = apic->int_cmd.lo;
1094 case INT_CMD_HI_OFFSET:
1095 val = apic->int_cmd.hi;
1098 // handle current timer count
1100 // Unhandled Registers
1101 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1102 val = apic->ext_intr_vec_tbl[0].val;
1104 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1105 val = apic->ext_intr_vec_tbl[1].val;
1107 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1108 val = apic->ext_intr_vec_tbl[2].val;
1110 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1111 val = apic->ext_intr_vec_tbl[3].val;
1115 case EXT_APIC_FEATURE_OFFSET:
1116 case EXT_APIC_CMD_OFFSET:
1120 PrintError("apic %u: core %u: Read from Unhandled APIC Register: %x (getting zero)\n",
1121 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1127 uint_t byte_addr = reg_addr & 0x3;
1128 uint8_t * val_ptr = (uint8_t *)dst;
1130 *val_ptr = *(((uint8_t *)&val) + byte_addr);
1132 } else if ((length == 2) &&
1133 ((reg_addr & 0x3) == 0x3)) {
1134 uint_t byte_addr = reg_addr & 0x3;
1135 uint16_t * val_ptr = (uint16_t *)dst;
1136 *val_ptr = *(((uint16_t *)&val) + byte_addr);
1138 } else if (length == 4) {
1139 uint32_t * val_ptr = (uint32_t *)dst;
1143 PrintError("apic %u: core %u: Invalid apic read length (%d)\n",
1144 apic->lapic_id.val, core->cpu_id, length);
1148 PrintDebug("apic %u: core %u: Read finished (val=%x)\n",
1149 apic->lapic_id.val, core->cpu_id, *(uint32_t *)dst);
1158 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
1159 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1160 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1161 addr_t reg_addr = guest_addr - apic->base_addr;
1162 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
1163 uint32_t op_val = *(uint32_t *)src;
1165 PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
1166 apic->lapic_id.val, core->cpu_id, apic, priv_data);
1168 PrintDebug("apic %u: core %u: write to address space (%p) (val=%x)\n",
1169 apic->lapic_id.val, core->cpu_id, (void *)guest_addr, *(uint32_t *)src);
1171 if (msr->apic_enable == 0) {
1172 PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
1173 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
1179 PrintError("apic %u: core %u: Invalid apic write length (%d)\n",
1180 apic->lapic_id.val, length, core->cpu_id);
1185 case REMOTE_READ_OFFSET:
1186 case APIC_VERSION_OFFSET:
1213 case EXT_APIC_FEATURE_OFFSET:
1215 PrintError("apic %u: core %u: Attempting to write to read only register %p (error)\n",
1216 apic->lapic_id.val, core->cpu_id, (void *)reg_addr);
1221 case APIC_ID_OFFSET:
1222 V3_Print("apic %u: core %u: my id is being changed to %u\n",
1223 apic->lapic_id.val, core->cpu_id, op_val);
1225 apic->lapic_id.val = op_val;
1228 apic->task_prio.val = op_val;
1231 PrintDebug("apic %u: core %u: setting log_dst.val to 0x%x\n",
1232 apic->lapic_id.val, core->cpu_id, op_val);
1233 apic->log_dst.val = op_val;
1236 apic->dst_fmt.val = op_val;
1238 case SPURIOUS_INT_VEC_OFFSET:
1239 apic->spurious_int.val = op_val;
1242 apic->err_status.val = op_val;
1244 case TMR_LOC_VEC_TBL_OFFSET:
1245 apic->tmr_vec_tbl.val = op_val;
1247 case THERM_LOC_VEC_TBL_OFFSET:
1248 apic->therm_loc_vec_tbl.val = op_val;
1250 case PERF_CTR_LOC_VEC_TBL_OFFSET:
1251 apic->perf_ctr_loc_vec_tbl.val = op_val;
1253 case LINT0_VEC_TBL_OFFSET:
1254 apic->lint0_vec_tbl.val = op_val;
1256 case LINT1_VEC_TBL_OFFSET:
1257 apic->lint1_vec_tbl.val = op_val;
1259 case ERR_VEC_TBL_OFFSET:
1260 apic->err_vec_tbl.val = op_val;
1262 case TMR_INIT_CNT_OFFSET:
1263 apic->tmr_init_cnt = op_val;
1264 apic->tmr_cur_cnt = op_val;
1266 case TMR_CUR_CNT_OFFSET:
1267 apic->tmr_cur_cnt = op_val;
1269 case TMR_DIV_CFG_OFFSET:
1270 apic->tmr_div_cfg.val = op_val;
1274 // Enable mask (256 bits)
1276 *(uint32_t *)(apic->int_en_reg) = op_val;
1279 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
1282 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
1285 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
1288 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
1291 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
1294 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
1297 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
1300 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1301 apic->ext_intr_vec_tbl[0].val = op_val;
1303 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1304 apic->ext_intr_vec_tbl[1].val = op_val;
1306 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1307 apic->ext_intr_vec_tbl[2].val = op_val;
1309 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1310 apic->ext_intr_vec_tbl[3].val = op_val;
1320 case INT_CMD_LO_OFFSET: {
1323 struct int_cmd_reg tmp_icr;
1325 apic->int_cmd.lo = op_val;
1327 tmp_icr = apic->int_cmd;
1329 // V3_Print("apic %u: core %u: sending cmd 0x%llx to apic %u\n",
1330 // apic->lapic_id.val, core->cpu_id,
1331 // apic->int_cmd.val, apic->int_cmd.dst);
1333 if (route_ipi(apic_dev, apic, &tmp_icr) == -1) {
1334 PrintError("IPI Routing failure\n");
1339 case INT_CMD_HI_OFFSET: {
1340 apic->int_cmd.hi = op_val;
1341 V3_Print("apic %u: core %u: writing command high=0x%x\n", apic->lapic_id.val, core->cpu_id,apic->int_cmd.hi);
1345 // Unhandled Registers
1346 case EXT_APIC_CMD_OFFSET:
1349 PrintError("apic %u: core %u: Write to Unhandled APIC Register: %x (ignored)\n",
1350 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1355 PrintDebug("apic %u: core %u: Write finished\n", apic->lapic_id.val, core->cpu_id);
1363 /* Interrupt Controller Functions */
1366 static int apic_intr_pending(struct guest_info * core, void * private_data) {
1367 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1368 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1369 int req_irq = get_highest_irr(apic);
1370 int svc_irq = get_highest_isr(apic);
1372 // PrintDebug("apic %u: core %u: req_irq=%d, svc_irq=%d\n",apic->lapic_id.val,info->cpu_id,req_irq,svc_irq);
1374 if ((req_irq >= 0) &&
1375 (req_irq > svc_irq)) {
1384 static int apic_get_intr_number(struct guest_info * core, void * private_data) {
1385 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1386 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1387 int req_irq = get_highest_irr(apic);
1388 int svc_irq = get_highest_isr(apic);
1390 if (svc_irq == -1) {
1392 } else if (svc_irq < req_irq) {
1401 int v3_apic_send_ipi(struct v3_vm_info * vm, struct v3_gen_ipi * ipi, void * dev_data) {
1402 struct apic_dev_state * apic_dev = (struct apic_dev_state *)
1403 (((struct vm_device *)dev_data)->private_data);
1404 struct int_cmd_reg tmp_icr;
1406 // zero out all the fields
1409 tmp_icr.vec = ipi->vector;
1410 tmp_icr.del_mode = ipi->mode;
1411 tmp_icr.dst_mode = ipi->logical;
1412 tmp_icr.trig_mode = ipi->trigger_mode;
1413 tmp_icr.dst_shorthand = ipi->dst_shorthand;
1414 tmp_icr.dst = ipi->dst;
1417 return route_ipi(apic_dev, NULL, &tmp_icr);
1421 int v3_apic_raise_intr(struct v3_vm_info * vm, uint32_t irq, uint32_t dst, void * dev_data) {
1422 struct apic_dev_state * apic_dev = (struct apic_dev_state *)
1423 (((struct vm_device*)dev_data)->private_data);
1424 struct apic_state * apic = &(apic_dev->apics[dst]);
1427 PrintDebug("apic %u core ?: raising interrupt IRQ %u (dst = %u).\n", apic->lapic_id.val, irq, dst);
1429 do_xcall = activate_apic_irq(apic, irq);
1432 PrintError("Failed to activate apic irq\n");
1436 if (do_xcall > 0 && (V3_Get_CPU() != dst)) {
1437 #ifdef CONFIG_MULTITHREAD_OS
1438 v3_interrupt_cpu(vm, dst, 0);
1450 static int apic_begin_irq(struct guest_info * core, void * private_data, int irq) {
1451 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1452 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1453 int major_offset = (irq & ~0x00000007) >> 3;
1454 int minor_offset = irq & 0x00000007;
1455 uint8_t *req_location = apic->int_req_reg + major_offset;
1456 uint8_t *svc_location = apic->int_svc_reg + major_offset;
1457 uint8_t flag = 0x01 << minor_offset;
1459 if (*req_location & flag) {
1460 // we will only pay attention to a begin irq if we
1461 // know that we initiated it!
1462 *svc_location |= flag;
1463 *req_location &= ~flag;
1466 //PrintDebug("apic %u: core %u: begin irq for %d ignored since I don't own it\n",
1467 // apic->lapic_id.val, core->cpu_id, irq);
1477 /* Timer Functions */
1479 static void apic_update_time(struct guest_info * core,
1480 uint64_t cpu_cycles, uint64_t cpu_freq,
1482 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1483 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1485 // The 32 bit GCC runtime is a pile of shit
1487 uint64_t tmr_ticks = 0;
1489 uint32_t tmr_ticks = 0;
1492 uint8_t tmr_div = *(uint8_t *)&(apic->tmr_div_cfg.val);
1493 uint_t shift_num = 0;
1496 // Check whether this is true:
1497 // -> If the Init count is zero then the timer is disabled
1498 // and doesn't just blitz interrupts to the CPU
1499 if ((apic->tmr_init_cnt == 0) ||
1500 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
1501 (apic->tmr_cur_cnt == 0))) {
1502 //PrintDebug("apic %u: core %u: APIC timer not yet initialized\n",apic->lapic_id.val,info->cpu_id);
1520 case APIC_TMR_DIV16:
1523 case APIC_TMR_DIV32:
1526 case APIC_TMR_DIV64:
1529 case APIC_TMR_DIV128:
1533 PrintError("apic %u: core %u: Invalid Timer Divider configuration\n",
1534 apic->lapic_id.val, core->cpu_id);
1538 tmr_ticks = cpu_cycles >> shift_num;
1539 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1541 if (tmr_ticks < apic->tmr_cur_cnt) {
1542 apic->tmr_cur_cnt -= tmr_ticks;
1544 tmr_ticks -= apic->tmr_cur_cnt;
1545 apic->tmr_cur_cnt = 0;
1548 PrintDebug("apic %u: core %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
1549 apic->lapic_id.val, core->cpu_id,
1550 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1552 if (apic_intr_pending(core, priv_data)) {
1553 PrintDebug("apic %u: core %u: Overriding pending IRQ %d\n",
1554 apic->lapic_id.val, core->cpu_id,
1555 apic_get_intr_number(core, priv_data));
1558 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1559 PrintError("apic %u: core %u: Could not raise Timer interrupt\n",
1560 apic->lapic_id.val, core->cpu_id);
1563 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1564 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1565 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1573 static struct intr_ctrl_ops intr_ops = {
1574 .intr_pending = apic_intr_pending,
1575 .get_intr_number = apic_get_intr_number,
1576 .begin_irq = apic_begin_irq,
1580 static struct v3_timer_ops timer_ops = {
1581 .update_timer = apic_update_time,
1587 static int apic_free(struct apic_dev_state * apic_dev) {
1589 struct v3_vm_info * vm = NULL;
1591 for (i = 0; i < apic_dev->num_apics; i++) {
1592 struct apic_state * apic = &(apic_dev->apics[i]);
1593 struct guest_info * core = apic->core;
1597 v3_remove_intr_controller(core, apic->controller_handle);
1600 v3_remove_timer(core, apic->timer);
1607 v3_unhook_msr(vm, BASE_ADDR_MSR);
1614 static struct v3_device_ops dev_ops = {
1615 .free = (int (*)(void *))apic_free,
1620 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1621 char * dev_id = v3_cfg_val(cfg, "ID");
1622 struct apic_dev_state * apic_dev = NULL;
1625 PrintDebug("apic: creating an APIC for each core\n");
1627 apic_dev = (struct apic_dev_state *)V3_Malloc(sizeof(struct apic_dev_state) +
1628 sizeof(struct apic_state) * vm->num_cores);
1630 apic_dev->num_apics = vm->num_cores;
1632 struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, apic_dev);
1635 PrintError("apic: Could not attach device %s\n", dev_id);
1641 for (i = 0; i < vm->num_cores; i++) {
1642 struct apic_state * apic = &(apic_dev->apics[i]);
1643 struct guest_info * core = &(vm->cores[i]);
1647 init_apic_state(apic, i);
1649 apic->controller_handle = v3_register_intr_controller(core, &intr_ops, apic_dev);
1651 apic->timer = v3_add_timer(core, &timer_ops, apic_dev);
1653 if (apic->timer == NULL) {
1654 PrintError("APIC: Failed to attach timer to core %d\n", i);
1655 v3_remove_device(dev);
1659 v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev);
1661 PrintDebug("apic %u: (setup device): done, my id is %u\n", i, apic->lapic_id.val);
1664 #ifdef CONFIG_DEBUG_APIC
1665 for (i = 0; i < vm->num_cores; i++) {
1666 struct apic_state * apic = &(apic_dev->apics[i]);
1667 PrintDebug("apic: sanity check: apic %u (at %p) has id %u and msr value %llx and core at %p\n",
1668 i, apic, apic->lapic_id.val, apic->base_addr_msr.value,apic->core);
1673 PrintDebug("apic: priv_data is at %p\n", apic_dev);
1675 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, apic_dev);
1682 device_register("LAPIC", apic_init)