2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <palacios/vmm.h>
24 #include <palacios/vmm_msr.h>
25 #include <palacios/vmm_sprintf.h>
26 #include <palacios/vm_guest.h>
27 #include <palacios/vmm_types.h>
30 #ifndef CONFIG_DEBUG_APIC
32 #define PrintDebug(fmt, args...)
35 #ifdef CONFIG_DEBUG_APIC
36 static char *shorthand_str[] = {
43 static char *deliverymode_str[] = {
55 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
56 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
58 #define APIC_FIXED_DELIVERY 0x0
59 #define APIC_SMI_DELIVERY 0x2
60 #define APIC_NMI_DELIVERY 0x4
61 #define APIC_INIT_DELIVERY 0x5
62 #define APIC_EXTINT_DELIVERY 0x7
65 #define BASE_ADDR_MSR 0x0000001B
66 #define DEFAULT_BASE_ADDR 0xfee00000
68 #define APIC_ID_OFFSET 0x020
69 #define APIC_VERSION_OFFSET 0x030
70 #define TPR_OFFSET 0x080
71 #define APR_OFFSET 0x090
72 #define PPR_OFFSET 0x0a0
73 #define EOI_OFFSET 0x0b0
74 #define REMOTE_READ_OFFSET 0x0c0
75 #define LDR_OFFSET 0x0d0
76 #define DFR_OFFSET 0x0e0
77 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
79 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
80 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
81 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
82 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
83 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
84 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
85 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
86 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
88 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
89 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
90 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
91 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
92 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
93 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
94 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
95 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
98 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
99 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
100 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
101 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
102 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
103 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
104 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
105 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
108 #define ESR_OFFSET 0x280
109 #define INT_CMD_LO_OFFSET 0x300
110 #define INT_CMD_HI_OFFSET 0x310
111 #define TMR_LOC_VEC_TBL_OFFSET 0x320
112 #define THERM_LOC_VEC_TBL_OFFSET 0x330
113 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
114 #define LINT0_VEC_TBL_OFFSET 0x350
115 #define LINT1_VEC_TBL_OFFSET 0x360
116 #define ERR_VEC_TBL_OFFSET 0x370
117 #define TMR_INIT_CNT_OFFSET 0x380
118 #define TMR_CUR_CNT_OFFSET 0x390
119 #define TMR_DIV_CFG_OFFSET 0x3e0
120 #define EXT_APIC_FEATURE_OFFSET 0x400
121 #define EXT_APIC_CMD_OFFSET 0x410
122 #define SEOI_OFFSET 0x420
124 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
125 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
126 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
127 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
128 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
129 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
130 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
131 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
133 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
134 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
135 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
136 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
143 uint8_t bootstrap_cpu : 1;
145 uint8_t apic_enable : 1;
146 uint64_t base_addr : 40;
148 } __attribute__((packed));
149 } __attribute__((packed));
150 } __attribute__((packed));
154 typedef enum {INIT_ST,
156 STARTED} ipi_state_t;
158 struct apic_dev_state;
164 struct apic_msr base_addr_msr;
167 /* memory map registers */
169 struct lapic_id_reg lapic_id;
170 struct apic_ver_reg apic_ver;
171 struct ext_apic_ctrl_reg ext_apic_ctrl;
172 struct local_vec_tbl_reg local_vec_tbl;
173 struct tmr_vec_tbl_reg tmr_vec_tbl;
174 struct tmr_div_cfg_reg tmr_div_cfg;
175 struct lint_vec_tbl_reg lint0_vec_tbl;
176 struct lint_vec_tbl_reg lint1_vec_tbl;
177 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
178 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
179 struct err_vec_tbl_reg err_vec_tbl;
180 struct err_status_reg err_status;
181 struct spurious_int_reg spurious_int;
182 struct int_cmd_reg int_cmd;
183 struct log_dst_reg log_dst;
184 struct dst_fmt_reg dst_fmt;
185 struct arb_prio_reg arb_prio;
186 struct task_prio_reg task_prio;
187 struct proc_prio_reg proc_prio;
188 struct ext_apic_feature_reg ext_apic_feature;
189 struct spec_eoi_reg spec_eoi;
192 uint32_t tmr_cur_cnt;
193 uint32_t tmr_init_cnt;
196 struct local_vec_tbl_reg ext_intr_vec_tbl[4];
198 uint32_t rem_rd_data;
201 ipi_state_t ipi_state;
203 uint8_t int_req_reg[32];
204 uint8_t int_svc_reg[32];
205 uint8_t int_en_reg[32];
206 uint8_t trig_mode_reg[32];
208 struct guest_info * core;
218 struct apic_dev_state {
221 struct apic_state apics[0];
222 } __attribute__((packed));
226 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data);
227 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data);
229 static void init_apic_state(struct apic_state * apic, uint32_t id) {
230 apic->base_addr = DEFAULT_BASE_ADDR;
233 // boot processor, enabled
234 apic->base_addr_msr.value = 0x0000000000000900LL;
236 // ap processor, enabled
237 apic->base_addr_msr.value = 0x0000000000000800LL;
240 // same base address regardless of ap or main
241 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
243 PrintDebug("apic %u: (init_apic_state): msr=0x%llx\n",id, apic->base_addr_msr.value);
245 PrintDebug("apic %u: (init_apic_state): Sizeof Interrupt Request Register %d, should be 32\n",
246 id, (uint_t)sizeof(apic->int_req_reg));
248 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
249 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
250 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
251 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
253 apic->eoi = 0x00000000;
254 apic->rem_rd_data = 0x00000000;
255 apic->tmr_init_cnt = 0x00000000;
256 apic->tmr_cur_cnt = 0x00000000;
258 apic->lapic_id.val = id;
260 apic->ipi_state = INIT_ST;
262 // The P6 has 6 LVT entries, so we set the value to (6-1)...
263 apic->apic_ver.val = 0x80050010;
265 apic->task_prio.val = 0x00000000;
266 apic->arb_prio.val = 0x00000000;
267 apic->proc_prio.val = 0x00000000;
268 apic->log_dst.val = 0x00000000;
269 apic->dst_fmt.val = 0xffffffff;
270 apic->spurious_int.val = 0x000000ff;
271 apic->err_status.val = 0x00000000;
272 apic->int_cmd.val = 0x0000000000000000LL;
273 apic->tmr_vec_tbl.val = 0x00010000;
274 apic->therm_loc_vec_tbl.val = 0x00010000;
275 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
276 apic->lint0_vec_tbl.val = 0x00010000;
277 apic->lint1_vec_tbl.val = 0x00010000;
278 apic->err_vec_tbl.val = 0x00010000;
279 apic->tmr_div_cfg.val = 0x00000000;
280 //apic->ext_apic_feature.val = 0x00000007;
281 apic->ext_apic_feature.val = 0x00040007;
282 apic->ext_apic_ctrl.val = 0x00000000;
283 apic->spec_eoi.val = 0x00000000;
285 v3_lock_init(&(apic->lock));
291 static int read_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t * dst, void * priv_data) {
292 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
293 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
295 PrintDebug("apic %u: core %u: MSR read\n", apic->lapic_id.val, core->cpu_id);
297 dst->value = apic->base_addr;
298 v3_unlock(apic->lock);
303 static int write_apic_msr(struct guest_info * core, uint_t msr, v3_msr_t src, void * priv_data) {
304 struct apic_dev_state * apic_dev = (struct apic_dev_state *)priv_data;
305 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
306 struct v3_mem_region * old_reg = v3_get_mem_region(core->vm_info, core->cpu_id, apic->base_addr);
309 PrintDebug("apic %u: core %u: MSR write\n", apic->lapic_id.val, core->cpu_id);
311 if (old_reg == NULL) {
313 PrintError("apic %u: core %u: APIC Base address region does not exit...\n",
314 apic->lapic_id.val, core->cpu_id);
320 v3_delete_mem_region(core->vm_info, old_reg);
322 apic->base_addr = src.value;
324 if (v3_hook_full_mem(core->vm_info, core->cpu_id, apic->base_addr,
325 apic->base_addr + PAGE_SIZE_4KB,
326 apic_read, apic_write, apic_dev) == -1) {
327 PrintError("apic %u: core %u: Could not hook new APIC Base address\n",
328 apic->lapic_id.val, core->cpu_id);
329 v3_unlock(apic->lock);
333 v3_unlock(apic->lock);
338 // irq_num is the bit offset into a 256 bit buffer...
339 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
340 int major_offset = (irq_num & ~0x00000007) >> 3;
341 int minor_offset = irq_num & 0x00000007;
342 uint8_t * req_location = apic->int_req_reg + major_offset;
343 uint8_t * en_location = apic->int_en_reg + major_offset;
344 uint8_t flag = 0x1 << minor_offset;
349 PrintError("apic %u: core %d: Attempting to raise an invalid interrupt: %d\n",
350 apic->lapic_id.val, apic->core->cpu_id, irq_num);
355 PrintDebug("apic %u: core %d: Raising APIC IRQ %d\n", apic->lapic_id.val, apic->core->cpu_id, irq_num);
357 if (*req_location & flag) {
358 PrintDebug("Interrupt %d coallescing\n", irq_num);
361 if (*en_location & flag) {
362 *req_location |= flag;
364 PrintDebug("apic %u: core %d: Interrupt not enabled... %.2x\n",
365 apic->lapic_id.val, apic->core->cpu_id,*en_location);
374 static int get_highest_isr(struct apic_state * apic) {
377 // We iterate backwards to find the highest priority
378 for (i = 31; i >= 0; i--) {
379 uint8_t * svc_major = apic->int_svc_reg + i;
381 if ((*svc_major) & 0xff) {
382 for (j = 7; j >= 0; j--) {
383 uint8_t flag = 0x1 << j;
384 if ((*svc_major) & flag) {
385 return ((i * 8) + j);
396 static int get_highest_irr(struct apic_state * apic) {
399 // We iterate backwards to find the highest priority
400 for (i = 31; i >= 0; i--) {
401 uint8_t * req_major = apic->int_req_reg + i;
403 if ((*req_major) & 0xff) {
404 for (j = 7; j >= 0; j--) {
405 uint8_t flag = 0x1 << j;
406 if ((*req_major) & flag) {
407 return ((i * 8) + j);
419 static int apic_do_eoi(struct apic_state * apic) {
420 int isr_irq = get_highest_isr(apic);
423 int major_offset = (isr_irq & ~0x00000007) >> 3;
424 int minor_offset = isr_irq & 0x00000007;
425 uint8_t flag = 0x1 << minor_offset;
426 uint8_t * svc_location = apic->int_svc_reg + major_offset;
428 PrintDebug("apic %u: core ?: Received APIC EOI for IRQ %d\n", apic->lapic_id.val,isr_irq);
430 *svc_location &= ~flag;
432 #ifdef CONFIG_CRAY_XT
434 if ((isr_irq == 238) ||
436 PrintDebug("apic %u: core ?: Acking IRQ %d\n", apic->lapic_id.val,isr_irq);
439 if (isr_irq == 238) {
444 //PrintError("apic %u: core ?: Spurious EOI...\n",apic->lapic_id.val);
451 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
452 uint32_t vec_num = 0;
453 uint32_t del_mode = 0;
459 vec_num = apic->tmr_vec_tbl.vec;
460 del_mode = APIC_FIXED_DELIVERY;
461 masked = apic->tmr_vec_tbl.mask;
464 vec_num = apic->therm_loc_vec_tbl.vec;
465 del_mode = apic->therm_loc_vec_tbl.msg_type;
466 masked = apic->therm_loc_vec_tbl.mask;
469 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
470 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
471 masked = apic->perf_ctr_loc_vec_tbl.mask;
474 vec_num = apic->lint0_vec_tbl.vec;
475 del_mode = apic->lint0_vec_tbl.msg_type;
476 masked = apic->lint0_vec_tbl.mask;
479 vec_num = apic->lint1_vec_tbl.vec;
480 del_mode = apic->lint1_vec_tbl.msg_type;
481 masked = apic->lint1_vec_tbl.mask;
484 vec_num = apic->err_vec_tbl.vec;
485 del_mode = APIC_FIXED_DELIVERY;
486 masked = apic->err_vec_tbl.mask;
489 PrintError("apic %u: core ?: Invalid APIC interrupt type\n", apic->lapic_id.val);
493 // interrupt is masked, don't send
495 PrintDebug("apic %u: core ?: Inerrupt is masked\n", apic->lapic_id.val);
499 if (del_mode == APIC_FIXED_DELIVERY) {
500 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
501 return activate_apic_irq(apic, vec_num);
503 PrintError("apic %u: core ?: Unhandled Delivery Mode\n", apic->lapic_id.val);
510 static inline int should_deliver_cluster_ipi(struct guest_info * dst_core,
511 struct apic_state * dst_apic, uint8_t mda) {
513 if ( ((mda & 0xf0) == (dst_apic->log_dst.dst_log_id & 0xf0)) && // (I am in the cluster and
514 ((mda & 0x0f) & (dst_apic->log_dst.dst_log_id & 0x0f)) ) { // I am in the set)
516 PrintDebug("apic %u core %u: accepting clustered IRQ (mda 0x%x == log_dst 0x%x)\n",
517 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
518 dst_apic->log_dst.dst_log_id);
522 PrintDebug("apic %u core %u: rejecting clustered IRQ (mda 0x%x != log_dst 0x%x)\n",
523 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
524 dst_apic->log_dst.dst_log_id);
529 static inline int should_deliver_flat_ipi(struct guest_info * dst_core,
530 struct apic_state * dst_apic, uint8_t mda) {
532 if (dst_apic->log_dst.dst_log_id & mda) { // I am in the set
534 PrintDebug("apic %u core %u: accepting flat IRQ (mda 0x%x == log_dst 0x%x)\n",
535 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
536 dst_apic->log_dst.dst_log_id);
539 PrintDebug("apic %u core %u: rejecting flat IRQ (mda 0x%x != log_dst 0x%x)\n",
540 dst_apic->lapic_id.val, dst_core->cpu_id, mda,
541 dst_apic->log_dst.dst_log_id);
548 static int should_deliver_ipi(struct guest_info * dst_core,
549 struct apic_state * dst_apic, uint8_t mda) {
552 if (dst_apic->dst_fmt.model == 0xf) {
555 // always deliver broadcast
559 return should_deliver_flat_ipi(dst_core, dst_apic, mda);
560 } else if (dst_apic->dst_fmt.model == 0x0) {
563 // always deliver broadcast
567 return should_deliver_cluster_ipi(dst_core, dst_apic, mda);
569 PrintError("apic %u core %u: invalid destination format register value 0x%x for logical mode delivery.\n",
570 dst_apic->lapic_id.val, dst_core->cpu_id, dst_apic->dst_fmt.model);
576 static int deliver_ipi(struct apic_state * src_apic,
577 struct apic_state * dst_apic,
578 uint32_t vector, uint8_t del_mode) {
580 struct guest_info * dst_core = dst_apic->core;
585 case 1: // lowest priority
586 PrintDebug("delivering IRQ %d to core %u\n", vector, dst_core->cpu_id);
588 activate_apic_irq(dst_apic, vector);
590 if (dst_apic != src_apic) {
591 // Assume core # is same as logical processor for now
592 // TODO FIX THIS FIX THIS
593 // THERE SHOULD BE: guestapicid->virtualapicid map,
594 // cpu_id->logical processor map
595 // host maitains logical proc->phsysical proc
596 PrintDebug(" non-local core, forcing it to exit\n");
598 v3_interrupt_cpu(dst_core->vm_info, dst_core->cpu_id, 0);
604 PrintDebug(" INIT delivery to core %u\n", dst_core->cpu_id);
606 // TODO: any APIC reset on dest core (shouldn't be needed, but not sure...)
609 if (dst_apic->ipi_state != INIT_ST) {
610 PrintError(" Warning: core %u is not in INIT state (mode = %d), ignored\n",
611 dst_core->cpu_id, dst_apic->ipi_state);
612 // Only a warning, since INIT INIT SIPI is common
616 // We transition the target core to SIPI state
617 dst_apic->ipi_state = SIPI; // note: locking should not be needed here
619 // That should be it since the target core should be
620 // waiting in host on this transition
621 // either it's on another core or on a different preemptive thread
622 // in both cases, it will quickly notice this transition
623 // in particular, we should not need to force an exit here
625 PrintDebug(" INIT delivery done\n");
632 if (dst_apic->ipi_state != SIPI) {
633 PrintError(" core %u is not in SIPI state (mode = %d), ignored!\n",
634 dst_core->cpu_id, dst_apic->ipi_state);
638 // Write the RIP, CS, and descriptor
639 // assume the rest is already good to go
641 // vector VV -> rip at 0
643 // This means we start executing at linear address VV000
645 // So the selector needs to be VV00
646 // and the base needs to be VV000
649 dst_core->segments.cs.selector = vector << 8;
650 dst_core->segments.cs.limit = 0xffff;
651 dst_core->segments.cs.base = vector << 12;
653 PrintDebug(" SIPI delivery (0x%x -> 0x%x:0x0) to core %u\n",
654 vector, dst_core->segments.cs.selector, dst_core->cpu_id);
655 // Maybe need to adjust the APIC?
657 // We transition the target core to SIPI state
658 dst_core->core_run_state = CORE_RUNNING; // note: locking should not be needed here
659 dst_apic->ipi_state = STARTED;
661 // As with INIT, we should not need to do anything else
663 PrintDebug(" SIPI delivery done\n");
672 PrintError("IPI %d delivery is unsupported\n", del_mode);
681 static int route_ipi(struct apic_dev_state * apic_dev,
682 struct apic_state * src_apic,
683 struct int_cmd_reg * icr) {
684 struct apic_state * dest_apic = NULL;
686 PrintDebug("route_ipi: src_apic=%p, icr_data=%p\n",
687 src_apic, (void *)(addr_t)icr->val);
690 if ((icr->dst_mode == 0) && (icr->dst >= apic_dev->num_apics)) {
691 PrintError("route_ipi: Attempted send to unregistered apic id=%u\n",
696 dest_apic = &(apic_dev->apics[icr->dst]);
699 PrintDebug("route_ipi: IPI %s %u from apic %p to %s %s %u (icr=0x%llx)\n",
700 deliverymode_str[icr->del_mode],
703 (icr->dst_mode == 0) ? "(physical)" : "(logical)",
704 shorthand_str[icr->dst_shorthand],
709 switch (icr->dst_shorthand) {
711 case 0: // no shorthand
712 if (icr->dst_mode == 0) {
715 if (deliver_ipi(src_apic, dest_apic,
716 icr->vec, icr->del_mode) == -1) {
717 PrintError("Error: Could not deliver IPI\n");
724 uint8_t mda = icr->dst;
726 for (i = 0; i < apic_dev->num_apics; i++) {
727 dest_apic = &(apic_dev->apics[i]);
728 int del_flag = should_deliver_ipi(dest_apic->core, dest_apic, mda);
730 if (del_flag == -1) {
731 PrintError("Error checking delivery mode\n");
733 } else if (del_flag == 1) {
734 if (deliver_ipi(src_apic, dest_apic,
735 icr->vec, icr->del_mode) == -1) {
736 PrintError("Error: Could not deliver IPI\n");
747 if (src_apic == NULL) {
748 PrintError("Sending IPI to self from generic IPI sender\n");
752 if (icr->dst_mode == 0) {
753 if (deliver_ipi(src_apic, src_apic, icr->vec, icr->del_mode) == -1) {
754 PrintError("Could not deliver IPI\n");
759 PrintError("use of logical delivery in self is not yet supported.\n");
765 case 3: { // all and all-but-me
766 // assuming that logical verus physical doesn't matter
767 // although it is odd that both are used
770 for (i = 0; i < apic_dev->num_apics; i++) {
771 dest_apic = &(apic_dev->apics[i]);
773 if ((dest_apic != src_apic) || (icr->dst_shorthand == 2)) {
774 if (deliver_ipi(src_apic, dest_apic, icr->vec, icr->del_mode) == -1) {
775 PrintError("Error: Could not deliver IPI\n");
784 PrintError("Error routing IPI, invalid Mode (%d)\n", icr->dst_shorthand);
794 static int apic_read(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
795 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
796 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
797 addr_t reg_addr = guest_addr - apic->base_addr;
798 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
802 PrintDebug("apic %u: core %u: at %p: Read apic address space (%p)\n",
803 apic->lapic_id.val, core->cpu_id, apic, (void *)guest_addr);
805 if (msr->apic_enable == 0) {
806 PrintError("apic %u: core %u: Read from APIC address space with disabled APIC, apic msr=0x%llx\n",
807 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
813 /* Because "May not be supported" doesn't matter to Linux developers... */
814 /* if (length != 4) { */
815 /* PrintError("Invalid apic read length (%d)\n", length); */
819 switch (reg_addr & ~0x3) {
821 // Well, only an idiot would read from a architectural write only register
823 // PrintError("Attempting to read from write only register\n");
829 val = apic->lapic_id.val;
831 case APIC_VERSION_OFFSET:
832 val = apic->apic_ver.val;
835 val = apic->task_prio.val;
838 val = apic->arb_prio.val;
841 val = apic->proc_prio.val;
843 case REMOTE_READ_OFFSET:
844 val = apic->rem_rd_data;
847 val = apic->log_dst.val;
850 val = apic->dst_fmt.val;
852 case SPURIOUS_INT_VEC_OFFSET:
853 val = apic->spurious_int.val;
856 val = apic->err_status.val;
858 case TMR_LOC_VEC_TBL_OFFSET:
859 val = apic->tmr_vec_tbl.val;
861 case LINT0_VEC_TBL_OFFSET:
862 val = apic->lint0_vec_tbl.val;
864 case LINT1_VEC_TBL_OFFSET:
865 val = apic->lint1_vec_tbl.val;
867 case ERR_VEC_TBL_OFFSET:
868 val = apic->err_vec_tbl.val;
870 case TMR_INIT_CNT_OFFSET:
871 val = apic->tmr_init_cnt;
873 case TMR_DIV_CFG_OFFSET:
874 val = apic->tmr_div_cfg.val;
878 val = *(uint32_t *)(apic->int_en_reg);
881 val = *(uint32_t *)(apic->int_en_reg + 4);
884 val = *(uint32_t *)(apic->int_en_reg + 8);
887 val = *(uint32_t *)(apic->int_en_reg + 12);
890 val = *(uint32_t *)(apic->int_en_reg + 16);
893 val = *(uint32_t *)(apic->int_en_reg + 20);
896 val = *(uint32_t *)(apic->int_en_reg + 24);
899 val = *(uint32_t *)(apic->int_en_reg + 28);
903 val = *(uint32_t *)(apic->int_svc_reg);
906 val = *(uint32_t *)(apic->int_svc_reg + 4);
909 val = *(uint32_t *)(apic->int_svc_reg + 8);
912 val = *(uint32_t *)(apic->int_svc_reg + 12);
915 val = *(uint32_t *)(apic->int_svc_reg + 16);
918 val = *(uint32_t *)(apic->int_svc_reg + 20);
921 val = *(uint32_t *)(apic->int_svc_reg + 24);
924 val = *(uint32_t *)(apic->int_svc_reg + 28);
928 val = *(uint32_t *)(apic->trig_mode_reg);
931 val = *(uint32_t *)(apic->trig_mode_reg + 4);
934 val = *(uint32_t *)(apic->trig_mode_reg + 8);
937 val = *(uint32_t *)(apic->trig_mode_reg + 12);
940 val = *(uint32_t *)(apic->trig_mode_reg + 16);
943 val = *(uint32_t *)(apic->trig_mode_reg + 20);
946 val = *(uint32_t *)(apic->trig_mode_reg + 24);
949 val = *(uint32_t *)(apic->trig_mode_reg + 28);
953 val = *(uint32_t *)(apic->int_req_reg);
956 val = *(uint32_t *)(apic->int_req_reg + 4);
959 val = *(uint32_t *)(apic->int_req_reg + 8);
962 val = *(uint32_t *)(apic->int_req_reg + 12);
965 val = *(uint32_t *)(apic->int_req_reg + 16);
968 val = *(uint32_t *)(apic->int_req_reg + 20);
971 val = *(uint32_t *)(apic->int_req_reg + 24);
974 val = *(uint32_t *)(apic->int_req_reg + 28);
976 case TMR_CUR_CNT_OFFSET:
977 val = apic->tmr_cur_cnt;
980 // We are not going to implement these....
981 case THERM_LOC_VEC_TBL_OFFSET:
982 val = apic->therm_loc_vec_tbl.val;
984 case PERF_CTR_LOC_VEC_TBL_OFFSET:
985 val = apic->perf_ctr_loc_vec_tbl.val;
991 case INT_CMD_LO_OFFSET:
992 val = apic->int_cmd.lo;
994 case INT_CMD_HI_OFFSET:
995 val = apic->int_cmd.hi;
998 // handle current timer count
1000 // Unhandled Registers
1001 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1002 val = apic->ext_intr_vec_tbl[0].val;
1004 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1005 val = apic->ext_intr_vec_tbl[1].val;
1007 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1008 val = apic->ext_intr_vec_tbl[2].val;
1010 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1011 val = apic->ext_intr_vec_tbl[3].val;
1015 case EXT_APIC_FEATURE_OFFSET:
1016 case EXT_APIC_CMD_OFFSET:
1020 PrintError("apic %u: core %u: Read from Unhandled APIC Register: %x (getting zero)\n",
1021 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1027 uint_t byte_addr = reg_addr & 0x3;
1028 uint8_t * val_ptr = (uint8_t *)dst;
1030 *val_ptr = *(((uint8_t *)&val) + byte_addr);
1032 } else if ((length == 2) &&
1033 ((reg_addr & 0x3) == 0x3)) {
1034 uint_t byte_addr = reg_addr & 0x3;
1035 uint16_t * val_ptr = (uint16_t *)dst;
1036 *val_ptr = *(((uint16_t *)&val) + byte_addr);
1038 } else if (length == 4) {
1039 uint32_t * val_ptr = (uint32_t *)dst;
1043 PrintError("apic %u: core %u: Invalid apic read length (%d)\n",
1044 apic->lapic_id.val, core->cpu_id, length);
1048 PrintDebug("apic %u: core %u: Read finished (val=%x)\n",
1049 apic->lapic_id.val, core->cpu_id, *(uint32_t *)dst);
1058 static int apic_write(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * priv_data) {
1059 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1060 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1061 addr_t reg_addr = guest_addr - apic->base_addr;
1062 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
1063 uint32_t op_val = *(uint32_t *)src;
1065 PrintDebug("apic %u: core %u: at %p and priv_data is at %p\n",
1066 apic->lapic_id.val, core->cpu_id, apic, priv_data);
1068 PrintDebug("Write to address space (%p) (val=%x)\n",
1069 (void *)guest_addr, *(uint32_t *)src);
1071 if (msr->apic_enable == 0) {
1072 PrintError("apic %u: core %u: Write to APIC address space with disabled APIC, apic msr=0x%llx\n",
1073 apic->lapic_id.val, core->cpu_id, apic->base_addr_msr.value);
1079 PrintError("apic %u: core %u: Invalid apic write length (%d)\n",
1080 apic->lapic_id.val, length, core->cpu_id);
1085 case REMOTE_READ_OFFSET:
1086 case APIC_VERSION_OFFSET:
1113 case EXT_APIC_FEATURE_OFFSET:
1115 PrintError("apic %u: core %u: Attempting to write to read only register %p (error)\n",
1116 apic->lapic_id.val, core->cpu_id, (void *)reg_addr);
1122 case APIC_ID_OFFSET:
1123 PrintDebug("apic %u: core %u: my id is being changed to %u\n",
1124 apic->lapic_id.val, core->cpu_id, op_val);
1126 apic->lapic_id.val = op_val;
1129 apic->task_prio.val = op_val;
1132 PrintDebug("apic %u: core %u: setting log_dst.val to 0x%x\n",
1133 apic->lapic_id.val, core->cpu_id, op_val);
1134 apic->log_dst.val = op_val;
1137 apic->dst_fmt.val = op_val;
1139 case SPURIOUS_INT_VEC_OFFSET:
1140 apic->spurious_int.val = op_val;
1143 apic->err_status.val = op_val;
1145 case TMR_LOC_VEC_TBL_OFFSET:
1146 apic->tmr_vec_tbl.val = op_val;
1148 case THERM_LOC_VEC_TBL_OFFSET:
1149 apic->therm_loc_vec_tbl.val = op_val;
1151 case PERF_CTR_LOC_VEC_TBL_OFFSET:
1152 apic->perf_ctr_loc_vec_tbl.val = op_val;
1154 case LINT0_VEC_TBL_OFFSET:
1155 apic->lint0_vec_tbl.val = op_val;
1157 case LINT1_VEC_TBL_OFFSET:
1158 apic->lint1_vec_tbl.val = op_val;
1160 case ERR_VEC_TBL_OFFSET:
1161 apic->err_vec_tbl.val = op_val;
1163 case TMR_INIT_CNT_OFFSET:
1164 apic->tmr_init_cnt = op_val;
1165 apic->tmr_cur_cnt = op_val;
1167 case TMR_CUR_CNT_OFFSET:
1168 apic->tmr_cur_cnt = op_val;
1170 case TMR_DIV_CFG_OFFSET:
1171 apic->tmr_div_cfg.val = op_val;
1175 // Enable mask (256 bits)
1177 *(uint32_t *)(apic->int_en_reg) = op_val;
1180 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
1183 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
1186 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
1189 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
1192 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
1195 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
1198 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
1201 case EXT_INT_LOC_VEC_TBL_OFFSET0:
1202 apic->ext_intr_vec_tbl[0].val = op_val;
1204 case EXT_INT_LOC_VEC_TBL_OFFSET1:
1205 apic->ext_intr_vec_tbl[1].val = op_val;
1207 case EXT_INT_LOC_VEC_TBL_OFFSET2:
1208 apic->ext_intr_vec_tbl[2].val = op_val;
1210 case EXT_INT_LOC_VEC_TBL_OFFSET3:
1211 apic->ext_intr_vec_tbl[3].val = op_val;
1221 case INT_CMD_LO_OFFSET:
1222 apic->int_cmd.lo = op_val;
1224 PrintDebug("apic %u: core %u: sending cmd 0x%llx to apic %u\n",
1225 apic->lapic_id.val, core->cpu_id,
1226 apic->int_cmd.val, apic->int_cmd.dst);
1228 if (route_ipi(apic_dev, apic, &(apic->int_cmd)) == -1) {
1229 PrintError("IPI Routing failure\n");
1235 case INT_CMD_HI_OFFSET:
1236 apic->int_cmd.hi = op_val;
1240 // Unhandled Registers
1241 case EXT_APIC_CMD_OFFSET:
1244 PrintError("apic %u: core %u: Write to Unhandled APIC Register: %x (ignored)\n",
1245 apic->lapic_id.val, core->cpu_id, (uint32_t)reg_addr);
1250 PrintDebug("apic %u: core %u: Write finished\n", apic->lapic_id.val, core->cpu_id);
1257 /* Interrupt Controller Functions */
1259 // returns 1 if an interrupt is pending, 0 otherwise
1260 static int apic_intr_pending(struct guest_info * core, void * private_data) {
1261 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1262 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1263 int req_irq = get_highest_irr(apic);
1264 int svc_irq = get_highest_isr(apic);
1266 // PrintDebug("apic %u: core %u: req_irq=%d, svc_irq=%d\n",apic->lapic_id.val,info->cpu_id,req_irq,svc_irq);
1268 if ((req_irq >= 0) &&
1269 (req_irq > svc_irq)) {
1276 static int apic_get_intr_number(struct guest_info * core, void * private_data) {
1277 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1278 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1279 int req_irq = get_highest_irr(apic);
1280 int svc_irq = get_highest_isr(apic);
1282 if (svc_irq == -1) {
1284 } else if (svc_irq < req_irq) {
1292 int v3_apic_send_ipi(struct v3_vm_info * vm, struct vm_device * dev,
1293 struct v3_gen_ipi * ipi) {
1294 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(dev->private_data);
1295 struct int_cmd_reg tmp_icr;
1297 // zero out all the fields
1301 tmp_icr.vec = ipi->vector;
1302 tmp_icr.del_mode = ipi->mode;
1303 tmp_icr.dst_mode = ipi->logical;
1304 tmp_icr.trig_mode = ipi->trigger_mode;
1305 tmp_icr.dst_shorthand = ipi->dst_shorthand;
1306 tmp_icr.dst = ipi->dst;
1309 return route_ipi(apic_dev, NULL, &tmp_icr);
1313 int v3_apic_raise_intr(struct v3_vm_info * vm, struct vm_device * dev,
1314 uint32_t irq, uint32_t dst) {
1315 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(dev->private_data);
1316 struct apic_state * apic = &(apic_dev->apics[dst]);
1318 PrintDebug("apic %u core ?: raising interrupt IRQ %u (dst = %u).\n", apic->lapic_id.val, irq, dst);
1320 activate_apic_irq(apic, irq);
1322 if (V3_Get_CPU() != dst) {
1323 v3_interrupt_cpu(vm, dst, 0);
1331 static int apic_begin_irq(struct guest_info * core, void * private_data, int irq) {
1332 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(private_data);
1333 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1334 int major_offset = (irq & ~0x00000007) >> 3;
1335 int minor_offset = irq & 0x00000007;
1336 uint8_t * req_location = apic->int_req_reg + major_offset;
1337 uint8_t * svc_location = apic->int_svc_reg + major_offset;
1338 uint8_t flag = 0x01 << minor_offset;
1340 if (*req_location & flag) {
1341 // we will only pay attention to a begin irq if we
1342 // know that we initiated it!
1343 *svc_location |= flag;
1344 *req_location &= ~flag;
1347 //PrintDebug("apic %u: core %u: begin irq for %d ignored since I don't own it\n",
1348 // apic->lapic_id.val, core->cpu_id, irq);
1357 /* Timer Functions */
1358 static void apic_update_time(struct guest_info * core,
1359 uint64_t cpu_cycles, uint64_t cpu_freq,
1361 struct apic_dev_state * apic_dev = (struct apic_dev_state *)(priv_data);
1362 struct apic_state * apic = &(apic_dev->apics[core->cpu_id]);
1364 // The 32 bit GCC runtime is a pile of shit
1366 uint64_t tmr_ticks = 0;
1368 uint32_t tmr_ticks = 0;
1371 uint8_t tmr_div = *(uint8_t *)&(apic->tmr_div_cfg.val);
1372 uint_t shift_num = 0;
1375 // Check whether this is true:
1376 // -> If the Init count is zero then the timer is disabled
1377 // and doesn't just blitz interrupts to the CPU
1378 if ((apic->tmr_init_cnt == 0) ||
1379 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
1380 (apic->tmr_cur_cnt == 0))) {
1381 //PrintDebug("apic %u: core %u: APIC timer not yet initialized\n",apic->lapic_id.val,info->cpu_id);
1399 case APIC_TMR_DIV16:
1402 case APIC_TMR_DIV32:
1405 case APIC_TMR_DIV64:
1408 case APIC_TMR_DIV128:
1412 PrintError("apic %u: core %u: Invalid Timer Divider configuration\n",
1413 apic->lapic_id.val, core->cpu_id);
1417 tmr_ticks = cpu_cycles >> shift_num;
1418 // PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
1420 if (tmr_ticks < apic->tmr_cur_cnt) {
1421 apic->tmr_cur_cnt -= tmr_ticks;
1423 tmr_ticks -= apic->tmr_cur_cnt;
1424 apic->tmr_cur_cnt = 0;
1427 PrintDebug("apic %u: core %u: Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
1428 apic->lapic_id.val, core->cpu_id,
1429 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
1431 if (apic_intr_pending(core, priv_data)) {
1432 PrintDebug("apic %u: core %u: Overriding pending IRQ %d\n",
1433 apic->lapic_id.val, core->cpu_id,
1434 apic_get_intr_number(core, priv_data));
1437 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
1438 PrintError("apic %u: core %u: Could not raise Timer interrupt\n",
1439 apic->lapic_id.val, core->cpu_id);
1442 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
1443 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
1444 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
1452 static struct intr_ctrl_ops intr_ops = {
1453 .intr_pending = apic_intr_pending,
1454 .get_intr_number = apic_get_intr_number,
1455 .begin_irq = apic_begin_irq,
1459 static struct vm_timer_ops timer_ops = {
1460 .update_timer = apic_update_time,
1466 static int apic_free(struct vm_device * dev) {
1468 /* TODO: This should crosscall to force an unhook on each CPU */
1470 // struct apic_state * apic = (struct apic_state *)dev->private_data;
1472 v3_unhook_msr(dev->vm, BASE_ADDR_MSR);
1478 static struct v3_device_ops dev_ops = {
1489 static int apic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
1490 char * dev_id = v3_cfg_val(cfg, "ID");
1491 struct apic_dev_state * apic_dev = NULL;
1494 PrintDebug("apic: creating an APIC for each core\n");
1496 apic_dev = (struct apic_dev_state *)V3_Malloc(sizeof(struct apic_dev_state) +
1497 sizeof(struct apic_state) * vm->num_cores);
1499 apic_dev->num_apics = vm->num_cores;
1501 struct vm_device * dev = v3_allocate_device(dev_id, &dev_ops, apic_dev);
1503 if (v3_attach_device(vm, dev) == -1) {
1504 PrintError("apic: Could not attach device %s\n", dev_id);
1509 for (i = 0; i < vm->num_cores; i++) {
1510 struct apic_state * apic = &(apic_dev->apics[i]);
1511 struct guest_info * core = &(vm->cores[i]);
1515 init_apic_state(apic, i);
1517 v3_register_intr_controller(core, &intr_ops, apic_dev);
1519 v3_add_timer(core, &timer_ops, apic_dev);
1521 v3_hook_full_mem(vm, core->cpu_id, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, apic_dev);
1523 PrintDebug("apic %u: (setup device): done, my id is %u\n", i, apic->lapic_id.val);
1526 #ifdef CONFIG_DEBUG_APIC
1527 for (i = 0; i < vm->num_cores; i++) {
1528 struct apic_state * apic = &(apic_dev->apics[i]);
1529 PrintDebug("apic: sanity check: apic %u (at %p) has id %u and msr value %llx\n",
1530 i, apic, apic->lapic_id.val, apic->base_addr_msr.value);
1535 PrintDebug("apic: priv_data is at %p\n", apic_dev);
1537 v3_hook_msr(vm, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, apic_dev);
1544 device_register("LAPIC", apic_init)