2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <devices/apic.h>
22 #include <devices/apic_regs.h>
23 #include <palacios/vmm.h>
24 #include <palacios/vmm_msr.h>
29 #define PrintDebug(fmt, args...)
33 typedef enum { APIC_TMR_INT, APIC_THERM_INT, APIC_PERF_INT,
34 APIC_LINT0_INT, APIC_LINT1_INT, APIC_ERR_INT } apic_irq_type_t;
36 #define APIC_FIXED_DELIVERY 0x0
37 #define APIC_SMI_DELIVERY 0x2
38 #define APIC_NMI_DELIVERY 0x4
39 #define APIC_INIT_DELIVERY 0x5
40 #define APIC_EXTINT_DELIVERY 0x7
43 #define BASE_ADDR_MSR 0x0000001B
44 #define DEFAULT_BASE_ADDR 0xfee00000
46 #define APIC_ID_OFFSET 0x020
47 #define APIC_VERSION_OFFSET 0x030
48 #define TPR_OFFSET 0x080
49 #define APR_OFFSET 0x090
50 #define PPR_OFFSET 0x0a0
51 #define EOI_OFFSET 0x0b0
52 #define REMOTE_READ_OFFSET 0x0c0
53 #define LDR_OFFSET 0x0d0
54 #define DFR_OFFSET 0x0e0
55 #define SPURIOUS_INT_VEC_OFFSET 0x0f0
57 #define ISR_OFFSET0 0x100 // 0x100 - 0x170
58 #define ISR_OFFSET1 0x110 // 0x100 - 0x170
59 #define ISR_OFFSET2 0x120 // 0x100 - 0x170
60 #define ISR_OFFSET3 0x130 // 0x100 - 0x170
61 #define ISR_OFFSET4 0x140 // 0x100 - 0x170
62 #define ISR_OFFSET5 0x150 // 0x100 - 0x170
63 #define ISR_OFFSET6 0x160 // 0x100 - 0x170
64 #define ISR_OFFSET7 0x170 // 0x100 - 0x170
66 #define TRIG_OFFSET0 0x180 // 0x180 - 0x1f0
67 #define TRIG_OFFSET1 0x190 // 0x180 - 0x1f0
68 #define TRIG_OFFSET2 0x1a0 // 0x180 - 0x1f0
69 #define TRIG_OFFSET3 0x1b0 // 0x180 - 0x1f0
70 #define TRIG_OFFSET4 0x1c0 // 0x180 - 0x1f0
71 #define TRIG_OFFSET5 0x1d0 // 0x180 - 0x1f0
72 #define TRIG_OFFSET6 0x1e0 // 0x180 - 0x1f0
73 #define TRIG_OFFSET7 0x1f0 // 0x180 - 0x1f0
76 #define IRR_OFFSET0 0x200 // 0x200 - 0x270
77 #define IRR_OFFSET1 0x210 // 0x200 - 0x270
78 #define IRR_OFFSET2 0x220 // 0x200 - 0x270
79 #define IRR_OFFSET3 0x230 // 0x200 - 0x270
80 #define IRR_OFFSET4 0x240 // 0x200 - 0x270
81 #define IRR_OFFSET5 0x250 // 0x200 - 0x270
82 #define IRR_OFFSET6 0x260 // 0x200 - 0x270
83 #define IRR_OFFSET7 0x270 // 0x200 - 0x270
86 #define ESR_OFFSET 0x280
87 #define INT_CMD_LO_OFFSET 0x300
88 #define INT_CMD_HI_OFFSET 0x310
89 #define TMR_LOC_VEC_TBL_OFFSET 0x320
90 #define THERM_LOC_VEC_TBL_OFFSET 0x330
91 #define PERF_CTR_LOC_VEC_TBL_OFFSET 0x340
92 #define LINT0_VEC_TBL_OFFSET 0x350
93 #define LINT1_VEC_TBL_OFFSET 0x360
94 #define ERR_VEC_TBL_OFFSET 0x370
95 #define TMR_INIT_CNT_OFFSET 0x380
96 #define TMR_CUR_CNT_OFFSET 0x390
97 #define TMR_DIV_CFG_OFFSET 0x3e0
98 #define EXT_APIC_FEATURE_OFFSET 0x400
99 #define EXT_APIC_CMD_OFFSET 0x410
100 #define SEOI_OFFSET 0x420
102 #define IER_OFFSET0 0x480 // 0x480 - 0x4f0
103 #define IER_OFFSET1 0x490 // 0x480 - 0x4f0
104 #define IER_OFFSET2 0x4a0 // 0x480 - 0x4f0
105 #define IER_OFFSET3 0x4b0 // 0x480 - 0x4f0
106 #define IER_OFFSET4 0x4c0 // 0x480 - 0x4f0
107 #define IER_OFFSET5 0x4d0 // 0x480 - 0x4f0
108 #define IER_OFFSET6 0x4e0 // 0x480 - 0x4f0
109 #define IER_OFFSET7 0x4f0 // 0x480 - 0x4f0
111 #define EXT_INT_LOC_VEC_TBL_OFFSET0 0x500 // 0x500 - 0x530
112 #define EXT_INT_LOC_VEC_TBL_OFFSET1 0x510 // 0x500 - 0x530
113 #define EXT_INT_LOC_VEC_TBL_OFFSET2 0x520 // 0x500 - 0x530
114 #define EXT_INT_LOC_VEC_TBL_OFFSET3 0x530 // 0x500 - 0x530
123 uint_t bootstrap_cpu : 1;
125 uint_t apic_enable : 1;
126 ullong_t base_addr : 40;
128 } __attribute__((packed));
129 } __attribute__((packed));
130 } __attribute__((packed));
139 v3_msr_t base_addr_msr;
142 /* memory map registers */
144 struct lapic_id_reg lapic_id;
145 struct apic_ver_reg apic_ver;
146 struct ext_apic_ctrl_reg ext_apic_ctrl;
147 struct local_vec_tbl_reg local_vec_tbl;
148 struct tmr_vec_tbl_reg tmr_vec_tbl;
149 struct tmr_div_cfg_reg tmr_div_cfg;
150 struct lint_vec_tbl_reg lint0_vec_tbl;
151 struct lint_vec_tbl_reg lint1_vec_tbl;
152 struct perf_ctr_loc_vec_tbl_reg perf_ctr_loc_vec_tbl;
153 struct therm_loc_vec_tbl_reg therm_loc_vec_tbl;
154 struct err_vec_tbl_reg err_vec_tbl;
155 struct err_status_reg err_status;
156 struct spurious_int_reg spurious_int;
157 struct int_cmd_reg int_cmd;
158 struct log_dst_reg log_dst;
159 struct dst_fmt_reg dst_fmt;
160 struct arb_prio_reg arb_prio;
161 struct task_prio_reg task_prio;
162 struct proc_prio_reg proc_prio;
163 struct ext_apic_feature_reg ext_apic_feature;
164 struct spec_eoi_reg spec_eoi;
167 uint32_t tmr_cur_cnt;
168 uint32_t tmr_init_cnt;
172 uint32_t rem_rd_data;
175 uchar_t int_req_reg[32];
176 uchar_t int_svc_reg[32];
177 uchar_t int_en_reg[32];
178 uchar_t trig_mode_reg[32];
186 static void init_apic_state(struct apic_state * apic) {
187 apic->base_addr = DEFAULT_BASE_ADDR;
188 apic->base_addr_msr.value = 0x0000000000000900LL;
189 apic->base_addr_msr.value |= ((uint64_t)DEFAULT_BASE_ADDR);
191 PrintDebug("Sizeof Interrupt Request Register %d, should be 32\n",
192 (uint_t)sizeof(apic->int_req_reg));
194 memset(apic->int_req_reg, 0, sizeof(apic->int_req_reg));
195 memset(apic->int_svc_reg, 0, sizeof(apic->int_svc_reg));
196 memset(apic->int_en_reg, 0xff, sizeof(apic->int_en_reg));
197 memset(apic->trig_mode_reg, 0, sizeof(apic->trig_mode_reg));
199 apic->eoi = 0x00000000;
200 apic->rem_rd_data = 0x00000000;
201 apic->tmr_init_cnt = 0x00000000;
202 apic->tmr_cur_cnt = 0x00000000;
205 // We need to figure out what the APIC ID is....
206 apic->lapic_id.val = 0x00000000;
208 // The P6 has 6 LVT entries, so we set the value to (6-1)...
209 apic->apic_ver.val = 0x80050010;
211 apic->task_prio.val = 0x00000000;
212 apic->arb_prio.val = 0x00000000;
213 apic->proc_prio.val = 0x00000000;
214 apic->log_dst.val = 0x00000000;
215 apic->dst_fmt.val = 0xffffffff;
216 apic->spurious_int.val = 0x000000ff;
217 apic->err_status.val = 0x00000000;
218 apic->int_cmd.val = 0x0000000000000000LL;
219 apic->tmr_vec_tbl.val = 0x00010000;
220 apic->therm_loc_vec_tbl.val = 0x00010000;
221 apic->perf_ctr_loc_vec_tbl.val = 0x00010000;
222 apic->lint0_vec_tbl.val = 0x00010000;
223 apic->lint1_vec_tbl.val = 0x00010000;
224 apic->err_vec_tbl.val = 0x00010000;
225 apic->tmr_div_cfg.val = 0x00000000;
226 apic->ext_apic_feature.val = 0x00040007;
227 apic->ext_apic_ctrl.val = 0x00000000;
228 apic->spec_eoi.val = 0x00000000;
234 static int read_apic_msr(uint_t msr, v3_msr_t * dst, void * priv_data) {
235 struct vm_device * dev = (struct vm_device *)priv_data;
236 struct apic_state * apic = (struct apic_state *)dev->private_data;
237 PrintError("READING APIC BASE ADDR: HI=%x LO=%x\n", apic->base_addr_msr.hi, apic->base_addr_msr.lo);
243 static int write_apic_msr(uint_t msr, v3_msr_t src, void * priv_data) {
244 // struct vm_device * dev = (struct vm_device *)priv_data;
245 // struct apic_state * apic = (struct apic_state *)dev->private_data;
247 PrintError("WRITING APIC BASE ADDR: HI=%x LO=%x\n", src.hi, src.lo);
253 // irq_num is the bit offset into a 256 bit buffer...
254 static int activate_apic_irq(struct apic_state * apic, uint32_t irq_num) {
255 int major_offset = (irq_num & ~0x00000007) >> 3;
256 int minor_offset = irq_num & 0x00000007;
257 uchar_t * req_location = apic->int_req_reg + major_offset;
258 uchar_t * en_location = apic->int_en_reg + major_offset;
259 uchar_t flag = 0x1 << minor_offset;
262 PrintError("Attempting to raise an invalid interrupt: %d\n", irq_num);
266 PrintDebug("Raising APIC IRQ %d\n", irq_num);
268 if (*en_location & flag) {
269 *req_location |= flag;
271 PrintDebug("Interrupt not enabled... %.2x\n", *en_location);
280 static int get_highest_isr(struct apic_state * apic) {
283 // We iterate backwards to find the highest priority
284 for (i = 31; i >= 0; i--) {
285 uchar_t * svc_major = apic->int_svc_reg + i;
287 if ((*svc_major) & 0xff) {
288 for (j = 7; j >= 0; j--) {
289 uchar_t flag = 0x1 << j;
290 if ((*svc_major) & flag) {
291 return ((i * 8) + j);
302 static int get_highest_irr(struct apic_state * apic) {
305 // We iterate backwards to find the highest priority
306 for (i = 31; i >= 0; i--) {
307 uchar_t * req_major = apic->int_req_reg + i;
309 if ((*req_major) & 0xff) {
310 for (j = 7; j >= 0; j--) {
311 uchar_t flag = 0x1 << j;
312 if ((*req_major) & flag) {
313 return ((i * 8) + j);
325 static int apic_do_eoi(struct apic_state * apic) {
326 int isr_irq = get_highest_isr(apic);
329 int major_offset = (isr_irq & ~0x00000007) >> 3;
330 int minor_offset = isr_irq & 0x00000007;
331 uchar_t flag = 0x1 << minor_offset;
332 uchar_t * svc_location = apic->int_svc_reg + major_offset;
334 PrintDebug("Received APIC EOI\n");
336 *svc_location &= ~flag;
340 if ((((i * 8) + j) == 238) ||
341 (((i * 8) + j) == 239)) {
342 PrintError("Acking IRQ %d\n", ((i * 8) + j));
345 if (((i * 8) + j) == 238) {
350 PrintError("Spurious EOI...\n");
357 static int activate_internal_irq(struct apic_state * apic, apic_irq_type_t int_type) {
358 uint32_t vec_num = 0;
359 uint32_t del_mode = 0;
365 vec_num = apic->tmr_vec_tbl.vec;
366 del_mode = APIC_FIXED_DELIVERY;
367 masked = apic->tmr_vec_tbl.mask;
370 vec_num = apic->therm_loc_vec_tbl.vec;
371 del_mode = apic->therm_loc_vec_tbl.msg_type;
372 masked = apic->therm_loc_vec_tbl.mask;
375 vec_num = apic->perf_ctr_loc_vec_tbl.vec;
376 del_mode = apic->perf_ctr_loc_vec_tbl.msg_type;
377 masked = apic->perf_ctr_loc_vec_tbl.mask;
380 vec_num = apic->lint0_vec_tbl.vec;
381 del_mode = apic->lint0_vec_tbl.msg_type;
382 masked = apic->lint0_vec_tbl.mask;
385 vec_num = apic->lint1_vec_tbl.vec;
386 del_mode = apic->lint1_vec_tbl.msg_type;
387 masked = apic->lint1_vec_tbl.mask;
390 vec_num = apic->err_vec_tbl.vec;
391 del_mode = APIC_FIXED_DELIVERY;
392 masked = apic->err_vec_tbl.mask;
395 PrintError("Invalid APIC interrupt type\n");
399 // interrupt is masked, don't send
401 PrintDebug("Inerrupt is masked\n");
405 if (del_mode == APIC_FIXED_DELIVERY) {
406 //PrintDebug("Activating internal APIC IRQ %d\n", vec_num);
407 return activate_apic_irq(apic, vec_num);
409 PrintError("Unhandled Delivery Mode\n");
415 static int apic_read(addr_t guest_addr, void * dst, uint_t length, void * priv_data) {
416 struct vm_device * dev = (struct vm_device *)priv_data;
417 struct apic_state * apic = (struct apic_state *)dev->private_data;
418 addr_t reg_addr = guest_addr - apic->base_addr;
419 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
423 PrintDebug("Read apic address space (%p)\n",
426 if (msr->apic_enable == 0) {
427 PrintError("Write to APIC address space with disabled APIC\n");
432 /* Because "May not be supported" doesn't matter to Linux developers... */
433 /* if (length != 4) { */
434 /* PrintError("Invalid apic read length (%d)\n", length); */
438 switch (reg_addr & ~0x3) {
440 // Well, only an idiot would read from a architectural write only register
442 // PrintError("Attempting to read from write only register\n");
448 val = apic->lapic_id.val;
450 case APIC_VERSION_OFFSET:
451 val = apic->apic_ver.val;
454 val = apic->task_prio.val;
457 val = apic->arb_prio.val;
460 val = apic->proc_prio.val;
462 case REMOTE_READ_OFFSET:
463 val = apic->rem_rd_data;
466 val = apic->log_dst.val;
469 val = apic->dst_fmt.val;
471 case SPURIOUS_INT_VEC_OFFSET:
472 val = apic->spurious_int.val;
475 val = apic->err_status.val;
477 case TMR_LOC_VEC_TBL_OFFSET:
478 val = apic->tmr_vec_tbl.val;
480 case LINT0_VEC_TBL_OFFSET:
481 val = apic->lint0_vec_tbl.val;
483 case LINT1_VEC_TBL_OFFSET:
484 val = apic->lint1_vec_tbl.val;
486 case ERR_VEC_TBL_OFFSET:
487 val = apic->err_vec_tbl.val;
489 case TMR_INIT_CNT_OFFSET:
490 val = apic->tmr_init_cnt;
492 case TMR_DIV_CFG_OFFSET:
493 val = apic->tmr_div_cfg.val;
497 val = *(uint32_t *)(apic->int_en_reg);
500 val = *(uint32_t *)(apic->int_en_reg + 4);
503 val = *(uint32_t *)(apic->int_en_reg + 8);
506 val = *(uint32_t *)(apic->int_en_reg + 12);
509 val = *(uint32_t *)(apic->int_en_reg + 16);
512 val = *(uint32_t *)(apic->int_en_reg + 20);
515 val = *(uint32_t *)(apic->int_en_reg + 24);
518 val = *(uint32_t *)(apic->int_en_reg + 28);
522 val = *(uint32_t *)(apic->int_svc_reg);
525 val = *(uint32_t *)(apic->int_svc_reg + 4);
528 val = *(uint32_t *)(apic->int_svc_reg + 8);
531 val = *(uint32_t *)(apic->int_svc_reg + 12);
534 val = *(uint32_t *)(apic->int_svc_reg + 16);
537 val = *(uint32_t *)(apic->int_svc_reg + 20);
540 val = *(uint32_t *)(apic->int_svc_reg + 24);
543 val = *(uint32_t *)(apic->int_svc_reg + 28);
547 val = *(uint32_t *)(apic->trig_mode_reg);
550 val = *(uint32_t *)(apic->trig_mode_reg + 4);
553 val = *(uint32_t *)(apic->trig_mode_reg + 8);
556 val = *(uint32_t *)(apic->trig_mode_reg + 12);
559 val = *(uint32_t *)(apic->trig_mode_reg + 16);
562 val = *(uint32_t *)(apic->trig_mode_reg + 20);
565 val = *(uint32_t *)(apic->trig_mode_reg + 24);
568 val = *(uint32_t *)(apic->trig_mode_reg + 28);
572 val = *(uint32_t *)(apic->int_req_reg);
575 val = *(uint32_t *)(apic->int_req_reg + 4);
578 val = *(uint32_t *)(apic->int_req_reg + 8);
581 val = *(uint32_t *)(apic->int_req_reg + 12);
584 val = *(uint32_t *)(apic->int_req_reg + 16);
587 val = *(uint32_t *)(apic->int_req_reg + 20);
590 val = *(uint32_t *)(apic->int_req_reg + 24);
593 val = *(uint32_t *)(apic->int_req_reg + 28);
595 case TMR_CUR_CNT_OFFSET:
596 val = apic->tmr_cur_cnt;
599 // We are not going to implement these....
600 case THERM_LOC_VEC_TBL_OFFSET:
601 val = apic->therm_loc_vec_tbl.val;
603 case PERF_CTR_LOC_VEC_TBL_OFFSET:
604 val = apic->perf_ctr_loc_vec_tbl.val;
610 case INT_CMD_LO_OFFSET:
611 val = apic->int_cmd.lo;
613 case INT_CMD_HI_OFFSET:
614 val = apic->int_cmd.hi;
617 // handle current timer count
619 // Unhandled Registers
620 case EXT_INT_LOC_VEC_TBL_OFFSET0:
621 case EXT_INT_LOC_VEC_TBL_OFFSET1:
622 case EXT_INT_LOC_VEC_TBL_OFFSET2:
623 case EXT_INT_LOC_VEC_TBL_OFFSET3:
624 case EXT_APIC_FEATURE_OFFSET:
625 case EXT_APIC_CMD_OFFSET:
629 PrintError("Read from Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
635 uint_t byte_addr = reg_addr & 0x3;
636 uint8_t * val_ptr = (uint8_t *)dst;
638 *val_ptr = *(((uint8_t *)&val) + byte_addr);
640 } else if ((length == 2) &&
641 ((reg_addr & 0x3) == 0x3)) {
642 uint_t byte_addr = reg_addr & 0x3;
643 uint16_t * val_ptr = (uint16_t *)dst;
644 *val_ptr = *(((uint16_t *)&val) + byte_addr);
646 } else if (length == 4) {
647 uint32_t * val_ptr = (uint32_t *)dst;
651 PrintError("Invalid apic read length (%d)\n", length);
655 PrintDebug("Read finished (val=%x)\n", *(uint32_t *)dst);
661 static int apic_write(addr_t guest_addr, void * src, uint_t length, void * priv_data) {
662 struct vm_device * dev = (struct vm_device *)priv_data;
663 struct apic_state * apic = (struct apic_state *)dev->private_data;
664 addr_t reg_addr = guest_addr - apic->base_addr;
665 struct apic_msr * msr = (struct apic_msr *)&(apic->base_addr_msr.value);
666 uint32_t op_val = *(uint32_t *)src;
668 PrintDebug("Write to apic address space (%p) (val=%x)\n",
669 (void *)guest_addr, *(uint32_t *)src);
671 if (msr->apic_enable == 0) {
672 PrintError("Write to APIC address space with disabled APIC\n");
678 PrintError("Invalid apic write length (%d)\n", length);
683 case REMOTE_READ_OFFSET:
684 case APIC_VERSION_OFFSET:
711 case EXT_APIC_FEATURE_OFFSET:
713 PrintError("Attempting to write to read only register %p (ignored)\n", (void *)reg_addr);
715 PrintError("Attempting to write to read only register %p (error)\n", (void *)reg_addr);
722 apic->lapic_id.val = op_val;
725 apic->task_prio.val = op_val;
728 apic->log_dst.val = op_val;
731 apic->dst_fmt.val = op_val;
733 case SPURIOUS_INT_VEC_OFFSET:
734 apic->spurious_int.val = op_val;
737 apic->err_status.val = op_val;
739 case TMR_LOC_VEC_TBL_OFFSET:
740 apic->tmr_vec_tbl.val = op_val;
742 case THERM_LOC_VEC_TBL_OFFSET:
743 apic->therm_loc_vec_tbl.val = op_val;
745 case PERF_CTR_LOC_VEC_TBL_OFFSET:
746 apic->perf_ctr_loc_vec_tbl.val = op_val;
748 case LINT0_VEC_TBL_OFFSET:
749 apic->lint0_vec_tbl.val = op_val;
751 case LINT1_VEC_TBL_OFFSET:
752 apic->lint1_vec_tbl.val = op_val;
754 case ERR_VEC_TBL_OFFSET:
755 apic->err_vec_tbl.val = op_val;
757 case TMR_INIT_CNT_OFFSET:
758 apic->tmr_init_cnt = op_val;
759 apic->tmr_cur_cnt = op_val;
761 case TMR_CUR_CNT_OFFSET:
762 apic->tmr_cur_cnt = op_val;
764 case TMR_DIV_CFG_OFFSET:
765 apic->tmr_div_cfg.val = op_val;
769 // Enable mask (256 bits)
771 *(uint32_t *)(apic->int_en_reg) = op_val;
774 *(uint32_t *)(apic->int_en_reg + 4) = op_val;
777 *(uint32_t *)(apic->int_en_reg + 8) = op_val;
780 *(uint32_t *)(apic->int_en_reg + 12) = op_val;
783 *(uint32_t *)(apic->int_en_reg + 16) = op_val;
786 *(uint32_t *)(apic->int_en_reg + 20) = op_val;
789 *(uint32_t *)(apic->int_en_reg + 24) = op_val;
792 *(uint32_t *)(apic->int_en_reg + 28) = op_val;
802 case INT_CMD_LO_OFFSET:
803 case INT_CMD_HI_OFFSET:
804 // Unhandled Registers
805 case EXT_INT_LOC_VEC_TBL_OFFSET0:
806 case EXT_INT_LOC_VEC_TBL_OFFSET1:
807 case EXT_INT_LOC_VEC_TBL_OFFSET2:
808 case EXT_INT_LOC_VEC_TBL_OFFSET3:
809 case EXT_APIC_CMD_OFFSET:
812 PrintError("Write to Unhandled APIC Register: %x\n", (uint32_t)reg_addr);
816 PrintDebug("Write finished\n");
823 /* Interrupt Controller Functions */
825 // returns 1 if an interrupt is pending, 0 otherwise
826 static int apic_intr_pending(void * private_data) {
827 struct vm_device * dev = (struct vm_device *)private_data;
828 struct apic_state * apic = (struct apic_state *)dev->private_data;
829 int req_irq = get_highest_irr(apic);
830 int svc_irq = get_highest_isr(apic);
832 if ((req_irq >= 0) &&
833 (req_irq > svc_irq)) {
840 static int apic_get_intr_number(void * private_data) {
841 struct vm_device * dev = (struct vm_device *)private_data;
842 struct apic_state * apic = (struct apic_state *)dev->private_data;
843 int req_irq = get_highest_irr(apic);
844 int svc_irq = get_highest_isr(apic);
848 } else if (svc_irq < req_irq) {
855 static int apic_raise_intr(void * private_data, int irq) {
857 // The Seastar is connected directly to the LAPIC via LINT0 on the ICC bus
860 struct vm_device * dev = (struct vm_device *)private_data;
861 struct apic_state * apic = (struct apic_state *)dev->private_data;
863 return activate_apic_irq(apic, irq);
869 static int apic_lower_intr(void * private_data, int irq) {
873 static int apic_begin_irq(void * private_data, int irq) {
874 struct vm_device * dev = (struct vm_device *)private_data;
875 struct apic_state * apic = (struct apic_state *)dev->private_data;
876 int major_offset = (irq & ~0x00000007) >> 3;
877 int minor_offset = irq & 0x00000007;
878 uchar_t * req_location = apic->int_req_reg + major_offset;
879 uchar_t * svc_location = apic->int_svc_reg + major_offset;
880 uchar_t flag = 0x01 << minor_offset;
882 *svc_location |= flag;
883 *req_location &= ~flag;
886 if ((irq == 238) || (irq == 239)) {
887 PrintError("APIC: Begin IRQ %d (ISR=%x), (IRR=%x)\n", irq, *svc_location, *req_location);
896 int v3_apic_raise_intr(struct vm_device * apic_dev, int intr_num) {
897 struct apic_state * apic = (struct apic_state *)apic_dev->private_data;
898 return activate_apic_irq(apic, intr_num);
903 /* Timer Functions */
904 static void apic_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * priv_data) {
905 struct vm_device * dev = (struct vm_device *)priv_data;
906 struct apic_state * apic = (struct apic_state *)dev->private_data;
907 // The 32 bit GCC runtime is a pile of shit
909 uint64_t tmr_ticks = 0;
911 uint32_t tmr_ticks = 0;
914 uchar_t tmr_div = *(uchar_t *)&(apic->tmr_div_cfg.val);
915 uint_t shift_num = 0;
918 // Check whether this is true:
919 // -> If the Init count is zero then the timer is disabled
920 // and doesn't just blitz interrupts to the CPU
921 if ((apic->tmr_init_cnt == 0) ||
922 ( (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_ONESHOT) &&
923 (apic->tmr_cur_cnt == 0))) {
924 //PrintDebug("APIC timer not yet initialized\n");
951 case APIC_TMR_DIV128:
955 PrintError("Invalid Timer Divider configuration\n");
959 tmr_ticks = cpu_cycles >> shift_num;
960 PrintDebug("Timer Ticks: %p\n", (void *)tmr_ticks);
962 if (tmr_ticks < apic->tmr_cur_cnt) {
963 apic->tmr_cur_cnt -= tmr_ticks;
965 tmr_ticks -= apic->tmr_cur_cnt;
966 apic->tmr_cur_cnt = 0;
969 PrintDebug("Raising APIC Timer interrupt (periodic=%d) (icnt=%d) (div=%d)\n",
970 apic->tmr_vec_tbl.tmr_mode, apic->tmr_init_cnt, shift_num);
972 if (activate_internal_irq(apic, APIC_TMR_INT) == -1) {
973 PrintError("Could not raise Timer interrupt\n");
976 if (apic->tmr_vec_tbl.tmr_mode == APIC_TMR_PERIODIC) {
977 tmr_ticks = tmr_ticks % apic->tmr_init_cnt;
978 apic->tmr_cur_cnt = apic->tmr_init_cnt - tmr_ticks;
987 static struct intr_ctrl_ops intr_ops = {
988 .intr_pending = apic_intr_pending,
989 .get_intr_number = apic_get_intr_number,
990 .raise_intr = apic_raise_intr,
991 .begin_irq = apic_begin_irq,
992 .lower_intr = apic_lower_intr,
996 static struct vm_timer_ops timer_ops = {
997 .update_time = apic_update_time,
1001 static int apic_init(struct vm_device * dev) {
1002 struct guest_info * info = dev->vm;
1003 struct apic_state * apic = (struct apic_state *)(dev->private_data);
1005 v3_register_intr_controller(dev->vm, &intr_ops, dev);
1006 v3_add_timer(dev->vm, &timer_ops, dev);
1008 init_apic_state(apic);
1010 v3_hook_msr(info, BASE_ADDR_MSR, read_apic_msr, write_apic_msr, dev);
1012 v3_hook_full_mem(info, apic->base_addr, apic->base_addr + PAGE_SIZE_4KB, apic_read, apic_write, dev);
1017 static int apic_deinit(struct vm_device * dev) {
1018 struct guest_info * info = dev->vm;
1020 v3_unhook_msr(info, BASE_ADDR_MSR);
1026 static struct vm_device_ops dev_ops = {
1028 .deinit = apic_deinit,
1035 struct vm_device * v3_create_apic() {
1036 PrintDebug("Creating APIC\n");
1038 struct apic_state * apic = (struct apic_state *)V3_Malloc(sizeof(struct apic_state));
1040 struct vm_device * device = v3_create_device("APIC", &dev_ops, apic);