1 /* Northwestern University */
2 /* (c) 2008, Jack Lange <jarusl@cs.northwestern.edu> */
4 #include <devices/8259a.h>
5 #include <palacios/vmm_intr.h>
6 #include <palacios/vmm_types.h>
7 #include <palacios/vmm.h>
11 #define PrintDebug(fmt, args...)
15 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
17 static const uint_t MASTER_PORT1 = 0x20;
18 static const uint_t MASTER_PORT2 = 0x21;
19 static const uint_t SLAVE_PORT1 = 0xA0;
20 static const uint_t SLAVE_PORT2 = 0xA1;
22 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
23 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
24 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
28 uint_t ic4 : 1; // ICW4 has to be read
29 uint_t sngl : 1; // single (only one PIC)
30 uint_t adi : 1; // call address interval
31 uint_t ltim : 1; // level interrupt mode
43 // Each bit that is set indicates that the IR input has a slave
55 // The ID is the Slave device ID
62 uint_t uPM : 1; // 1=x86
63 uint_t AEOI : 1; // Automatic End of Interrupt
64 uint_t M_S : 1; // only if buffered 1=master,0=slave
65 uint_t BUF : 1; // buffered mode
66 uint_t SFNM : 1; // special fully nexted mode
84 uint_t cw_code : 2; // should be 00
94 uint_t cw_code : 2; // should be 01
101 struct pic_internal {
129 pic_state_t master_state;
130 pic_state_t slave_state;
134 static void DumpPICState(struct pic_internal *p)
137 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
138 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
139 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
140 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
142 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
143 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
145 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
146 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
147 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
148 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
150 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
151 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
152 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
153 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
155 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
156 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
158 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
159 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
160 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
161 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
166 static int pic_raise_intr(void * private_data, int irq) {
167 struct pic_internal * state = (struct pic_internal*)private_data;
171 state->master_irr |= 0x04; // PAD
174 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq);
177 state->master_irr |= 0x01 << irq;
178 } else if ((irq > 7) && (irq < 16)) {
179 state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq
181 PrintError("8259 PIC: Invalid IRQ raised (%d)\n", irq);
191 static int pic_lower_intr(void *private_data, int irq_no) {
193 struct pic_internal *state = (struct pic_internal*)private_data;
195 PrintDebug("[pic_lower_intr] IRQ line %d now low\n", (unsigned) irq_no);
198 state->master_irr &= ~(1 << irq_no);
199 if ((state->master_irr & ~(state->master_imr)) == 0) {
200 PrintDebug("\t\tFIXME: Master maybe should do sth\n");
202 } else if ((irq_no > 7) && (irq_no <= 15)) {
204 state->slave_irr &= ~(1 << (irq_no - 8));
205 if ((state->slave_irr & (~(state->slave_imr))) == 0) {
206 PrintDebug("\t\tFIXME: Slave maybe should do sth\n");
214 static int pic_intr_pending(void * private_data) {
215 struct pic_internal * state = (struct pic_internal*)private_data;
217 if ((state->master_irr & ~(state->master_imr)) ||
218 (state->slave_irr & ~(state->slave_imr))) {
225 static int pic_get_intr_number(void * private_data) {
226 struct pic_internal * state = (struct pic_internal *)private_data;
230 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", i, state->master_irr, state->master_imr);
231 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", i, state->slave_irr, state->slave_imr);
233 for (i = 0; i < 16; i++) {
235 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
236 //state->master_isr |= (0x1 << i);
238 //state->master_irr &= ~(0x1 << i);
239 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
240 irq= i + state->master_icw2;
244 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
245 //state->slave_isr |= (0x1 << (i - 8));
246 //state->slave_irr &= ~(0x1 << (i - 8));
247 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
248 irq= (i - 8) + state->slave_icw2;
254 if ((i == 15) || (i == 6)) {
267 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
268 static int pic_begin_irq(void * private_data, int irq) {
269 struct pic_internal * state = (struct pic_internal*)private_data;
271 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
273 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
277 PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
282 if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
283 state->master_isr |= (0x1 << irq);
284 state->master_irr &= ~(0x1 << irq);
287 state->slave_isr |= (0x1 << (irq - 8));
288 state->slave_irr &= ~(0x1 << (irq - 8));
296 static int pic_end_irq(void * private_data, int irq) {
303 static struct intr_ctrl_ops intr_ops = {
304 .intr_pending = pic_intr_pending,
305 .get_intr_number = pic_get_intr_number,
306 .raise_intr = pic_raise_intr,
307 .begin_irq = pic_begin_irq,
308 .lower_intr = pic_lower_intr, //Zheng added
315 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
316 struct pic_internal * state = (struct pic_internal*)dev->private_data;
319 PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
323 if ((state->master_ocw3 & 0x03) == 0x02) {
324 *(uchar_t *)dst = state->master_irr;
325 } else if ((state->master_ocw3 & 0x03) == 0x03) {
326 *(uchar_t *)dst = state->master_isr;
334 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
335 struct pic_internal * state = (struct pic_internal*)dev->private_data;
338 PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
342 *(uchar_t *)dst = state->master_imr;
348 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
349 struct pic_internal * state = (struct pic_internal*)dev->private_data;
352 PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
356 if ((state->slave_ocw3 & 0x03) == 0x02) {
357 *(uchar_t*)dst = state->slave_irr;
358 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
359 *(uchar_t *)dst = state->slave_isr;
367 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
368 struct pic_internal * state = (struct pic_internal*)dev->private_data;
371 PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
375 *(uchar_t *)dst = state->slave_imr;
381 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
382 struct pic_internal * state = (struct pic_internal*)dev->private_data;
383 uchar_t cw = *(uchar_t *)src;
385 PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
388 PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
394 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
396 state->master_icw1 = cw;
397 state->master_state = ICW2;
399 } else if (state->master_state == READY) {
401 // handle the EOI here
402 struct ocw2 * cw2 = (struct ocw2*)&cw;
404 PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
406 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
408 state->master_isr &= ~(0x01 << cw2->level);
409 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
412 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
413 for (i = 0; i < 8; i++) {
414 if (state->master_isr & (0x01 << i)) {
415 state->master_isr &= ~(0x01 << i);
419 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
421 PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
425 state->master_ocw2 = cw;
426 } else if (IS_OCW3(cw)) {
427 PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
428 state->master_ocw3 = cw;
430 PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
431 PrintError("8259 PIC: CW=%x\n", cw);
435 PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
436 PrintError("8259 PIC: CW=%x\n", cw);
443 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
444 struct pic_internal * state = (struct pic_internal*)dev->private_data;
445 uchar_t cw = *(uchar_t *)src;
447 PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
450 PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
454 if (state->master_state == ICW2) {
455 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
457 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
458 state->master_icw2 = cw;
460 if (cw1->sngl == 0) {
461 state->master_state = ICW3;
462 } else if (cw1->ic4 == 1) {
463 state->master_state = ICW4;
465 state->master_state = READY;
468 } else if (state->master_state == ICW3) {
469 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
471 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
473 state->master_icw3 = cw;
476 state->master_state = ICW4;
478 state->master_state = READY;
481 } else if (state->master_state == ICW4) {
482 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
483 state->master_icw4 = cw;
484 state->master_state = READY;
485 } else if (state->master_state == READY) {
486 PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
487 state->master_imr = cw;
490 PrintError("8259 PIC: Invalid master PIC State (wr_Master2)\n");
497 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
498 struct pic_internal * state = (struct pic_internal*)dev->private_data;
499 uchar_t cw = *(uchar_t *)src;
501 PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
505 PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
510 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
511 state->slave_icw1 = cw;
512 state->slave_state = ICW2;
513 } else if (state->slave_state == READY) {
515 // handle the EOI here
516 struct ocw2 * cw2 = (struct ocw2 *)&cw;
518 PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
520 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
522 state->slave_isr &= ~(0x01 << cw2->level);
523 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
526 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
527 for (i = 0; i < 8; i++) {
528 if (state->slave_isr & (0x01 << i)) {
529 state->slave_isr &= ~(0x01 << i);
533 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
535 PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
539 state->slave_ocw2 = cw;
540 } else if (IS_OCW3(cw)) {
541 // Basically sets the IRR/ISR read flag
542 PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
543 state->slave_ocw3 = cw;
545 PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
549 PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n");
556 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
557 struct pic_internal * state = (struct pic_internal*)dev->private_data;
558 uchar_t cw = *(uchar_t *)src;
560 PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
563 PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
567 if (state->slave_state == ICW2) {
568 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
570 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
572 state->slave_icw2 = cw;
574 if (cw1->sngl == 0) {
575 state->slave_state = ICW3;
576 } else if (cw1->ic4 == 1) {
577 state->slave_state = ICW4;
579 state->slave_state = READY;
582 } else if (state->slave_state == ICW3) {
583 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
585 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
587 state->slave_icw3 = cw;
590 state->slave_state = ICW4;
592 state->slave_state = READY;
595 } else if (state->slave_state == ICW4) {
596 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
597 state->slave_icw4 = cw;
598 state->slave_state = READY;
599 } else if (state->slave_state == READY) {
600 PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
601 state->slave_imr = cw;
603 PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
617 int pic_init(struct vm_device * dev) {
618 struct pic_internal * state = (struct pic_internal*)dev->private_data;
620 set_intr_controller(dev->vm, &intr_ops, state);
622 state->master_irr = 0;
623 state->master_isr = 0;
624 state->master_icw1 = 0;
625 state->master_icw2 = 0;
626 state->master_icw3 = 0;
627 state->master_icw4 = 0;
628 state->master_imr = 0;
629 state->master_ocw2 = 0;
630 state->master_ocw3 = 0x02;
631 state->master_state = ICW1;
634 state->slave_irr = 0;
635 state->slave_isr = 0;
636 state->slave_icw1 = 0;
637 state->slave_icw2 = 0;
638 state->slave_icw3 = 0;
639 state->slave_icw4 = 0;
640 state->slave_imr = 0;
641 state->slave_ocw2 = 0;
642 state->slave_ocw3 = 0x02;
643 state->slave_state = ICW1;
646 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
647 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
648 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
649 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
655 int pic_deinit(struct vm_device * dev) {
656 dev_unhook_io(dev, MASTER_PORT1);
657 dev_unhook_io(dev, MASTER_PORT2);
658 dev_unhook_io(dev, SLAVE_PORT1);
659 dev_unhook_io(dev, SLAVE_PORT2);
670 static struct vm_device_ops dev_ops = {
672 .deinit = pic_deinit,
679 struct vm_device * create_pic() {
680 struct pic_internal * state = NULL;
681 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
682 V3_ASSERT(state != NULL);
684 struct vm_device *device = create_device("8259A", &dev_ops, state);