2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
22 #include <palacios/vmm_intr.h>
23 #include <palacios/vmm_types.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmm_dev_mgr.h>
27 #ifndef CONFIG_DEBUG_PIC
29 #define PrintDebug(fmt, args...)
33 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
35 static const uint_t MASTER_PORT1 = 0x20;
36 static const uint_t MASTER_PORT2 = 0x21;
37 static const uint_t SLAVE_PORT1 = 0xA0;
38 static const uint_t SLAVE_PORT2 = 0xA1;
40 static const uint_t ELCR1_PORT = 0x4d0;
41 static const uint_t ELCR2_PORT = 0x4d1;
44 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
45 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
46 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
50 uint_t ic4 : 1; // ICW4 has to be read
51 uint_t sngl : 1; // single (only one PIC)
52 uint_t adi : 1; // call address interval
53 uint_t ltim : 1; // level interrupt mode
65 // Each bit that is set indicates that the IR input has a slave
77 // The ID is the Slave device ID
84 uint_t uPM : 1; // 1=x86
85 uint_t AEOI : 1; // Automatic End of Interrupt
86 uint_t M_S : 1; // only if buffered 1=master,0=slave
87 uint_t BUF : 1; // buffered mode
88 uint_t SFNM : 1; // special fully nexted mode
106 uint_t cw_code : 2; // should be 00
116 uint_t cw_code : 2; // should be 01
123 struct pic_internal {
134 uchar_t master_elcr_mask;
135 uchar_t slave_elcr_mask;
156 pic_state_t master_state;
157 pic_state_t slave_state;
161 static void DumpPICState(struct pic_internal *p)
164 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
165 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
166 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
167 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
169 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
170 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
172 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
173 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
174 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
175 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
177 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
178 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
179 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
180 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
182 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
183 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
185 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
186 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
187 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
188 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
193 static int pic_raise_intr(struct v3_vm_info * vm, void * private_data, int irq) {
194 struct pic_internal * state = (struct pic_internal*)private_data;
198 state->master_irr |= 0x04; // PAD
201 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq);
204 state->master_irr |= 0x01 << irq;
205 } else if ((irq > 7) && (irq < 16)) {
206 state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq
208 PrintDebug("8259 PIC: Invalid IRQ raised (%d)\n", irq);
212 v3_interrupt_cpu(vm, 0, 0);
218 static int pic_lower_intr(struct v3_vm_info * vm, void * private_data, int irq) {
219 struct pic_internal * state = (struct pic_internal*)private_data;
221 PrintDebug("[pic_lower_intr] IRQ line %d now low\n", irq);
224 state->master_irr &= ~(1 << irq);
225 if ((state->master_irr & ~(state->master_imr)) == 0) {
226 PrintDebug("\t\tFIXME: Master maybe should do sth\n");
228 } else if ((irq > 7) && (irq < 16)) {
230 state->slave_irr &= ~(1 << (irq - 8));
231 if ((state->slave_irr & (~(state->slave_imr))) == 0) {
232 PrintDebug("\t\tFIXME: Slave maybe should do sth\n");
240 static int pic_intr_pending(struct guest_info * info, void * private_data) {
241 struct pic_internal * state = (struct pic_internal*)private_data;
243 if ((state->master_irr & ~(state->master_imr)) ||
244 (state->slave_irr & ~(state->slave_imr))) {
251 static int pic_get_intr_number(struct guest_info * info, void * private_data) {
252 struct pic_internal * state = (struct pic_internal *)private_data;
256 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", state->master_irr, state->master_imr);
257 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", state->slave_irr, state->slave_imr);
259 for (i = 0; i < 16; i++) {
261 if (((state->master_irr & ~(state->master_imr)) >> i) & 0x01) {
262 //state->master_isr |= (0x1 << i);
264 //state->master_irr &= ~(0x1 << i);
265 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
266 irq = i + state->master_icw2;
270 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) & 0x01) {
271 //state->slave_isr |= (0x1 << (i - 8));
272 //state->slave_irr &= ~(0x1 << (i - 8));
273 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
274 irq = (i - 8) + state->slave_icw2;
280 if ((i == 15) || (i == 6)) {
293 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
294 static int pic_begin_irq(struct guest_info * info, void * private_data, int irq) {
295 struct pic_internal * state = (struct pic_internal*)private_data;
297 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
299 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
303 // PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
308 // This should always be true: See pic_get_intr_number
309 if (((state->master_irr & ~(state->master_imr)) >> irq) & 0x01) {
310 state->master_isr |= (0x1 << irq);
312 if (!(state->master_elcr & (0x1 << irq))) {
313 state->master_irr &= ~(0x1 << irq);
317 // This should always be true: See pic_get_intr_number
318 if (((state->slave_irr & ~(state->slave_imr)) >> (irq - 8)) & 0x01) {
319 state->slave_isr |= (0x1 << (irq - 8));
321 if (!(state->slave_elcr & (0x1 << (irq - 8)))) {
322 state->slave_irr &= ~(0x1 << (irq - 8));
332 static int pic_end_irq(void * private_data, int irq) {
339 static struct intr_ctrl_ops intr_ops = {
340 .intr_pending = pic_intr_pending,
341 .get_intr_number = pic_get_intr_number,
342 .begin_irq = pic_begin_irq
345 static struct intr_router_ops router_ops = {
346 .raise_intr = pic_raise_intr,
347 .lower_intr = pic_lower_intr
351 static int read_master_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
352 struct pic_internal * state = (struct pic_internal*)dev->private_data;
355 PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
359 if ((state->master_ocw3 & 0x03) == 0x02) {
360 *(uchar_t *)dst = state->master_irr;
361 } else if ((state->master_ocw3 & 0x03) == 0x03) {
362 *(uchar_t *)dst = state->master_isr;
370 static int read_master_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
371 struct pic_internal * state = (struct pic_internal*)dev->private_data;
374 PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
378 *(uchar_t *)dst = state->master_imr;
384 static int read_slave_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
385 struct pic_internal * state = (struct pic_internal*)dev->private_data;
388 PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
392 if ((state->slave_ocw3 & 0x03) == 0x02) {
393 *(uchar_t*)dst = state->slave_irr;
394 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
395 *(uchar_t *)dst = state->slave_isr;
403 static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
404 struct pic_internal * state = (struct pic_internal*)dev->private_data;
407 PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
411 *(uchar_t *)dst = state->slave_imr;
417 static int write_master_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
418 struct pic_internal * state = (struct pic_internal*)dev->private_data;
419 uchar_t cw = *(uchar_t *)src;
421 PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
424 PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
428 v3_clear_pending_intr(core);
432 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
434 state->master_icw1 = cw;
435 state->master_state = ICW2;
437 } else if (state->master_state == READY) {
439 // handle the EOI here
440 struct ocw2 * cw2 = (struct ocw2*)&cw;
442 PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
444 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
446 state->master_isr &= ~(0x01 << cw2->level);
447 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
450 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
451 for (i = 0; i < 8; i++) {
452 if (state->master_isr & (0x01 << i)) {
453 state->master_isr &= ~(0x01 << i);
457 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
459 PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
463 state->master_ocw2 = cw;
464 } else if (IS_OCW3(cw)) {
465 PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
466 state->master_ocw3 = cw;
468 PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
469 PrintError("8259 PIC: CW=%x\n", cw);
473 PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
474 PrintError("8259 PIC: CW=%x\n", cw);
481 static int write_master_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
482 struct pic_internal * state = (struct pic_internal*)dev->private_data;
483 uchar_t cw = *(uchar_t *)src;
485 PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
488 PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
492 v3_clear_pending_intr(core);
494 if (state->master_state == ICW2) {
495 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
497 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
498 state->master_icw2 = cw;
502 if (cw1->sngl == 0) {
503 state->master_state = ICW3;
504 } else if (cw1->ic4 == 1) {
505 state->master_state = ICW4;
507 state->master_state = READY;
512 } else if (state->master_state == ICW3) {
513 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
515 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
517 state->master_icw3 = cw;
520 state->master_state = ICW4;
522 state->master_state = READY;
525 } else if (state->master_state == ICW4) {
526 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
527 state->master_icw4 = cw;
528 state->master_state = READY;
529 } else if ((state->master_state == ICW1) || (state->master_state == READY)) {
530 PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
531 state->master_imr = cw;
534 PrintError("8259 PIC: Invalid master PIC State (wr_Master2) (state=%d)\n",
535 state->master_state);
542 static int write_slave_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
543 struct pic_internal * state = (struct pic_internal*)dev->private_data;
544 uchar_t cw = *(uchar_t *)src;
546 PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
550 PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
554 v3_clear_pending_intr(core);
557 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
558 state->slave_icw1 = cw;
559 state->slave_state = ICW2;
560 } else if (state->slave_state == READY) {
562 // handle the EOI here
563 struct ocw2 * cw2 = (struct ocw2 *)&cw;
565 PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
567 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
569 state->slave_isr &= ~(0x01 << cw2->level);
570 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
573 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
574 for (i = 0; i < 8; i++) {
575 if (state->slave_isr & (0x01 << i)) {
576 state->slave_isr &= ~(0x01 << i);
580 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
582 PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
586 state->slave_ocw2 = cw;
587 } else if (IS_OCW3(cw)) {
588 // Basically sets the IRR/ISR read flag
589 PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
590 state->slave_ocw3 = cw;
592 PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
596 PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n");
603 static int write_slave_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
604 struct pic_internal * state = (struct pic_internal*)dev->private_data;
605 uchar_t cw = *(uchar_t *)src;
607 PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
610 PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
614 v3_clear_pending_intr(core);
617 if (state->slave_state == ICW2) {
618 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
620 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
622 state->slave_icw2 = cw;
624 if (cw1->sngl == 0) {
625 state->slave_state = ICW3;
626 } else if (cw1->ic4 == 1) {
627 state->slave_state = ICW4;
629 state->slave_state = READY;
632 } else if (state->slave_state == ICW3) {
633 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
635 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
637 state->slave_icw3 = cw;
640 state->slave_state = ICW4;
642 state->slave_state = READY;
645 } else if (state->slave_state == ICW4) {
646 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
647 state->slave_icw4 = cw;
648 state->slave_state = READY;
649 } else if ((state->slave_state == ICW1) || (state->slave_state == READY)) {
650 PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
651 state->slave_imr = cw;
653 PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
663 static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
664 struct pic_internal * state = (struct pic_internal*)dev->private_data;
667 PrintError("ELCR read of invalid length %d\n", length);
671 if (port == ELCR1_PORT) {
673 *(uint8_t *)dst = state->master_elcr;
674 } else if (port == ELCR2_PORT) {
675 *(uint8_t *)dst = state->slave_elcr;
677 PrintError("Invalid port %x\n", port);
685 static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, uint_t length, struct vm_device * dev) {
686 struct pic_internal * state = (struct pic_internal*)dev->private_data;
689 PrintError("ELCR read of invalid length %d\n", length);
693 if (port == ELCR1_PORT) {
695 state->master_elcr = (*(uint8_t *)src) & state->master_elcr_mask;
696 } else if (port == ELCR2_PORT) {
697 state->slave_elcr = (*(uint8_t *)src) & state->slave_elcr_mask;
699 PrintError("Invalid port %x\n", port);
711 static int pic_free(struct vm_device * dev) {
712 v3_dev_unhook_io(dev, MASTER_PORT1);
713 v3_dev_unhook_io(dev, MASTER_PORT2);
714 v3_dev_unhook_io(dev, SLAVE_PORT1);
715 v3_dev_unhook_io(dev, SLAVE_PORT2);
726 static struct v3_device_ops dev_ops = {
735 #include <palacios/vm_guest.h>
737 static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
738 struct pic_internal * state = NULL;
739 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
740 char * name = v3_cfg_val(cfg, "name");
742 // PIC is only usable in non-multicore environments
743 // just hardcode the core context
744 struct guest_info * core = &(vm->cores[0]);
746 V3_ASSERT(state != NULL);
748 struct vm_device * dev = v3_allocate_device(name, &dev_ops, state);
750 if (v3_attach_device(vm, dev) == -1) {
751 PrintError("Could not attach device %s\n", name);
756 v3_register_intr_controller(core, &intr_ops, state);
757 v3_register_intr_router(vm, &router_ops, state);
759 state->master_irr = 0;
760 state->master_isr = 0;
761 state->master_elcr = 0;
762 state->master_elcr_mask = 0xf8;
763 state->master_icw1 = 0;
764 state->master_icw2 = 0;
765 state->master_icw3 = 0;
766 state->master_icw4 = 0;
767 state->master_imr = 0;
768 state->master_ocw2 = 0;
769 state->master_ocw3 = 0x02;
770 state->master_state = ICW1;
773 state->slave_irr = 0;
774 state->slave_isr = 0;
775 state->slave_elcr = 0;
776 state->slave_elcr_mask = 0xde;
777 state->slave_icw1 = 0;
778 state->slave_icw2 = 0;
779 state->slave_icw3 = 0;
780 state->slave_icw4 = 0;
781 state->slave_imr = 0;
782 state->slave_ocw2 = 0;
783 state->slave_ocw3 = 0x02;
784 state->slave_state = ICW1;
787 v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
788 v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
789 v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
790 v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
793 v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
794 v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
801 device_register("8259A", pic_init);