1 #include <devices/8259a.h>
2 #include <palacios/vmm_intr.h>
3 #include <palacios/vmm_types.h>
4 #include <palacios/vmm.h>
8 #define PrintDebug(fmt, args...)
11 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
13 static const uint_t MASTER_PORT1 = 0x20;
14 static const uint_t MASTER_PORT2 = 0x21;
15 static const uint_t SLAVE_PORT1 = 0xA0;
16 static const uint_t SLAVE_PORT2 = 0xA1;
18 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
19 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
20 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
24 uint_t ic4 : 1; // ICW4 has to be read
25 uint_t sngl : 1; // single (only one PIC)
26 uint_t adi : 1; // call address interval
27 uint_t ltim : 1; // level interrupt mode
39 // Each bit that is set indicates that the IR input has a slave
51 // The ID is the Slave device ID
58 uint_t uPM : 1; // 1=x86
59 uint_t AEOI : 1; // Automatic End of Interrupt
60 uint_t M_S : 1; // only if buffered 1=master,0=slave
61 uint_t BUF : 1; // buffered mode
62 uint_t SFNM : 1; // special fully nexted mode
80 uint_t cw_code : 2; // should be 00
90 uint_t cw_code : 2; // should be 01
125 pic_state_t master_state;
126 pic_state_t slave_state;
130 static void DumpPICState(struct pic_internal *p)
133 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
134 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
135 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
136 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
138 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
139 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
141 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
142 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
143 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
144 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
146 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
147 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
148 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
149 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
151 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
152 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
154 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
155 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
156 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
157 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
162 static int pic_raise_intr(void * private_data, int irq) {
163 struct pic_internal * state = (struct pic_internal*)private_data;
167 state->master_irr |= 0x04; // PAD
170 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq);
173 state->master_irr |= 0x01 << irq;
174 } else if ((irq > 7) && (irq < 16)) {
175 state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq
177 PrintError("8259 PIC: Invalid IRQ raised (%d)\n", irq);
184 static int pic_intr_pending(void * private_data) {
185 struct pic_internal * state = (struct pic_internal*)private_data;
187 if ((state->master_irr & ~(state->master_imr)) ||
188 (state->slave_irr & ~(state->slave_imr))) {
195 static int pic_get_intr_number(void * private_data) {
196 struct pic_internal * state = (struct pic_internal*)private_data;
200 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", i, state->master_irr, state->master_imr);
201 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", i, state->slave_irr, state->slave_imr);
203 for (i = 0; i < 16; i++) {
205 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
206 //state->master_isr |= (0x1 << i);
208 //state->master_irr &= ~(0x1 << i);
209 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
210 irq= i + state->master_icw2;
214 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
215 //state->slave_isr |= (0x1 << (i - 8));
216 //state->slave_irr &= ~(0x1 << (i - 8));
217 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
218 irq= (i - 8) + state->slave_icw2;
237 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
238 static int pic_begin_irq(void * private_data, int irq) {
239 struct pic_internal * state = (struct pic_internal*)private_data;
241 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
243 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
247 PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
252 if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
253 state->master_isr |= (0x1 << irq);
254 state->master_irr &= ~(0x1 << irq);
257 state->slave_isr |= (0x1 << (irq - 8));
258 state->slave_irr &= ~(0x1 << (irq - 8));
266 static int pic_end_irq(void * private_data, int irq) {
271 static struct intr_ctrl_ops intr_ops = {
272 .intr_pending = pic_intr_pending,
273 .get_intr_number = pic_get_intr_number,
274 .raise_intr = pic_raise_intr,
275 .begin_irq = pic_begin_irq,
281 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
282 struct pic_internal * state = (struct pic_internal*)dev->private_data;
285 PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
289 if ((state->master_ocw3 & 0x03) == 0x02) {
290 *(uchar_t *)dst = state->master_irr;
291 } else if ((state->master_ocw3 & 0x03) == 0x03) {
292 *(uchar_t *)dst = state->master_isr;
300 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
301 struct pic_internal * state = (struct pic_internal*)dev->private_data;
304 PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
308 *(uchar_t *)dst = state->master_imr;
314 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
315 struct pic_internal * state = (struct pic_internal*)dev->private_data;
318 PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
322 if ((state->slave_ocw3 & 0x03) == 0x02) {
323 *(uchar_t*)dst = state->slave_irr;
324 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
325 *(uchar_t *)dst = state->slave_isr;
333 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
334 struct pic_internal * state = (struct pic_internal*)dev->private_data;
337 PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
341 *(uchar_t *)dst = state->slave_imr;
347 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
348 struct pic_internal * state = (struct pic_internal*)dev->private_data;
349 uchar_t cw = *(uchar_t *)src;
351 PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
354 PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
360 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
362 state->master_icw1 = cw;
363 state->master_state = ICW2;
365 } else if (state->master_state == READY) {
367 // handle the EOI here
368 struct ocw2 * cw2 = (struct ocw2*)&cw;
370 PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
372 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
374 state->master_isr &= ~(0x01 << cw2->level);
375 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
378 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
379 for (i = 0; i < 8; i++) {
380 if (state->master_isr & (0x01 << i)) {
381 state->master_isr &= ~(0x01 << i);
385 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
387 PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
391 state->master_ocw2 = cw;
392 } else if (IS_OCW3(cw)) {
393 PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
394 state->master_ocw3 = cw;
396 PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
397 PrintError("8259 PIC: CW=%x\n", cw);
401 PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
402 PrintError("8259 PIC: CW=%x\n", cw);
409 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
410 struct pic_internal * state = (struct pic_internal*)dev->private_data;
411 uchar_t cw = *(uchar_t *)src;
413 PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
416 PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
420 if (state->master_state == ICW2) {
421 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
423 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
424 state->master_icw2 = cw;
426 if (cw1->sngl == 0) {
427 state->master_state = ICW3;
428 } else if (cw1->ic4 == 1) {
429 state->master_state = ICW4;
431 state->master_state = READY;
434 } else if (state->master_state == ICW3) {
435 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
437 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
439 state->master_icw3 = cw;
442 state->master_state = ICW4;
444 state->master_state = READY;
447 } else if (state->master_state == ICW4) {
448 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
449 state->master_icw4 = cw;
450 state->master_state = READY;
451 } else if (state->master_state == READY) {
452 PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
453 state->master_imr = cw;
456 PrintError("8259 PIC: Invalid master PIC State (wr_Master2)\n");
463 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
464 struct pic_internal * state = (struct pic_internal*)dev->private_data;
465 uchar_t cw = *(uchar_t *)src;
467 PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
471 PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
476 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
477 state->slave_icw1 = cw;
478 state->slave_state = ICW2;
479 } else if (state->slave_state == READY) {
481 // handle the EOI here
482 struct ocw2 * cw2 = (struct ocw2 *)&cw;
484 PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
486 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
488 state->slave_isr &= ~(0x01 << cw2->level);
489 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
492 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
493 for (i = 0; i < 8; i++) {
494 if (state->slave_isr & (0x01 << i)) {
495 state->slave_isr &= ~(0x01 << i);
499 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
501 PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
505 state->slave_ocw2 = cw;
506 } else if (IS_OCW3(cw)) {
507 // Basically sets the IRR/ISR read flag
508 PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
509 state->slave_ocw3 = cw;
511 PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
515 PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n");
522 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
523 struct pic_internal * state = (struct pic_internal*)dev->private_data;
524 uchar_t cw = *(uchar_t *)src;
526 PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
529 PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
533 if (state->slave_state == ICW2) {
534 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
536 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
538 state->slave_icw2 = cw;
540 if (cw1->sngl == 0) {
541 state->slave_state = ICW3;
542 } else if (cw1->ic4 == 1) {
543 state->slave_state = ICW4;
545 state->slave_state = READY;
548 } else if (state->slave_state == ICW3) {
549 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
551 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
553 state->slave_icw3 = cw;
556 state->slave_state = ICW4;
558 state->slave_state = READY;
561 } else if (state->slave_state == ICW4) {
562 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
563 state->slave_icw4 = cw;
564 state->slave_state = READY;
565 } else if (state->slave_state == READY) {
566 PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
567 state->slave_imr = cw;
569 PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
583 int pic_init(struct vm_device * dev) {
584 struct pic_internal * state = (struct pic_internal*)dev->private_data;
586 set_intr_controller(dev->vm, &intr_ops, state);
588 state->master_irr = 0;
589 state->master_isr = 0;
590 state->master_icw1 = 0;
591 state->master_icw2 = 0;
592 state->master_icw3 = 0;
593 state->master_icw4 = 0;
594 state->master_imr = 0;
595 state->master_ocw2 = 0;
596 state->master_ocw3 = 0x02;
597 state->master_state = ICW1;
600 state->slave_irr = 0;
601 state->slave_isr = 0;
602 state->slave_icw1 = 0;
603 state->slave_icw2 = 0;
604 state->slave_icw3 = 0;
605 state->slave_icw4 = 0;
606 state->slave_imr = 0;
607 state->slave_ocw2 = 0;
608 state->slave_ocw3 = 0x02;
609 state->slave_state = ICW1;
612 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
613 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
614 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
615 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
621 int pic_deinit(struct vm_device * dev) {
622 dev_unhook_io(dev, MASTER_PORT1);
623 dev_unhook_io(dev, MASTER_PORT2);
624 dev_unhook_io(dev, SLAVE_PORT1);
625 dev_unhook_io(dev, SLAVE_PORT2);
636 static struct vm_device_ops dev_ops = {
638 .deinit = pic_deinit,
645 struct vm_device * create_pic() {
646 struct pic_internal * state = NULL;
647 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
648 V3_ASSERT(state != NULL);
650 struct vm_device *device = create_device("8259A", &dev_ops, state);