2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
22 #include <palacios/vmm_intr.h>
23 #include <palacios/vmm_types.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmm_dev_mgr.h>
27 #ifndef CONFIG_DEBUG_PIC
29 #define PrintDebug(fmt, args...)
33 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
35 static const uint_t MASTER_PORT1 = 0x20;
36 static const uint_t MASTER_PORT2 = 0x21;
37 static const uint_t SLAVE_PORT1 = 0xA0;
38 static const uint_t SLAVE_PORT2 = 0xA1;
40 static const uint_t ELCR1_PORT = 0x4d0;
41 static const uint_t ELCR2_PORT = 0x4d1;
44 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
45 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
46 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
50 uint_t ic4 : 1; // ICW4 has to be read
51 uint_t sngl : 1; // single (only one PIC)
52 uint_t adi : 1; // call address interval
53 uint_t ltim : 1; // level interrupt mode
65 // Each bit that is set indicates that the IR input has a slave
77 // The ID is the Slave device ID
84 uint_t uPM : 1; // 1=x86
85 uint_t AEOI : 1; // Automatic End of Interrupt
86 uint_t M_S : 1; // only if buffered 1=master,0=slave
87 uint_t BUF : 1; // buffered mode
88 uint_t SFNM : 1; // special fully nexted mode
106 uint_t cw_code : 2; // should be 00
116 uint_t cw_code : 2; // should be 01
123 struct pic_internal {
134 uchar_t master_elcr_mask;
135 uchar_t slave_elcr_mask;
156 pic_state_t master_state;
157 pic_state_t slave_state;
161 static void DumpPICState(struct pic_internal *p)
164 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
165 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
166 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
167 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
169 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
170 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
172 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
173 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
174 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
175 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
177 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
178 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
179 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
180 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
182 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
183 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
185 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
186 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
187 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
188 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
193 static int pic_raise_intr(void * private_data, int irq) {
194 struct pic_internal * state = (struct pic_internal*)private_data;
198 state->master_irr |= 0x04; // PAD
201 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq);
204 state->master_irr |= 0x01 << irq;
205 } else if ((irq > 7) && (irq < 16)) {
206 state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq
208 PrintDebug("8259 PIC: Invalid IRQ raised (%d)\n", irq);
216 static int pic_lower_intr(void *private_data, int irq) {
218 struct pic_internal *state = (struct pic_internal*)private_data;
220 PrintDebug("[pic_lower_intr] IRQ line %d now low\n", irq);
223 state->master_irr &= ~(1 << irq);
224 if ((state->master_irr & ~(state->master_imr)) == 0) {
225 PrintDebug("\t\tFIXME: Master maybe should do sth\n");
227 } else if ((irq > 7) && (irq < 16)) {
229 state->slave_irr &= ~(1 << (irq - 8));
230 if ((state->slave_irr & (~(state->slave_imr))) == 0) {
231 PrintDebug("\t\tFIXME: Slave maybe should do sth\n");
239 static int pic_intr_pending(void * private_data) {
240 struct pic_internal * state = (struct pic_internal*)private_data;
242 if ((state->master_irr & ~(state->master_imr)) ||
243 (state->slave_irr & ~(state->slave_imr))) {
250 static int pic_get_intr_number(void * private_data) {
251 struct pic_internal * state = (struct pic_internal *)private_data;
255 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", state->master_irr, state->master_imr);
256 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", state->slave_irr, state->slave_imr);
258 for (i = 0; i < 16; i++) {
260 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
261 //state->master_isr |= (0x1 << i);
263 //state->master_irr &= ~(0x1 << i);
264 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
265 irq = i + state->master_icw2;
269 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
270 //state->slave_isr |= (0x1 << (i - 8));
271 //state->slave_irr &= ~(0x1 << (i - 8));
272 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
273 irq= (i - 8) + state->slave_icw2;
279 if ((i == 15) || (i == 6)) {
292 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
293 static int pic_begin_irq(void * private_data, int irq) {
294 struct pic_internal * state = (struct pic_internal*)private_data;
296 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
298 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
302 // PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
307 if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
308 state->master_isr |= (0x1 << irq);
310 if (!(state->master_elcr & (0x1 << irq))) {
311 state->master_irr &= ~(0x1 << irq);
315 state->slave_isr |= (0x1 << (irq - 8));
317 if (!(state->slave_elcr & (0x1 << irq))) {
318 state->slave_irr &= ~(0x1 << (irq - 8));
327 static int pic_end_irq(void * private_data, int irq) {
334 static struct intr_ctrl_ops intr_ops = {
335 .intr_pending = pic_intr_pending,
336 .get_intr_number = pic_get_intr_number,
337 .raise_intr = pic_raise_intr,
338 .begin_irq = pic_begin_irq,
339 .lower_intr = pic_lower_intr,
346 static int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
347 struct pic_internal * state = (struct pic_internal*)dev->private_data;
350 PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
354 if ((state->master_ocw3 & 0x03) == 0x02) {
355 *(uchar_t *)dst = state->master_irr;
356 } else if ((state->master_ocw3 & 0x03) == 0x03) {
357 *(uchar_t *)dst = state->master_isr;
365 static int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
366 struct pic_internal * state = (struct pic_internal*)dev->private_data;
369 PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
373 *(uchar_t *)dst = state->master_imr;
379 static int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
380 struct pic_internal * state = (struct pic_internal*)dev->private_data;
383 PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
387 if ((state->slave_ocw3 & 0x03) == 0x02) {
388 *(uchar_t*)dst = state->slave_irr;
389 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
390 *(uchar_t *)dst = state->slave_isr;
398 static int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
399 struct pic_internal * state = (struct pic_internal*)dev->private_data;
402 PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
406 *(uchar_t *)dst = state->slave_imr;
412 static int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
413 struct pic_internal * state = (struct pic_internal*)dev->private_data;
414 uchar_t cw = *(uchar_t *)src;
416 PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
419 PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
425 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
427 state->master_icw1 = cw;
428 state->master_state = ICW2;
430 } else if (state->master_state == READY) {
432 // handle the EOI here
433 struct ocw2 * cw2 = (struct ocw2*)&cw;
435 PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
437 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
439 state->master_isr &= ~(0x01 << cw2->level);
440 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
443 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
444 for (i = 0; i < 8; i++) {
445 if (state->master_isr & (0x01 << i)) {
446 state->master_isr &= ~(0x01 << i);
450 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
452 PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
456 state->master_ocw2 = cw;
457 } else if (IS_OCW3(cw)) {
458 PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
459 state->master_ocw3 = cw;
461 PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
462 PrintError("8259 PIC: CW=%x\n", cw);
466 PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
467 PrintError("8259 PIC: CW=%x\n", cw);
474 static int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
475 struct pic_internal * state = (struct pic_internal*)dev->private_data;
476 uchar_t cw = *(uchar_t *)src;
478 PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
481 PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
485 if (state->master_state == ICW2) {
486 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
488 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
489 state->master_icw2 = cw;
491 if (cw1->sngl == 0) {
492 state->master_state = ICW3;
493 } else if (cw1->ic4 == 1) {
494 state->master_state = ICW4;
496 state->master_state = READY;
499 } else if (state->master_state == ICW3) {
500 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
502 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
504 state->master_icw3 = cw;
507 state->master_state = ICW4;
509 state->master_state = READY;
512 } else if (state->master_state == ICW4) {
513 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
514 state->master_icw4 = cw;
515 state->master_state = READY;
516 } else if ((state->master_state == ICW1) || (state->master_state == READY)) {
517 PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
518 state->master_imr = cw;
521 PrintError("8259 PIC: Invalid master PIC State (wr_Master2) (state=%d)\n",
522 state->master_state);
529 static int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
530 struct pic_internal * state = (struct pic_internal*)dev->private_data;
531 uchar_t cw = *(uchar_t *)src;
533 PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
537 PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
542 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
543 state->slave_icw1 = cw;
544 state->slave_state = ICW2;
545 } else if (state->slave_state == READY) {
547 // handle the EOI here
548 struct ocw2 * cw2 = (struct ocw2 *)&cw;
550 PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
552 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
554 state->slave_isr &= ~(0x01 << cw2->level);
555 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
558 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
559 for (i = 0; i < 8; i++) {
560 if (state->slave_isr & (0x01 << i)) {
561 state->slave_isr &= ~(0x01 << i);
565 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
567 PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
571 state->slave_ocw2 = cw;
572 } else if (IS_OCW3(cw)) {
573 // Basically sets the IRR/ISR read flag
574 PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
575 state->slave_ocw3 = cw;
577 PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
581 PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n");
588 static int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
589 struct pic_internal * state = (struct pic_internal*)dev->private_data;
590 uchar_t cw = *(uchar_t *)src;
592 PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
595 PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
599 if (state->slave_state == ICW2) {
600 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
602 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
604 state->slave_icw2 = cw;
606 if (cw1->sngl == 0) {
607 state->slave_state = ICW3;
608 } else if (cw1->ic4 == 1) {
609 state->slave_state = ICW4;
611 state->slave_state = READY;
614 } else if (state->slave_state == ICW3) {
615 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
617 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
619 state->slave_icw3 = cw;
622 state->slave_state = ICW4;
624 state->slave_state = READY;
627 } else if (state->slave_state == ICW4) {
628 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
629 state->slave_icw4 = cw;
630 state->slave_state = READY;
631 } else if ((state->slave_state == ICW1) || (state->slave_state == READY)) {
632 PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
633 state->slave_imr = cw;
635 PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
645 static int read_elcr_port(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
646 struct pic_internal * state = (struct pic_internal*)dev->private_data;
649 PrintError("ELCR read of invalid length %d\n", length);
653 if (port == ELCR1_PORT) {
655 *(uint8_t *)dst = state->master_elcr;
656 } else if (port == ELCR2_PORT) {
657 *(uint8_t *)dst = state->slave_elcr;
659 PrintError("Invalid port %x\n", port);
667 static int write_elcr_port(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
668 struct pic_internal * state = (struct pic_internal*)dev->private_data;
671 PrintError("ELCR read of invalid length %d\n", length);
675 if (port == ELCR1_PORT) {
677 state->master_elcr = (*(uint8_t *)src) & state->master_elcr_mask;
678 } else if (port == ELCR2_PORT) {
679 state->slave_elcr = (*(uint8_t *)src) & state->slave_elcr_mask;
681 PrintError("Invalid port %x\n", port);
693 static int pic_free(struct vm_device * dev) {
694 v3_dev_unhook_io(dev, MASTER_PORT1);
695 v3_dev_unhook_io(dev, MASTER_PORT2);
696 v3_dev_unhook_io(dev, SLAVE_PORT1);
697 v3_dev_unhook_io(dev, SLAVE_PORT2);
708 static struct v3_device_ops dev_ops = {
717 static int pic_init(struct guest_info * vm, void * cfg_data) {
718 struct pic_internal * state = NULL;
719 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
720 V3_ASSERT(state != NULL);
722 struct vm_device * dev = v3_allocate_device("8259A", &dev_ops, state);
724 if (v3_attach_device(vm, dev) == -1) {
725 PrintError("Could not attach device %s\n", "8259A");
730 v3_register_intr_controller(vm, &intr_ops, state);
732 state->master_irr = 0;
733 state->master_isr = 0;
734 state->master_elcr = 0;
735 state->master_elcr_mask = 0xf8;
736 state->master_icw1 = 0;
737 state->master_icw2 = 0;
738 state->master_icw3 = 0;
739 state->master_icw4 = 0;
740 state->master_imr = 0;
741 state->master_ocw2 = 0;
742 state->master_ocw3 = 0x02;
743 state->master_state = ICW1;
746 state->slave_irr = 0;
747 state->slave_isr = 0;
748 state->slave_elcr = 0;
749 state->slave_elcr_mask = 0xde;
750 state->slave_icw1 = 0;
751 state->slave_icw2 = 0;
752 state->slave_icw3 = 0;
753 state->slave_icw4 = 0;
754 state->slave_imr = 0;
755 state->slave_ocw2 = 0;
756 state->slave_ocw3 = 0x02;
757 state->slave_state = ICW1;
760 v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
761 v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
762 v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
763 v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
766 v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
767 v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
774 device_register("8259A", pic_init);