1 #include <devices/8259a.h>
2 #include <palacios/vmm_intr.h>
3 #include <palacios/vmm_types.h>
4 #include <palacios/vmm.h>
8 #define PrintDebug(fmt, args...)
12 #define Ramdisk_Print_Pic(_f, _a...) PrintTrace("\n8259a.c(%d) "_f, __LINE__, ## _a)
14 #define Ramdisk_Print_Pic(_f, _a...)
18 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
20 static const uint_t MASTER_PORT1 = 0x20;
21 static const uint_t MASTER_PORT2 = 0x21;
22 static const uint_t SLAVE_PORT1 = 0xA0;
23 static const uint_t SLAVE_PORT2 = 0xA1;
25 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
26 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
27 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
31 uint_t ic4 : 1; // ICW4 has to be read
32 uint_t sngl : 1; // single (only one PIC)
33 uint_t adi : 1; // call address interval
34 uint_t ltim : 1; // level interrupt mode
46 // Each bit that is set indicates that the IR input has a slave
58 // The ID is the Slave device ID
65 uint_t uPM : 1; // 1=x86
66 uint_t AEOI : 1; // Automatic End of Interrupt
67 uint_t M_S : 1; // only if buffered 1=master,0=slave
68 uint_t BUF : 1; // buffered mode
69 uint_t SFNM : 1; // special fully nexted mode
87 uint_t cw_code : 2; // should be 00
97 uint_t cw_code : 2; // should be 01
104 struct pic_internal {
132 pic_state_t master_state;
133 pic_state_t slave_state;
137 static void DumpPICState(struct pic_internal *p)
140 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
141 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
142 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
143 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
145 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
146 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
148 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
149 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
150 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
151 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
153 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
154 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
155 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
156 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
158 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
159 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
161 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
162 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
163 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
164 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
169 static int pic_raise_intr(void * private_data, int irq) {
170 struct pic_internal * state = (struct pic_internal*)private_data;
174 state->master_irr |= 0x04; // PAD
177 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq);
180 state->master_irr |= 0x01 << irq;
181 } else if ((irq > 7) && (irq < 16)) {
182 state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq
184 PrintError("8259 PIC: Invalid IRQ raised (%d)\n", irq);
194 static int pic_lower_intr(void *private_data, int irq_no) {
196 struct pic_internal *state = (struct pic_internal*)private_data;
198 Ramdisk_Print_Pic("[pic_lower_intr] IRQ line %d now low\n", (unsigned) irq_no);
201 state->master_irr &= ~(1 << irq_no);
202 if ((state->master_irr & ~(state->master_imr)) == 0) {
203 Ramdisk_Print_Pic("\t\tFIXME: Master maybe should do sth\n");
205 } else if ((irq_no > 7) && (irq_no <= 15)) {
207 state->slave_irr &= ~(1 << (irq_no - 8));
208 if ((state->slave_irr & (~(state->slave_imr))) == 0) {
209 Ramdisk_Print_Pic("\t\tFIXME: Slave maybe should do sth\n");
217 static int pic_intr_pending(void * private_data) {
218 struct pic_internal * state = (struct pic_internal*)private_data;
220 if ((state->master_irr & ~(state->master_imr)) ||
221 (state->slave_irr & ~(state->slave_imr))) {
228 static int pic_get_intr_number(void * private_data) {
229 struct pic_internal * state = (struct pic_internal*)private_data;
233 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", i, state->master_irr, state->master_imr);
234 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", i, state->slave_irr, state->slave_imr);
236 for (i = 0; i < 16; i++) {
238 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
239 //state->master_isr |= (0x1 << i);
241 //state->master_irr &= ~(0x1 << i);
242 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
243 irq= i + state->master_icw2;
247 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
248 //state->slave_isr |= (0x1 << (i - 8));
249 //state->slave_irr &= ~(0x1 << (i - 8));
250 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
251 irq= (i - 8) + state->slave_icw2;
270 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
271 static int pic_begin_irq(void * private_data, int irq) {
272 struct pic_internal * state = (struct pic_internal*)private_data;
274 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
276 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
280 PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
285 if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
286 state->master_isr |= (0x1 << irq);
287 state->master_irr &= ~(0x1 << irq);
290 state->slave_isr |= (0x1 << (irq - 8));
291 state->slave_irr &= ~(0x1 << (irq - 8));
299 static int pic_end_irq(void * private_data, int irq) {
306 static struct intr_ctrl_ops intr_ops = {
307 .intr_pending = pic_intr_pending,
308 .get_intr_number = pic_get_intr_number,
309 .raise_intr = pic_raise_intr,
310 .begin_irq = pic_begin_irq,
311 .lower_intr = pic_lower_intr, //Zheng added
318 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
319 struct pic_internal * state = (struct pic_internal*)dev->private_data;
322 PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
326 if ((state->master_ocw3 & 0x03) == 0x02) {
327 *(uchar_t *)dst = state->master_irr;
328 } else if ((state->master_ocw3 & 0x03) == 0x03) {
329 *(uchar_t *)dst = state->master_isr;
337 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
338 struct pic_internal * state = (struct pic_internal*)dev->private_data;
341 PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
345 *(uchar_t *)dst = state->master_imr;
351 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
352 struct pic_internal * state = (struct pic_internal*)dev->private_data;
355 PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
359 if ((state->slave_ocw3 & 0x03) == 0x02) {
360 *(uchar_t*)dst = state->slave_irr;
361 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
362 *(uchar_t *)dst = state->slave_isr;
370 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
371 struct pic_internal * state = (struct pic_internal*)dev->private_data;
374 PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
378 *(uchar_t *)dst = state->slave_imr;
384 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
385 struct pic_internal * state = (struct pic_internal*)dev->private_data;
386 uchar_t cw = *(uchar_t *)src;
388 PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
391 PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
397 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
399 state->master_icw1 = cw;
400 state->master_state = ICW2;
402 } else if (state->master_state == READY) {
404 // handle the EOI here
405 struct ocw2 * cw2 = (struct ocw2*)&cw;
407 PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
409 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
411 state->master_isr &= ~(0x01 << cw2->level);
412 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
415 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
416 for (i = 0; i < 8; i++) {
417 if (state->master_isr & (0x01 << i)) {
418 state->master_isr &= ~(0x01 << i);
422 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
424 PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
428 state->master_ocw2 = cw;
429 } else if (IS_OCW3(cw)) {
430 PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
431 state->master_ocw3 = cw;
433 PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
434 PrintError("8259 PIC: CW=%x\n", cw);
438 PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
439 PrintError("8259 PIC: CW=%x\n", cw);
446 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
447 struct pic_internal * state = (struct pic_internal*)dev->private_data;
448 uchar_t cw = *(uchar_t *)src;
450 PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
453 PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
457 if (state->master_state == ICW2) {
458 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
460 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
461 state->master_icw2 = cw;
463 if (cw1->sngl == 0) {
464 state->master_state = ICW3;
465 } else if (cw1->ic4 == 1) {
466 state->master_state = ICW4;
468 state->master_state = READY;
471 } else if (state->master_state == ICW3) {
472 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
474 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
476 state->master_icw3 = cw;
479 state->master_state = ICW4;
481 state->master_state = READY;
484 } else if (state->master_state == ICW4) {
485 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
486 state->master_icw4 = cw;
487 state->master_state = READY;
488 } else if (state->master_state == READY) {
489 PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
490 state->master_imr = cw;
493 PrintError("8259 PIC: Invalid master PIC State (wr_Master2)\n");
500 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
501 struct pic_internal * state = (struct pic_internal*)dev->private_data;
502 uchar_t cw = *(uchar_t *)src;
504 PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
508 PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
513 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
514 state->slave_icw1 = cw;
515 state->slave_state = ICW2;
516 } else if (state->slave_state == READY) {
518 // handle the EOI here
519 struct ocw2 * cw2 = (struct ocw2 *)&cw;
521 PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
523 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
525 state->slave_isr &= ~(0x01 << cw2->level);
526 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
529 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
530 for (i = 0; i < 8; i++) {
531 if (state->slave_isr & (0x01 << i)) {
532 state->slave_isr &= ~(0x01 << i);
536 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
538 PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
542 state->slave_ocw2 = cw;
543 } else if (IS_OCW3(cw)) {
544 // Basically sets the IRR/ISR read flag
545 PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
546 state->slave_ocw3 = cw;
548 PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
552 PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n");
559 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
560 struct pic_internal * state = (struct pic_internal*)dev->private_data;
561 uchar_t cw = *(uchar_t *)src;
563 PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
566 PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
570 if (state->slave_state == ICW2) {
571 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
573 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
575 state->slave_icw2 = cw;
577 if (cw1->sngl == 0) {
578 state->slave_state = ICW3;
579 } else if (cw1->ic4 == 1) {
580 state->slave_state = ICW4;
582 state->slave_state = READY;
585 } else if (state->slave_state == ICW3) {
586 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
588 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
590 state->slave_icw3 = cw;
593 state->slave_state = ICW4;
595 state->slave_state = READY;
598 } else if (state->slave_state == ICW4) {
599 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
600 state->slave_icw4 = cw;
601 state->slave_state = READY;
602 } else if (state->slave_state == READY) {
603 PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
604 state->slave_imr = cw;
606 PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
620 int pic_init(struct vm_device * dev) {
621 struct pic_internal * state = (struct pic_internal*)dev->private_data;
623 set_intr_controller(dev->vm, &intr_ops, state);
625 state->master_irr = 0;
626 state->master_isr = 0;
627 state->master_icw1 = 0;
628 state->master_icw2 = 0;
629 state->master_icw3 = 0;
630 state->master_icw4 = 0;
631 state->master_imr = 0;
632 state->master_ocw2 = 0;
633 state->master_ocw3 = 0x02;
634 state->master_state = ICW1;
637 state->slave_irr = 0;
638 state->slave_isr = 0;
639 state->slave_icw1 = 0;
640 state->slave_icw2 = 0;
641 state->slave_icw3 = 0;
642 state->slave_icw4 = 0;
643 state->slave_imr = 0;
644 state->slave_ocw2 = 0;
645 state->slave_ocw3 = 0x02;
646 state->slave_state = ICW1;
649 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
650 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
651 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
652 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
658 int pic_deinit(struct vm_device * dev) {
659 dev_unhook_io(dev, MASTER_PORT1);
660 dev_unhook_io(dev, MASTER_PORT2);
661 dev_unhook_io(dev, SLAVE_PORT1);
662 dev_unhook_io(dev, SLAVE_PORT2);
673 static struct vm_device_ops dev_ops = {
675 .deinit = pic_deinit,
682 struct vm_device * create_pic() {
683 struct pic_internal * state = NULL;
684 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
685 V3_ASSERT(state != NULL);
687 struct vm_device *device = create_device("8259A", &dev_ops, state);