1 #include <devices/8259a.h>
2 #include <palacios/vmm_intr.h>
3 #include <palacios/vmm_types.h>
4 #include <palacios/vmm.h>
7 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
9 static const uint_t MASTER_PORT1 = 0x20;
10 static const uint_t MASTER_PORT2 = 0x21;
11 static const uint_t SLAVE_PORT1 = 0xA0;
12 static const uint_t SLAVE_PORT2 = 0xA1;
14 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
15 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
18 uint_t ic4 : 1; // ICW4 has to be read
19 uint_t sngl : 1; // single (only one PIC)
20 uint_t adi : 1; // call address interval
21 uint_t ltim : 1; // level interrupt mode
33 // Each bit that is set indicates that the IR input has a slave
45 // The ID is the Slave device ID
52 uint_t uPM : 1; // 1=x86
53 uint_t AEOI : 1; // Automatic End of Interrupt
54 uint_t M_S : 1; // only if buffered 1=master,0=slave
55 uint_t BUF : 1; // buffered mode
56 uint_t SFNM : 1; // special fully nexted mode
74 uint_t cw_code : 2; // should be 00
84 uint_t cw_code : 2; // should be 01
119 pic_state_t master_state;
120 pic_state_t slave_state;
125 static int pic_raise_intr(void * private_data, int irq, int error_code) {
126 struct pic_internal * state = (struct pic_internal*)private_data;
132 PrintDebug("Raising irq %d in the PIC\n", irq);
135 state->master_irr |= 0x01 << irq;
136 } else if ((irq > 7) && (irq < 16)) {
137 state->slave_irr |= 0x01 << (irq - 7);
139 PrintDebug("Invalid IRQ raised (%d)\n", irq);
146 static int pic_intr_pending(void * private_data) {
147 struct pic_internal * state = (struct pic_internal*)private_data;
149 if ((state->master_irr & ~(state->master_imr)) ||
150 (state->slave_irr & ~(state->slave_imr))) {
157 static int pic_get_intr_number(void * private_data) {
158 struct pic_internal * state = (struct pic_internal*)private_data;
161 for (i = 0; i < 16; i++) {
163 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
164 state->master_isr |= (0x1 << i);
166 state->master_irr &= ~(0x1 << i);
167 PrintDebug("IRQ: %d, icw2: %x\n", i, state->master_icw2);
168 return i + state->master_icw2;
171 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
172 state->slave_isr |= (0x1 << (i - 8));
173 state->slave_irr &= ~(0x1 << (i - 8));
174 return (i - 8) + state->slave_icw2;
183 static int pic_begin_irq(void * private_data, int irq) {
189 static int pic_end_irq(void * private_data, int irq) {
195 static struct intr_ctrl_ops intr_ops = {
196 .intr_pending = pic_intr_pending,
197 .get_intr_number = pic_get_intr_number,
198 .raise_intr = pic_raise_intr,
199 .begin_irq = pic_begin_irq,
205 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
206 struct pic_internal * state = (struct pic_internal*)dev->private_data;
211 if ((state->master_ocw3 & 0x03) == 0x02) {
212 *(char *)dst = state->master_irr;
213 } else if ((state->master_ocw3 & 0x03) == 0x03) {
214 *(char *)dst = state->master_isr;
222 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
223 struct pic_internal * state = (struct pic_internal*)dev->private_data;
228 *(char *)dst = state->master_imr;
234 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
235 struct pic_internal * state = (struct pic_internal*)dev->private_data;
240 if ((state->slave_ocw3 & 0x03) == 0x02) {
241 *(char*)dst = state->slave_irr;
242 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
243 *(char *)dst = state->slave_isr;
251 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
252 struct pic_internal * state = (struct pic_internal*)dev->private_data;
257 *(char *)dst = state->slave_imr;
263 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
264 struct pic_internal * state = (struct pic_internal*)dev->private_data;
265 char cw = *(char *)src;
271 if (state->master_state == ICW1) {
272 state->master_icw1 = cw;
273 state->master_state = ICW2;
275 } else if (state->master_state == READY) {
277 // handle the EOI here
278 struct ocw2 * cw2 = (struct ocw2*)&cw;
281 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
283 state->master_isr &= ~(0x01 << cw2->level);
284 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
287 PrintDebug("Pre ISR = %x\n", state->master_isr);
288 for (i = 0; i < 8; i++) {
289 if (state->master_isr & (0x01 << i)) {
290 state->master_isr &= ~(0x01 << i);
294 PrintDebug("Post ISR = %x\n", state->master_isr);
299 state->master_ocw2 = cw;
300 } else if (IS_OCW3(cw)) {
301 state->master_ocw3 = cw;
312 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
313 struct pic_internal * state = (struct pic_internal*)dev->private_data;
314 char cw = *(char *)src;
320 if (state->master_state == ICW2) {
321 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
323 PrintDebug("Setting ICW2 = %x\n", cw);
324 state->master_icw2 = cw;
326 if (cw1->sngl == 0) {
327 state->master_state = ICW3;
328 } else if (cw1->ic4 == 1) {
329 state->master_state = ICW4;
331 state->master_state = READY;
334 } else if (state->master_state == ICW3) {
335 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
337 state->master_icw3 = cw;
340 state->master_state = ICW4;
342 state->master_state = READY;
345 } else if (state->master_state == ICW4) {
346 state->master_icw4 = cw;
347 state->master_state = READY;
348 } else if (state->master_state == READY) {
349 state->master_imr = cw;
357 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
358 struct pic_internal * state = (struct pic_internal*)dev->private_data;
359 char cw = *(char *)src;
365 if (state->slave_state == ICW1) {
366 state->slave_icw1 = cw;
367 state->slave_state = ICW2;
368 } else if (state->slave_state == READY) {
370 // handle the EOI here
371 struct ocw2 * cw2 = (struct ocw2 *)&cw;
373 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
375 state->slave_isr &= ~(0x01 << cw2->level);
376 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
379 PrintDebug("Pre ISR = %x\n", state->slave_isr);
380 for (i = 0; i < 8; i++) {
381 if (state->slave_isr & (0x01 << i)) {
382 state->slave_isr &= ~(0x01 << i);
386 PrintDebug("Post ISR = %x\n", state->slave_isr);
391 state->slave_ocw2 = cw;
392 } else if (IS_OCW3(cw)) {
393 // Basically sets the IRR/ISR read flag
394 state->slave_ocw3 = cw;
405 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
406 struct pic_internal * state = (struct pic_internal*)dev->private_data;
407 char cw = *(char *)src;
413 if (state->slave_state == ICW2) {
414 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
416 state->slave_icw2 = cw;
418 if (cw1->sngl == 0) {
419 state->slave_state = ICW3;
420 } else if (cw1->ic4 == 1) {
421 state->slave_state = ICW4;
423 state->slave_state = READY;
426 } else if (state->slave_state == ICW3) {
427 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
429 state->slave_icw3 = cw;
432 state->slave_state = ICW4;
434 state->slave_state = READY;
437 } else if (state->slave_state == ICW4) {
438 state->slave_icw4 = cw;
439 state->slave_state = READY;
440 } else if (state->slave_state == READY) {
441 state->slave_imr = cw;
456 int pic_init(struct vm_device * dev) {
457 struct pic_internal * state = (struct pic_internal*)dev->private_data;
459 set_intr_controller(dev->vm, &intr_ops, state);
461 state->master_irr = 0;
462 state->master_isr = 0;
463 state->master_icw1 = 0;
464 state->master_icw2 = 0;
465 state->master_icw3 = 0;
466 state->master_icw4 = 0;
467 state->master_imr = 0;
468 state->master_ocw2 = 0;
469 state->master_ocw3 = 0x02;
470 state->master_state = ICW1;
473 state->slave_irr = 0;
474 state->slave_isr = 0;
475 state->slave_icw1 = 0;
476 state->slave_icw2 = 0;
477 state->slave_icw3 = 0;
478 state->slave_icw4 = 0;
479 state->slave_imr = 0;
480 state->slave_ocw2 = 0;
481 state->slave_ocw3 = 0x02;
482 state->slave_state = ICW1;
485 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
486 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
487 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
488 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
494 int pic_deinit(struct vm_device * dev) {
495 dev_unhook_io(dev, MASTER_PORT1);
496 dev_unhook_io(dev, MASTER_PORT2);
497 dev_unhook_io(dev, SLAVE_PORT1);
498 dev_unhook_io(dev, SLAVE_PORT2);
509 static struct vm_device_ops dev_ops = {
511 .deinit = pic_deinit,
518 struct vm_device * create_pic() {
519 struct pic_internal * state = NULL;
520 VMMMalloc(struct pic_internal *, state, sizeof(struct pic_internal));
522 struct vm_device *device = create_device("8259A", &dev_ops, state);