1 #include <devices/8259a.h>
2 #include <palacios/vmm_intr.h>
3 #include <palacios/vmm_types.h>
4 #include <palacios/vmm.h>
7 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
9 static const uint_t MASTER_PORT1 = 0x20;
10 static const uint_t MASTER_PORT2 = 0x21;
11 static const uint_t SLAVE_PORT1 = 0xA0;
12 static const uint_t SLAVE_PORT2 = 0xA1;
14 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
15 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
16 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
20 uint_t ic4 : 1; // ICW4 has to be read
21 uint_t sngl : 1; // single (only one PIC)
22 uint_t adi : 1; // call address interval
23 uint_t ltim : 1; // level interrupt mode
35 // Each bit that is set indicates that the IR input has a slave
47 // The ID is the Slave device ID
54 uint_t uPM : 1; // 1=x86
55 uint_t AEOI : 1; // Automatic End of Interrupt
56 uint_t M_S : 1; // only if buffered 1=master,0=slave
57 uint_t BUF : 1; // buffered mode
58 uint_t SFNM : 1; // special fully nexted mode
76 uint_t cw_code : 2; // should be 00
86 uint_t cw_code : 2; // should be 01
121 pic_state_t master_state;
122 pic_state_t slave_state;
126 static void DumpPICState(struct pic_internal *p)
129 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
130 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
131 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
132 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
134 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
135 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
137 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
138 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
139 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
140 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
142 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
143 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
144 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
145 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
147 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
148 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
150 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
151 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
152 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
153 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
158 static int pic_raise_intr(void * private_data, int irq) {
159 struct pic_internal * state = (struct pic_internal*)private_data;
163 state->master_irr |= 0x04; // PAD
166 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq);
169 state->master_irr |= 0x01 << irq;
170 } else if ((irq > 7) && (irq < 16)) {
171 state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq
173 PrintDebug("8259 PIC: Invalid IRQ raised (%d)\n", irq);
180 static int pic_intr_pending(void * private_data) {
181 struct pic_internal * state = (struct pic_internal*)private_data;
183 if ((state->master_irr & ~(state->master_imr)) ||
184 (state->slave_irr & ~(state->slave_imr))) {
191 static int pic_get_intr_number(void * private_data) {
192 struct pic_internal * state = (struct pic_internal*)private_data;
196 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", i, state->master_irr, state->master_imr);
197 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", i, state->slave_irr, state->slave_imr);
199 for (i = 0; i < 16; i++) {
201 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
202 //state->master_isr |= (0x1 << i);
204 //state->master_irr &= ~(0x1 << i);
205 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
206 irq= i + state->master_icw2;
210 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
211 //state->slave_isr |= (0x1 << (i - 8));
212 //state->slave_irr &= ~(0x1 << (i - 8));
213 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
214 irq= (i - 8) + state->slave_icw2;
233 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
234 static int pic_begin_irq(void * private_data, int irq) {
235 struct pic_internal * state = (struct pic_internal*)private_data;
237 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
239 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
243 PrintDebug("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
248 if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
249 state->master_isr |= (0x1 << irq);
250 state->master_irr &= ~(0x1 << irq);
253 state->slave_isr |= (0x1 << (irq - 8));
254 state->slave_irr &= ~(0x1 << (irq - 8));
262 static int pic_end_irq(void * private_data, int irq) {
267 static struct intr_ctrl_ops intr_ops = {
268 .intr_pending = pic_intr_pending,
269 .get_intr_number = pic_get_intr_number,
270 .raise_intr = pic_raise_intr,
271 .begin_irq = pic_begin_irq,
277 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
278 struct pic_internal * state = (struct pic_internal*)dev->private_data;
281 PrintDebug("8259 PIC: Invalid Read length (rd_Master1)\n");
285 if ((state->master_ocw3 & 0x03) == 0x02) {
286 *(uchar_t *)dst = state->master_irr;
287 } else if ((state->master_ocw3 & 0x03) == 0x03) {
288 *(uchar_t *)dst = state->master_isr;
296 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
297 struct pic_internal * state = (struct pic_internal*)dev->private_data;
300 PrintDebug("8259 PIC: Invalid Read length (rd_Master2)\n");
304 *(uchar_t *)dst = state->master_imr;
310 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
311 struct pic_internal * state = (struct pic_internal*)dev->private_data;
314 PrintDebug("8259 PIC: Invalid Read length (rd_Slave1)\n");
318 if ((state->slave_ocw3 & 0x03) == 0x02) {
319 *(uchar_t*)dst = state->slave_irr;
320 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
321 *(uchar_t *)dst = state->slave_isr;
329 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
330 struct pic_internal * state = (struct pic_internal*)dev->private_data;
333 PrintDebug("8259 PIC: Invalid Read length (rd_Slave2)\n");
337 *(uchar_t *)dst = state->slave_imr;
343 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
344 struct pic_internal * state = (struct pic_internal*)dev->private_data;
345 uchar_t cw = *(uchar_t *)src;
348 PrintDebug("8259 PIC: Invalid Write length (wr_Master1)\n");
353 state->master_icw1 = cw;
354 state->master_state = ICW2;
356 } else if (state->master_state == READY) {
358 // handle the EOI here
359 struct ocw2 * cw2 = (struct ocw2*)&cw;
362 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
364 state->master_isr &= ~(0x01 << cw2->level);
365 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
368 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
369 for (i = 0; i < 8; i++) {
370 if (state->master_isr & (0x01 << i)) {
371 state->master_isr &= ~(0x01 << i);
375 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
377 PrintDebug("8259 PIC: Command not handled, or in error (wr_Master1)\n");
381 state->master_ocw2 = cw;
382 } else if (IS_OCW3(cw)) {
383 state->master_ocw3 = cw;
385 PrintDebug("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
386 PrintDebug("8259 PIC: CW=%x\n", cw);
390 PrintDebug("8259 PIC: Invalid PIC State (wr_Master1)\n");
391 PrintDebug("8259 PIC: CW=%x\n", cw);
398 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
399 struct pic_internal * state = (struct pic_internal*)dev->private_data;
400 uchar_t cw = *(uchar_t *)src;
403 PrintDebug("8259 PIC: Invalid Write length (wr_Master2)\n");
407 if (state->master_state == ICW2) {
408 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
410 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
411 state->master_icw2 = cw;
413 if (cw1->sngl == 0) {
414 state->master_state = ICW3;
415 } else if (cw1->ic4 == 1) {
416 state->master_state = ICW4;
418 state->master_state = READY;
421 } else if (state->master_state == ICW3) {
422 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
424 state->master_icw3 = cw;
427 state->master_state = ICW4;
429 state->master_state = READY;
432 } else if (state->master_state == ICW4) {
433 state->master_icw4 = cw;
434 state->master_state = READY;
435 } else if (state->master_state == READY) {
436 state->master_imr = cw;
439 PrintDebug("8259 PIC: Invalid master PIC State (wr_Master2)\n");
446 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
447 struct pic_internal * state = (struct pic_internal*)dev->private_data;
448 uchar_t cw = *(uchar_t *)src;
452 PrintDebug("8259 PIC: Invalid Write length (wr_Slave1)\n");
457 state->slave_icw1 = cw;
458 state->slave_state = ICW2;
459 } else if (state->slave_state == READY) {
461 // handle the EOI here
462 struct ocw2 * cw2 = (struct ocw2 *)&cw;
464 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
466 state->slave_isr &= ~(0x01 << cw2->level);
467 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
470 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
471 for (i = 0; i < 8; i++) {
472 if (state->slave_isr & (0x01 << i)) {
473 state->slave_isr &= ~(0x01 << i);
477 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
479 PrintDebug("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
483 state->slave_ocw2 = cw;
484 } else if (IS_OCW3(cw)) {
485 // Basically sets the IRR/ISR read flag
486 state->slave_ocw3 = cw;
488 PrintDebug("8259 PIC: Invalid command work (wr_Slave1)\n");
492 PrintDebug("8259 PIC: Invalid State writing (wr_Slave1)\n");
499 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
500 struct pic_internal * state = (struct pic_internal*)dev->private_data;
501 uchar_t cw = *(uchar_t *)src;
504 PrintDebug("8259 PIC: Invalid write length (wr_Slave2)\n");
508 if (state->slave_state == ICW2) {
509 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
511 state->slave_icw2 = cw;
513 if (cw1->sngl == 0) {
514 state->slave_state = ICW3;
515 } else if (cw1->ic4 == 1) {
516 state->slave_state = ICW4;
518 state->slave_state = READY;
521 } else if (state->slave_state == ICW3) {
522 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
524 state->slave_icw3 = cw;
527 state->slave_state = ICW4;
529 state->slave_state = READY;
532 } else if (state->slave_state == ICW4) {
533 state->slave_icw4 = cw;
534 state->slave_state = READY;
535 } else if (state->slave_state == READY) {
536 state->slave_imr = cw;
538 PrintDebug("8259 PIC: Invalid State at write (wr_Slave2)\n");
552 int pic_init(struct vm_device * dev) {
553 struct pic_internal * state = (struct pic_internal*)dev->private_data;
555 set_intr_controller(dev->vm, &intr_ops, state);
557 state->master_irr = 0;
558 state->master_isr = 0;
559 state->master_icw1 = 0;
560 state->master_icw2 = 0;
561 state->master_icw3 = 0;
562 state->master_icw4 = 0;
563 state->master_imr = 0;
564 state->master_ocw2 = 0;
565 state->master_ocw3 = 0x02;
566 state->master_state = ICW1;
569 state->slave_irr = 0;
570 state->slave_isr = 0;
571 state->slave_icw1 = 0;
572 state->slave_icw2 = 0;
573 state->slave_icw3 = 0;
574 state->slave_icw4 = 0;
575 state->slave_imr = 0;
576 state->slave_ocw2 = 0;
577 state->slave_ocw3 = 0x02;
578 state->slave_state = ICW1;
581 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
582 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
583 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
584 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
590 int pic_deinit(struct vm_device * dev) {
591 dev_unhook_io(dev, MASTER_PORT1);
592 dev_unhook_io(dev, MASTER_PORT2);
593 dev_unhook_io(dev, SLAVE_PORT1);
594 dev_unhook_io(dev, SLAVE_PORT2);
605 static struct vm_device_ops dev_ops = {
607 .deinit = pic_deinit,
614 struct vm_device * create_pic() {
615 struct pic_internal * state = NULL;
616 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
617 V3_ASSERT(state != NULL);
619 struct vm_device *device = create_device("8259A", &dev_ops, state);