1 #include <devices/8259a.h>
2 #include <palacios/vmm_intr.h>
3 #include <palacios/vmm_types.h>
4 #include <palacios/vmm.h>
8 #define PrintDebug(fmt, args...)
12 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
14 static const uint_t MASTER_PORT1 = 0x20;
15 static const uint_t MASTER_PORT2 = 0x21;
16 static const uint_t SLAVE_PORT1 = 0xA0;
17 static const uint_t SLAVE_PORT2 = 0xA1;
19 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
20 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
21 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
25 uint_t ic4 : 1; // ICW4 has to be read
26 uint_t sngl : 1; // single (only one PIC)
27 uint_t adi : 1; // call address interval
28 uint_t ltim : 1; // level interrupt mode
40 // Each bit that is set indicates that the IR input has a slave
52 // The ID is the Slave device ID
59 uint_t uPM : 1; // 1=x86
60 uint_t AEOI : 1; // Automatic End of Interrupt
61 uint_t M_S : 1; // only if buffered 1=master,0=slave
62 uint_t BUF : 1; // buffered mode
63 uint_t SFNM : 1; // special fully nexted mode
81 uint_t cw_code : 2; // should be 00
91 uint_t cw_code : 2; // should be 01
126 pic_state_t master_state;
127 pic_state_t slave_state;
131 static void DumpPICState(struct pic_internal *p)
134 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
135 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
136 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
137 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
139 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
140 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
142 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
143 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
144 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
145 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
147 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
148 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
149 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
150 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
152 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
153 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
155 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
156 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
157 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
158 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
163 static int pic_raise_intr(void * private_data, int irq) {
164 struct pic_internal * state = (struct pic_internal*)private_data;
168 state->master_irr |= 0x04; // PAD
171 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq);
174 state->master_irr |= 0x01 << irq;
175 } else if ((irq > 7) && (irq < 16)) {
176 state->slave_irr |= 0x01 << (irq - 8); // PAD if -7 then irq 15=no irq
178 PrintError("8259 PIC: Invalid IRQ raised (%d)\n", irq);
188 static int pic_lower_intr(void *private_data, int irq_no) {
190 struct pic_internal *state = (struct pic_internal*)private_data;
192 PrintDebug("[pic_lower_intr] IRQ line %d now low\n", (unsigned) irq_no);
195 state->master_irr &= ~(1 << irq_no);
196 if ((state->master_irr & ~(state->master_imr)) == 0) {
197 PrintDebug("\t\tFIXME: Master maybe should do sth\n");
199 } else if ((irq_no > 7) && (irq_no <= 15)) {
201 state->slave_irr &= ~(1 << (irq_no - 8));
202 if ((state->slave_irr & (~(state->slave_imr))) == 0) {
203 PrintDebug("\t\tFIXME: Slave maybe should do sth\n");
211 static int pic_intr_pending(void * private_data) {
212 struct pic_internal * state = (struct pic_internal*)private_data;
214 if ((state->master_irr & ~(state->master_imr)) ||
215 (state->slave_irr & ~(state->slave_imr))) {
222 static int pic_get_intr_number(void * private_data) {
223 struct pic_internal * state = (struct pic_internal *)private_data;
227 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", i, state->master_irr, state->master_imr);
228 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", i, state->slave_irr, state->slave_imr);
230 for (i = 0; i < 16; i++) {
232 if (((state->master_irr & ~(state->master_imr)) >> i) == 0x01) {
233 //state->master_isr |= (0x1 << i);
235 //state->master_irr &= ~(0x1 << i);
236 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
237 irq= i + state->master_icw2;
241 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) == 0x01) {
242 //state->slave_isr |= (0x1 << (i - 8));
243 //state->slave_irr &= ~(0x1 << (i - 8));
244 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
245 irq= (i - 8) + state->slave_icw2;
251 if ((i == 15) || (i == 6)) {
264 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
265 static int pic_begin_irq(void * private_data, int irq) {
266 struct pic_internal * state = (struct pic_internal*)private_data;
268 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
270 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
274 PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
279 if (((state->master_irr & ~(state->master_imr)) >> irq) == 0x01) {
280 state->master_isr |= (0x1 << irq);
281 state->master_irr &= ~(0x1 << irq);
284 state->slave_isr |= (0x1 << (irq - 8));
285 state->slave_irr &= ~(0x1 << (irq - 8));
293 static int pic_end_irq(void * private_data, int irq) {
300 static struct intr_ctrl_ops intr_ops = {
301 .intr_pending = pic_intr_pending,
302 .get_intr_number = pic_get_intr_number,
303 .raise_intr = pic_raise_intr,
304 .begin_irq = pic_begin_irq,
305 .lower_intr = pic_lower_intr, //Zheng added
312 int read_master_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
313 struct pic_internal * state = (struct pic_internal*)dev->private_data;
316 PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
320 if ((state->master_ocw3 & 0x03) == 0x02) {
321 *(uchar_t *)dst = state->master_irr;
322 } else if ((state->master_ocw3 & 0x03) == 0x03) {
323 *(uchar_t *)dst = state->master_isr;
331 int read_master_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
332 struct pic_internal * state = (struct pic_internal*)dev->private_data;
335 PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
339 *(uchar_t *)dst = state->master_imr;
345 int read_slave_port1(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
346 struct pic_internal * state = (struct pic_internal*)dev->private_data;
349 PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
353 if ((state->slave_ocw3 & 0x03) == 0x02) {
354 *(uchar_t*)dst = state->slave_irr;
355 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
356 *(uchar_t *)dst = state->slave_isr;
364 int read_slave_port2(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
365 struct pic_internal * state = (struct pic_internal*)dev->private_data;
368 PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
372 *(uchar_t *)dst = state->slave_imr;
378 int write_master_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
379 struct pic_internal * state = (struct pic_internal*)dev->private_data;
380 uchar_t cw = *(uchar_t *)src;
382 PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
385 PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
391 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
393 state->master_icw1 = cw;
394 state->master_state = ICW2;
396 } else if (state->master_state == READY) {
398 // handle the EOI here
399 struct ocw2 * cw2 = (struct ocw2*)&cw;
401 PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
403 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
405 state->master_isr &= ~(0x01 << cw2->level);
406 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
409 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
410 for (i = 0; i < 8; i++) {
411 if (state->master_isr & (0x01 << i)) {
412 state->master_isr &= ~(0x01 << i);
416 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
418 PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
422 state->master_ocw2 = cw;
423 } else if (IS_OCW3(cw)) {
424 PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
425 state->master_ocw3 = cw;
427 PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
428 PrintError("8259 PIC: CW=%x\n", cw);
432 PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
433 PrintError("8259 PIC: CW=%x\n", cw);
440 int write_master_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
441 struct pic_internal * state = (struct pic_internal*)dev->private_data;
442 uchar_t cw = *(uchar_t *)src;
444 PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
447 PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
451 if (state->master_state == ICW2) {
452 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
454 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
455 state->master_icw2 = cw;
457 if (cw1->sngl == 0) {
458 state->master_state = ICW3;
459 } else if (cw1->ic4 == 1) {
460 state->master_state = ICW4;
462 state->master_state = READY;
465 } else if (state->master_state == ICW3) {
466 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
468 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
470 state->master_icw3 = cw;
473 state->master_state = ICW4;
475 state->master_state = READY;
478 } else if (state->master_state == ICW4) {
479 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
480 state->master_icw4 = cw;
481 state->master_state = READY;
482 } else if (state->master_state == READY) {
483 PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
484 state->master_imr = cw;
487 PrintError("8259 PIC: Invalid master PIC State (wr_Master2)\n");
494 int write_slave_port1(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
495 struct pic_internal * state = (struct pic_internal*)dev->private_data;
496 uchar_t cw = *(uchar_t *)src;
498 PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
502 PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
507 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
508 state->slave_icw1 = cw;
509 state->slave_state = ICW2;
510 } else if (state->slave_state == READY) {
512 // handle the EOI here
513 struct ocw2 * cw2 = (struct ocw2 *)&cw;
515 PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
517 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
519 state->slave_isr &= ~(0x01 << cw2->level);
520 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
523 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
524 for (i = 0; i < 8; i++) {
525 if (state->slave_isr & (0x01 << i)) {
526 state->slave_isr &= ~(0x01 << i);
530 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
532 PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
536 state->slave_ocw2 = cw;
537 } else if (IS_OCW3(cw)) {
538 // Basically sets the IRR/ISR read flag
539 PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
540 state->slave_ocw3 = cw;
542 PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
546 PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n");
553 int write_slave_port2(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
554 struct pic_internal * state = (struct pic_internal*)dev->private_data;
555 uchar_t cw = *(uchar_t *)src;
557 PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
560 PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
564 if (state->slave_state == ICW2) {
565 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
567 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
569 state->slave_icw2 = cw;
571 if (cw1->sngl == 0) {
572 state->slave_state = ICW3;
573 } else if (cw1->ic4 == 1) {
574 state->slave_state = ICW4;
576 state->slave_state = READY;
579 } else if (state->slave_state == ICW3) {
580 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
582 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
584 state->slave_icw3 = cw;
587 state->slave_state = ICW4;
589 state->slave_state = READY;
592 } else if (state->slave_state == ICW4) {
593 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
594 state->slave_icw4 = cw;
595 state->slave_state = READY;
596 } else if (state->slave_state == READY) {
597 PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
598 state->slave_imr = cw;
600 PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
614 int pic_init(struct vm_device * dev) {
615 struct pic_internal * state = (struct pic_internal*)dev->private_data;
617 set_intr_controller(dev->vm, &intr_ops, state);
619 state->master_irr = 0;
620 state->master_isr = 0;
621 state->master_icw1 = 0;
622 state->master_icw2 = 0;
623 state->master_icw3 = 0;
624 state->master_icw4 = 0;
625 state->master_imr = 0;
626 state->master_ocw2 = 0;
627 state->master_ocw3 = 0x02;
628 state->master_state = ICW1;
631 state->slave_irr = 0;
632 state->slave_isr = 0;
633 state->slave_icw1 = 0;
634 state->slave_icw2 = 0;
635 state->slave_icw3 = 0;
636 state->slave_icw4 = 0;
637 state->slave_imr = 0;
638 state->slave_ocw2 = 0;
639 state->slave_ocw3 = 0x02;
640 state->slave_state = ICW1;
643 dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
644 dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
645 dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
646 dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
652 int pic_deinit(struct vm_device * dev) {
653 dev_unhook_io(dev, MASTER_PORT1);
654 dev_unhook_io(dev, MASTER_PORT2);
655 dev_unhook_io(dev, SLAVE_PORT1);
656 dev_unhook_io(dev, SLAVE_PORT2);
667 static struct vm_device_ops dev_ops = {
669 .deinit = pic_deinit,
676 struct vm_device * create_pic() {
677 struct pic_internal * state = NULL;
678 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
679 V3_ASSERT(state != NULL);
681 struct vm_device *device = create_device("8259A", &dev_ops, state);