2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
22 #include <palacios/vmm_intr.h>
23 #include <palacios/vmm_types.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmm_dev_mgr.h>
26 #include <palacios/vm_guest.h>
28 #ifndef V3_CONFIG_DEBUG_PIC
30 #define PrintDebug(fmt, args...)
34 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
36 static const uint_t MASTER_PORT1 = 0x20;
37 static const uint_t MASTER_PORT2 = 0x21;
38 static const uint_t SLAVE_PORT1 = 0xA0;
39 static const uint_t SLAVE_PORT2 = 0xA1;
41 static const uint_t ELCR1_PORT = 0x4d0;
42 static const uint_t ELCR2_PORT = 0x4d1;
45 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
46 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
47 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
51 uint_t ic4 : 1; // ICW4 has to be read
52 uint_t sngl : 1; // single (only one PIC)
53 uint_t adi : 1; // call address interval
54 uint_t ltim : 1; // level interrupt mode
66 // Each bit that is set indicates that the IR input has a slave
78 // The ID is the Slave device ID
85 uint_t uPM : 1; // 1=x86
86 uint_t AEOI : 1; // Automatic End of Interrupt
87 uint_t M_S : 1; // only if buffered 1=master,0=slave
88 uint_t BUF : 1; // buffered mode
89 uint_t SFNM : 1; // special fully nexted mode
107 uint_t cw_code : 2; // should be 00
117 uint_t cw_code : 2; // should be 01
124 struct pic_internal {
135 uint8_t master_elcr_mask;
136 uint8_t slave_elcr_mask;
157 pic_state_t master_state;
158 pic_state_t slave_state;
160 struct guest_info * core;
163 void * router_handle;
164 void * controller_handle;
168 static void DumpPICState(struct pic_internal *p)
171 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
172 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
173 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
174 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
176 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
177 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
179 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
180 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
181 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
182 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
184 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
185 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
186 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
187 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
189 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
190 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
192 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
193 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
194 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
195 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
200 static int pic_raise_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) {
201 struct pic_internal * state = (struct pic_internal*)private_data;
202 uint8_t irq_num = irq->irq;
206 state->master_irr |= 0x04;
209 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq_num);
212 state->master_irr |= 0x01 << irq_num;
213 } else if ((irq_num > 7) && (irq_num < 16)) {
214 state->slave_irr |= 0x01 << (irq_num - 8);
216 PrintDebug("8259 PIC: Invalid IRQ raised (%d)\n", irq_num);
220 if (V3_Get_CPU() != vm->cores[0].pcpu_id) {
221 // guest is running on another core, interrupt it to deliver irq
222 v3_interrupt_cpu(vm, 0, 0);
229 static int pic_lower_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) {
230 struct pic_internal * state = (struct pic_internal*)private_data;
231 uint8_t irq_num = irq->irq;
234 PrintDebug("[pic_lower_intr] IRQ line %d now low\n", irq_num);
237 state->master_irr &= ~(1 << irq_num);
238 if ((state->master_irr & ~(state->master_imr)) == 0) {
239 PrintDebug("\t\tFIXME: Master maybe should do sth\n");
241 } else if ((irq_num > 7) && (irq_num < 16)) {
243 state->slave_irr &= ~(1 << (irq_num - 8));
244 if ((state->slave_irr & (~(state->slave_imr))) == 0) {
245 PrintDebug("\t\tFIXME: Slave maybe should do sth\n");
253 static int pic_intr_pending(struct guest_info * info, void * private_data) {
254 struct pic_internal * state = (struct pic_internal*)private_data;
256 if ((state->master_irr & ~(state->master_imr)) ||
257 (state->slave_irr & ~(state->slave_imr))) {
264 static int pic_get_intr_number(struct guest_info * info, void * private_data) {
265 struct pic_internal * state = (struct pic_internal *)private_data;
269 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", state->master_irr, state->master_imr);
270 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", state->slave_irr, state->slave_imr);
272 for (i = 0; i < 16; i++) {
274 if (((state->master_irr & ~(state->master_imr)) >> i) & 0x01) {
275 //state->master_isr |= (0x1 << i);
277 //state->master_irr &= ~(0x1 << i);
278 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
279 irq = i + state->master_icw2;
283 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) & 0x01) {
284 //state->slave_isr |= (0x1 << (i - 8));
285 //state->slave_irr &= ~(0x1 << (i - 8));
286 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
287 irq = (i - 8) + state->slave_icw2;
294 if ((i == 15) || (i == 6)) {
302 PrintDebug("8259 PIC: get num is returning %d\n",irq);
309 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
310 static int pic_begin_irq(struct guest_info * info, void * private_data, int irq) {
311 struct pic_internal * state = (struct pic_internal*)private_data;
313 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
315 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
319 // PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
324 // This should always be true: See pic_get_intr_number
325 if (((state->master_irr & ~(state->master_imr)) >> irq) & 0x01) {
326 state->master_isr |= (0x1 << irq);
328 if (!(state->master_elcr & (0x1 << irq))) {
329 state->master_irr &= ~(0x1 << irq);
332 PrintDebug("8259 PIC: (master) Ignoring begin_irq for %d since I don't own it\n",irq);
336 // This should always be true: See pic_get_intr_number
337 if (((state->slave_irr & ~(state->slave_imr)) >> (irq - 8)) & 0x01) {
338 state->slave_isr |= (0x1 << (irq - 8));
340 if (!(state->slave_elcr & (0x1 << (irq - 8)))) {
341 state->slave_irr &= ~(0x1 << (irq - 8));
344 PrintDebug("8259 PIC: (slave) Ignoring begin_irq for %d since I don't own it\n",irq);
354 static int pic_end_irq(void * private_data, int irq) {
361 static struct intr_ctrl_ops intr_ops = {
362 .intr_pending = pic_intr_pending,
363 .get_intr_number = pic_get_intr_number,
364 .begin_irq = pic_begin_irq
367 static struct intr_router_ops router_ops = {
368 .raise_intr = pic_raise_intr,
369 .lower_intr = pic_lower_intr
373 static int read_master_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
374 struct pic_internal * state = (struct pic_internal *)priv_data;
377 PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
381 if ((state->master_ocw3 & 0x03) == 0x02) {
382 *(uint8_t *)dst = state->master_irr;
383 } else if ((state->master_ocw3 & 0x03) == 0x03) {
384 *(uint8_t *)dst = state->master_isr;
392 static int read_master_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
393 struct pic_internal * state = (struct pic_internal *)priv_data;
396 PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
400 *(uint8_t *)dst = state->master_imr;
406 static int read_slave_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
407 struct pic_internal * state = (struct pic_internal *)priv_data;
410 PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
414 if ((state->slave_ocw3 & 0x03) == 0x02) {
415 *(uint8_t*)dst = state->slave_irr;
416 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
417 *(uint8_t *)dst = state->slave_isr;
425 static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
426 struct pic_internal * state = (struct pic_internal *)priv_data;
429 PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
433 *(uint8_t *)dst = state->slave_imr;
439 static int write_master_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
440 struct pic_internal * state = (struct pic_internal *)priv_data;
441 uint8_t cw = *(uint8_t *)src;
443 PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
446 PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
450 v3_clear_pending_intr(core);
454 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
456 state->master_icw1 = cw;
457 state->master_state = ICW2;
459 } else if (state->master_state == READY) {
461 // handle the EOI here
462 struct ocw2 * cw2 = (struct ocw2*)&cw;
464 PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
466 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
468 state->master_isr &= ~(0x01 << cw2->level);
469 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
472 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
473 for (i = 0; i < 8; i++) {
474 if (state->master_isr & (0x01 << i)) {
475 state->master_isr &= ~(0x01 << i);
479 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
480 } else if (!(cw2->EOI) && (cw2->R) && (cw2->SL)) {
481 PrintDebug("8259 PIC: Ignoring set-priority, priorities not implemented (level=%d, wr_Master1)\n", cw2->level);
482 } else if (!(cw2->EOI) && !(cw2->R) && (cw2->SL)) {
483 PrintDebug("8259 PIC: Ignoring no-op (level=%d, wr_Master1)\n", cw2->level);
485 PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
489 state->master_ocw2 = cw;
490 } else if (IS_OCW3(cw)) {
491 PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
492 state->master_ocw3 = cw;
494 PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
495 PrintError("8259 PIC: CW=%x\n", cw);
499 PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
500 PrintError("8259 PIC: CW=%x\n", cw);
507 static int write_master_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
508 struct pic_internal * state = (struct pic_internal *)priv_data;
509 uint8_t cw = *(uint8_t *)src;
511 PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
514 PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
518 v3_clear_pending_intr(core);
520 if (state->master_state == ICW2) {
521 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
523 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
524 state->master_icw2 = cw;
528 if (cw1->sngl == 0) {
529 state->master_state = ICW3;
530 } else if (cw1->ic4 == 1) {
531 state->master_state = ICW4;
533 state->master_state = READY;
538 } else if (state->master_state == ICW3) {
539 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
541 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
543 state->master_icw3 = cw;
546 state->master_state = ICW4;
548 state->master_state = READY;
551 } else if (state->master_state == ICW4) {
552 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
553 state->master_icw4 = cw;
554 state->master_state = READY;
555 } else if ((state->master_state == ICW1) || (state->master_state == READY)) {
556 PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
557 state->master_imr = cw;
560 PrintError("8259 PIC: Invalid master PIC State (wr_Master2) (state=%d)\n",
561 state->master_state);
568 static int write_slave_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
569 struct pic_internal * state = (struct pic_internal *)priv_data;
570 uint8_t cw = *(uint8_t *)src;
572 PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
576 PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
580 v3_clear_pending_intr(core);
583 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
584 state->slave_icw1 = cw;
585 state->slave_state = ICW2;
586 } else if (state->slave_state == READY) {
588 // handle the EOI here
589 struct ocw2 * cw2 = (struct ocw2 *)&cw;
591 PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
593 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
595 state->slave_isr &= ~(0x01 << cw2->level);
596 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
599 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
600 for (i = 0; i < 8; i++) {
601 if (state->slave_isr & (0x01 << i)) {
602 state->slave_isr &= ~(0x01 << i);
606 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
608 PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
612 state->slave_ocw2 = cw;
613 } else if (IS_OCW3(cw)) {
614 // Basically sets the IRR/ISR read flag
615 PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
616 state->slave_ocw3 = cw;
618 PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
622 PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n");
629 static int write_slave_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
630 struct pic_internal * state = (struct pic_internal *)priv_data;
631 uint8_t cw = *(uint8_t *)src;
633 PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
636 PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
640 v3_clear_pending_intr(core);
643 if (state->slave_state == ICW2) {
644 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
646 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
648 state->slave_icw2 = cw;
650 if (cw1->sngl == 0) {
651 state->slave_state = ICW3;
652 } else if (cw1->ic4 == 1) {
653 state->slave_state = ICW4;
655 state->slave_state = READY;
658 } else if (state->slave_state == ICW3) {
659 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
661 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
663 state->slave_icw3 = cw;
666 state->slave_state = ICW4;
668 state->slave_state = READY;
671 } else if (state->slave_state == ICW4) {
672 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
673 state->slave_icw4 = cw;
674 state->slave_state = READY;
675 } else if ((state->slave_state == ICW1) || (state->slave_state == READY)) {
676 PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
677 state->slave_imr = cw;
679 PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
689 static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
690 struct pic_internal * state = (struct pic_internal *)priv_data;
693 PrintError("ELCR read of invalid length %d\n", length);
697 if (port == ELCR1_PORT) {
699 *(uint8_t *)dst = state->master_elcr;
700 } else if (port == ELCR2_PORT) {
701 *(uint8_t *)dst = state->slave_elcr;
703 PrintError("Invalid port %x\n", port);
711 static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
712 struct pic_internal * state = (struct pic_internal *)priv_data;
715 PrintError("ELCR read of invalid length %d\n", length);
719 if (port == ELCR1_PORT) {
721 state->master_elcr = (*(uint8_t *)src) & state->master_elcr_mask;
722 } else if (port == ELCR2_PORT) {
723 state->slave_elcr = (*(uint8_t *)src) & state->slave_elcr_mask;
725 PrintError("Invalid port %x\n", port);
734 static int pic_free(struct pic_internal * state) {
735 struct guest_info * core = state->core;
737 v3_remove_intr_controller(core, state->controller_handle);
738 v3_remove_intr_router(core->vm_info, state->router_handle);
744 #ifdef V3_CONFIG_CHECKPOINT
745 static int pic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
746 struct pic_internal * pic = (struct pic_internal *)private_data;
748 v3_chkpt_save_8(ctx, "MASTER_IRR", &(pic->master_irr));
749 v3_chkpt_save_8(ctx, "SLAVE_IRR", &(pic->slave_irr));
751 v3_chkpt_save_8(ctx, "MASTER_ISR", &(pic->master_isr));
752 v3_chkpt_save_8(ctx, "SLAVE_ISR", &(pic->slave_isr));
754 v3_chkpt_save_8(ctx, "MASTER_ELCR", &(pic->master_elcr));
755 v3_chkpt_save_8(ctx, "SLAVE_ELCR", &(pic->slave_elcr));
756 v3_chkpt_save_8(ctx, "MASTER_ELCR_MASK", &(pic->master_elcr_mask));
757 v3_chkpt_save_8(ctx, "SLAVE_ELCR_MASK", &(pic->slave_elcr_mask));
759 v3_chkpt_save_8(ctx, "MASTER_ICW1", &(pic->master_icw1));
760 v3_chkpt_save_8(ctx, "MASTER_ICW2", &(pic->master_icw2));
761 v3_chkpt_save_8(ctx, "MASTER_ICW3", &(pic->master_icw3));
762 v3_chkpt_save_8(ctx, "MASTER_ICW4", &(pic->master_icw4));
765 v3_chkpt_save_8(ctx, "SLAVE_ICW1", &(pic->slave_icw1));
766 v3_chkpt_save_8(ctx, "SLAVE_ICW2", &(pic->slave_icw2));
767 v3_chkpt_save_8(ctx, "SLAVE_ICW3", &(pic->slave_icw3));
768 v3_chkpt_save_8(ctx, "SLAVE_ICW4", &(pic->slave_icw4));
771 v3_chkpt_save_8(ctx, "MASTER_IMR", &(pic->master_imr));
772 v3_chkpt_save_8(ctx, "SLAVE_IMR", &(pic->slave_imr));
773 v3_chkpt_save_8(ctx, "MASTER_OCW2", &(pic->master_ocw2));
774 v3_chkpt_save_8(ctx, "MASTER_OCW3", &(pic->master_ocw3));
775 v3_chkpt_save_8(ctx, "SLAVE_OCW2", &(pic->slave_ocw2));
776 v3_chkpt_save_8(ctx, "SLAVE_OCW3", &(pic->slave_ocw3));
778 v3_chkpt_save_8(ctx, "MASTER_STATE", &(pic->master_state));
779 v3_chkpt_save_8(ctx, "SLAVE_STATE", &(pic->slave_state));
786 static int pic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
787 struct pic_internal * pic = (struct pic_internal *)private_data;
790 v3_chkpt_load_8(ctx, "MASTER_IRR", &(pic->master_irr));
791 v3_chkpt_load_8(ctx, "SLAVE_IRR", &(pic->slave_irr));
793 v3_chkpt_load_8(ctx, "MASTER_ISR", &(pic->master_isr));
794 v3_chkpt_load_8(ctx, "SLAVE_ISR", &(pic->slave_isr));
796 v3_chkpt_load_8(ctx, "MASTER_ELCR", &(pic->master_elcr));
797 v3_chkpt_load_8(ctx, "SLAVE_ELCR", &(pic->slave_elcr));
798 v3_chkpt_load_8(ctx, "MASTER_ELCR_MASK", &(pic->master_elcr_mask));
799 v3_chkpt_load_8(ctx, "SLAVE_ELCR_MASK", &(pic->slave_elcr_mask));
801 v3_chkpt_load_8(ctx, "MASTER_ICW1", &(pic->master_icw1));
802 v3_chkpt_load_8(ctx, "MASTER_ICW2", &(pic->master_icw2));
803 v3_chkpt_load_8(ctx, "MASTER_ICW3", &(pic->master_icw3));
804 v3_chkpt_load_8(ctx, "MASTER_ICW4", &(pic->master_icw4));
807 v3_chkpt_load_8(ctx, "SLAVE_ICW1", &(pic->slave_icw1));
808 v3_chkpt_load_8(ctx, "SLAVE_ICW2", &(pic->slave_icw2));
809 v3_chkpt_load_8(ctx, "SLAVE_ICW3", &(pic->slave_icw3));
810 v3_chkpt_load_8(ctx, "SLAVE_ICW4", &(pic->slave_icw4));
813 v3_chkpt_load_8(ctx, "MASTER_IMR", &(pic->master_imr));
814 v3_chkpt_load_8(ctx, "SLAVE_IMR", &(pic->slave_imr));
815 v3_chkpt_load_8(ctx, "MASTER_OCW2", &(pic->master_ocw2));
816 v3_chkpt_load_8(ctx, "MASTER_OCW3", &(pic->master_ocw3));
817 v3_chkpt_load_8(ctx, "SLAVE_OCW2", &(pic->slave_ocw2));
818 v3_chkpt_load_8(ctx, "SLAVE_OCW3", &(pic->slave_ocw3));
820 v3_chkpt_load_8(ctx, "MASTER_STATE", &(pic->master_state));
821 v3_chkpt_load_8(ctx, "SLAVE_STATE", &(pic->slave_state));
829 static struct v3_device_ops dev_ops = {
830 .free = (int (*)(void *))pic_free,
831 #ifdef V3_CONFIG_CHECKPOINT
841 static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
842 struct pic_internal * state = NULL;
843 char * dev_id = v3_cfg_val(cfg, "ID");
846 // PIC is only usable in non-multicore environments
847 // just hardcode the core context
848 struct guest_info * core = &(vm->cores[0]);
850 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
852 V3_ASSERT(state != NULL);
854 struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, state);
857 PrintError("Could not add device %s\n", dev_id);
864 state->controller_handle = v3_register_intr_controller(core, &intr_ops, state);
865 state->router_handle = v3_register_intr_router(vm, &router_ops, state);
867 state->master_irr = 0;
868 state->master_isr = 0;
869 state->master_elcr = 0;
870 state->master_elcr_mask = 0xf8;
871 state->master_icw1 = 0;
872 state->master_icw2 = 0;
873 state->master_icw3 = 0;
874 state->master_icw4 = 0;
875 state->master_imr = 0;
876 state->master_ocw2 = 0;
877 state->master_ocw3 = 0x02;
878 state->master_state = ICW1;
881 state->slave_irr = 0;
882 state->slave_isr = 0;
883 state->slave_elcr = 0;
884 state->slave_elcr_mask = 0xde;
885 state->slave_icw1 = 0;
886 state->slave_icw2 = 0;
887 state->slave_icw3 = 0;
888 state->slave_icw4 = 0;
889 state->slave_imr = 0;
890 state->slave_ocw2 = 0;
891 state->slave_ocw3 = 0x02;
892 state->slave_state = ICW1;
895 ret |= v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
896 ret |= v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
897 ret |= v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
898 ret |= v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
901 ret |= v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
902 ret |= v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
905 PrintError("Error hooking io ports\n");
906 v3_remove_device(dev);
915 device_register("8259A", pic_init);