2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
22 #include <palacios/vmm_intr.h>
23 #include <palacios/vmm_types.h>
24 #include <palacios/vmm.h>
25 #include <palacios/vmm_dev_mgr.h>
26 #include <palacios/vm_guest.h>
28 #ifndef V3_CONFIG_DEBUG_PIC
30 #define PrintDebug(fmt, args...)
34 typedef enum {RESET, ICW1, ICW2, ICW3, ICW4, READY} pic_state_t;
36 static const uint_t MASTER_PORT1 = 0x20;
37 static const uint_t MASTER_PORT2 = 0x21;
38 static const uint_t SLAVE_PORT1 = 0xA0;
39 static const uint_t SLAVE_PORT2 = 0xA1;
41 static const uint_t ELCR1_PORT = 0x4d0;
42 static const uint_t ELCR2_PORT = 0x4d1;
45 #define IS_ICW1(x) (((x & 0x10) >> 4) == 0x1)
46 #define IS_OCW2(x) (((x & 0x18) >> 3) == 0x0)
47 #define IS_OCW3(x) (((x & 0x18) >> 3) == 0x1)
51 uint_t ic4 : 1; // ICW4 has to be read
52 uint_t sngl : 1; // single (only one PIC)
53 uint_t adi : 1; // call address interval
54 uint_t ltim : 1; // level interrupt mode
66 // Each bit that is set indicates that the IR input has a slave
78 // The ID is the Slave device ID
85 uint_t uPM : 1; // 1=x86
86 uint_t AEOI : 1; // Automatic End of Interrupt
87 uint_t M_S : 1; // only if buffered 1=master,0=slave
88 uint_t BUF : 1; // buffered mode
89 uint_t SFNM : 1; // special fully nexted mode
107 uint_t cw_code : 2; // should be 00
117 uint_t cw_code : 2; // should be 01
124 struct pic_internal {
135 uint8_t master_elcr_mask;
136 uint8_t slave_elcr_mask;
157 pic_state_t master_state;
158 pic_state_t slave_state;
160 struct guest_info * core;
163 int (*ack)(struct guest_info * core, uint32_t irq, void * private_data);
168 void * router_handle;
169 void * controller_handle;
173 static void DumpPICState(struct pic_internal *p)
176 PrintDebug("8259 PIC: master_state=0x%x\n",p->master_state);
177 PrintDebug("8259 PIC: master_irr=0x%x\n",p->master_irr);
178 PrintDebug("8259 PIC: master_isr=0x%x\n",p->master_isr);
179 PrintDebug("8259 PIC: master_imr=0x%x\n",p->master_imr);
181 PrintDebug("8259 PIC: master_ocw2=0x%x\n",p->master_ocw2);
182 PrintDebug("8259 PIC: master_ocw3=0x%x\n",p->master_ocw3);
184 PrintDebug("8259 PIC: master_icw1=0x%x\n",p->master_icw1);
185 PrintDebug("8259 PIC: master_icw2=0x%x\n",p->master_icw2);
186 PrintDebug("8259 PIC: master_icw3=0x%x\n",p->master_icw3);
187 PrintDebug("8259 PIC: master_icw4=0x%x\n",p->master_icw4);
189 PrintDebug("8259 PIC: slave_state=0x%x\n",p->slave_state);
190 PrintDebug("8259 PIC: slave_irr=0x%x\n",p->slave_irr);
191 PrintDebug("8259 PIC: slave_isr=0x%x\n",p->slave_isr);
192 PrintDebug("8259 PIC: slave_imr=0x%x\n",p->slave_imr);
194 PrintDebug("8259 PIC: slave_ocw2=0x%x\n",p->slave_ocw2);
195 PrintDebug("8259 PIC: slave_ocw3=0x%x\n",p->slave_ocw3);
197 PrintDebug("8259 PIC: slave_icw1=0x%x\n",p->slave_icw1);
198 PrintDebug("8259 PIC: slave_icw2=0x%x\n",p->slave_icw2);
199 PrintDebug("8259 PIC: slave_icw3=0x%x\n",p->slave_icw3);
200 PrintDebug("8259 PIC: slave_icw4=0x%x\n",p->slave_icw4);
205 static int pic_raise_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) {
206 struct pic_internal * state = (struct pic_internal*)private_data;
207 uint8_t irq_num = irq->irq;
211 state->master_irr |= 0x04;
214 PrintDebug("8259 PIC: Raising irq %d in the PIC\n", irq_num);
217 state->master_irr |= 0x01 << irq_num;
218 } else if ((irq_num > 7) && (irq_num < 16)) {
219 state->slave_irr |= 0x01 << (irq_num - 8);
221 PrintDebug("8259 PIC: Invalid IRQ raised (%d)\n", irq_num);
225 state->irq_ack_cbs[irq_num].ack = irq->ack;
226 state->irq_ack_cbs[irq_num].private_data = irq->private_data;
228 if (V3_Get_CPU() != vm->cores[0].pcpu_id) {
229 // guest is running on another core, interrupt it to deliver irq
230 v3_interrupt_cpu(vm, 0, 0);
237 static int pic_lower_intr(struct v3_vm_info * vm, void * private_data, struct v3_irq * irq) {
238 struct pic_internal * state = (struct pic_internal*)private_data;
239 uint8_t irq_num = irq->irq;
242 PrintDebug("[pic_lower_intr] IRQ line %d now low\n", irq_num);
245 state->master_irr &= ~(1 << irq_num);
246 if ((state->master_irr & ~(state->master_imr)) == 0) {
247 PrintDebug("\t\tFIXME: Master maybe should do sth\n");
249 } else if ((irq_num > 7) && (irq_num < 16)) {
251 state->slave_irr &= ~(1 << (irq_num - 8));
252 if ((state->slave_irr & (~(state->slave_imr))) == 0) {
253 PrintDebug("\t\tFIXME: Slave maybe should do sth\n");
261 static int pic_intr_pending(struct guest_info * info, void * private_data) {
262 struct pic_internal * state = (struct pic_internal*)private_data;
264 if ((state->master_irr & ~(state->master_imr)) ||
265 (state->slave_irr & ~(state->slave_imr))) {
272 static int pic_get_intr_number(struct guest_info * info, void * private_data) {
273 struct pic_internal * state = (struct pic_internal *)private_data;
277 PrintDebug("8259 PIC: getnum: master_irr: 0x%x master_imr: 0x%x\n", state->master_irr, state->master_imr);
278 PrintDebug("8259 PIC: getnum: slave_irr: 0x%x slave_imr: 0x%x\n", state->slave_irr, state->slave_imr);
280 for (i = 0; i < 16; i++) {
282 if (((state->master_irr & ~(state->master_imr)) >> i) & 0x01) {
283 //state->master_isr |= (0x1 << i);
285 //state->master_irr &= ~(0x1 << i);
286 PrintDebug("8259 PIC: IRQ: %d, master_icw2: %x\n", i, state->master_icw2);
287 irq = i + state->master_icw2;
291 if (((state->slave_irr & ~(state->slave_imr)) >> (i - 8)) & 0x01) {
292 //state->slave_isr |= (0x1 << (i - 8));
293 //state->slave_irr &= ~(0x1 << (i - 8));
294 PrintDebug("8259 PIC: IRQ: %d, slave_icw2: %x\n", i, state->slave_icw2);
295 irq = (i - 8) + state->slave_icw2;
302 if ((i == 15) || (i == 6)) {
310 PrintDebug("8259 PIC: get num is returning %d\n",irq);
317 /* The IRQ number is the number returned by pic_get_intr_number(), not the pin number */
318 static int pic_begin_irq(struct guest_info * info, void * private_data, int irq) {
319 struct pic_internal * state = (struct pic_internal*)private_data;
321 if ((irq >= state->master_icw2) && (irq <= state->master_icw2 + 7)) {
323 } else if ((irq >= state->slave_icw2) && (irq <= state->slave_icw2 + 7)) {
327 // PrintError("8259 PIC: Could not find IRQ (0x%x) to Begin\n",irq);
332 // This should always be true: See pic_get_intr_number
333 if (((state->master_irr & ~(state->master_imr)) >> irq) & 0x01) {
334 state->master_isr |= (0x1 << irq);
336 if (!(state->master_elcr & (0x1 << irq))) {
337 state->master_irr &= ~(0x1 << irq);
340 PrintDebug("8259 PIC: (master) Ignoring begin_irq for %d since I don't own it\n", irq);
344 // This should always be true: See pic_get_intr_number
345 if (((state->slave_irr & ~(state->slave_imr)) >> (irq - 8)) & 0x01) {
346 state->slave_isr |= (0x1 << (irq - 8));
348 if (!(state->slave_elcr & (0x1 << (irq - 8)))) {
349 state->slave_irr &= ~(0x1 << (irq - 8));
352 PrintDebug("8259 PIC: (slave) Ignoring begin_irq for %d since I don't own it\n", irq);
363 static int pic_end_irq(void * private_data, int irq) {
370 static struct intr_ctrl_ops intr_ops = {
371 .intr_pending = pic_intr_pending,
372 .get_intr_number = pic_get_intr_number,
373 .begin_irq = pic_begin_irq
376 static struct intr_router_ops router_ops = {
377 .raise_intr = pic_raise_intr,
378 .lower_intr = pic_lower_intr
382 static int read_master_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
383 struct pic_internal * state = (struct pic_internal *)priv_data;
386 PrintError("8259 PIC: Invalid Read length (rd_Master1)\n");
390 if ((state->master_ocw3 & 0x03) == 0x02) {
391 *(uint8_t *)dst = state->master_irr;
392 } else if ((state->master_ocw3 & 0x03) == 0x03) {
393 *(uint8_t *)dst = state->master_isr;
401 static int read_master_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
402 struct pic_internal * state = (struct pic_internal *)priv_data;
405 PrintError("8259 PIC: Invalid Read length (rd_Master2)\n");
409 *(uint8_t *)dst = state->master_imr;
415 static int read_slave_port1(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
416 struct pic_internal * state = (struct pic_internal *)priv_data;
419 PrintError("8259 PIC: Invalid Read length (rd_Slave1)\n");
423 if ((state->slave_ocw3 & 0x03) == 0x02) {
424 *(uint8_t*)dst = state->slave_irr;
425 } else if ((state->slave_ocw3 & 0x03) == 0x03) {
426 *(uint8_t *)dst = state->slave_isr;
434 static int read_slave_port2(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
435 struct pic_internal * state = (struct pic_internal *)priv_data;
438 PrintError("8259 PIC: Invalid Read length (rd_Slave2)\n");
442 *(uint8_t *)dst = state->slave_imr;
448 static int write_master_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
449 struct pic_internal * state = (struct pic_internal *)priv_data;
450 uint8_t cw = *(uint8_t *)src;
452 PrintDebug("8259 PIC: Write master port 1 with 0x%x\n",cw);
455 PrintError("8259 PIC: Invalid Write length (wr_Master1)\n");
459 v3_clear_pending_intr(core);
463 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Master1)\n", cw);
465 state->master_icw1 = cw;
466 state->master_state = ICW2;
468 } else if (state->master_state == READY) {
470 // handle the EOI here
471 struct ocw2 * cw2 = (struct ocw2*)&cw;
473 PrintDebug("8259 PIC: Handling OCW2 = %x (wr_Master1)\n", cw);
475 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
477 state->master_isr &= ~(0x01 << cw2->level);
481 // ack the irq if requested
482 if (state->irq_ack_cbs[irq].ack) {
483 state->irq_ack_cbs[irq].ack(info, irq, state->irq_ack_cbs[irq].private_data);
487 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
490 PrintDebug("8259 PIC: Pre ISR = %x (wr_Master1)\n", state->master_isr);
491 for (i = 0; i < 8; i++) {
492 if (state->master_isr & (0x01 << i)) {
493 state->master_isr &= ~(0x01 << i);
497 PrintDebug("8259 PIC: Post ISR = %x (wr_Master1)\n", state->master_isr);
498 } else if (!(cw2->EOI) && (cw2->R) && (cw2->SL)) {
499 PrintDebug("8259 PIC: Ignoring set-priority, priorities not implemented (level=%d, wr_Master1)\n", cw2->level);
500 } else if (!(cw2->EOI) && !(cw2->R) && (cw2->SL)) {
501 PrintDebug("8259 PIC: Ignoring no-op (level=%d, wr_Master1)\n", cw2->level);
503 PrintError("8259 PIC: Command not handled, or in error (wr_Master1)\n");
508 if (pic_get_intr_number(core, state) != -1) {
509 PrintError("Interrupt pending after EOI\n");
514 state->master_ocw2 = cw;
515 } else if (IS_OCW3(cw)) {
516 PrintDebug("8259 PIC: Handling OCW3 = %x (wr_Master1)\n", cw);
517 state->master_ocw3 = cw;
519 PrintError("8259 PIC: Invalid OCW to PIC (wr_Master1)\n");
520 PrintError("8259 PIC: CW=%x\n", cw);
524 PrintError("8259 PIC: Invalid PIC State (wr_Master1)\n");
525 PrintError("8259 PIC: CW=%x\n", cw);
532 static int write_master_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
533 struct pic_internal * state = (struct pic_internal *)priv_data;
534 uint8_t cw = *(uint8_t *)src;
536 PrintDebug("8259 PIC: Write master port 2 with 0x%x\n",cw);
539 PrintError("8259 PIC: Invalid Write length (wr_Master2)\n");
543 v3_clear_pending_intr(core);
545 if (state->master_state == ICW2) {
546 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
548 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Master2)\n", cw);
549 state->master_icw2 = cw;
553 if (cw1->sngl == 0) {
554 state->master_state = ICW3;
555 } else if (cw1->ic4 == 1) {
556 state->master_state = ICW4;
558 state->master_state = READY;
563 } else if (state->master_state == ICW3) {
564 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
566 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Master2)\n", cw);
568 state->master_icw3 = cw;
571 state->master_state = ICW4;
573 state->master_state = READY;
576 } else if (state->master_state == ICW4) {
577 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Master2)\n", cw);
578 state->master_icw4 = cw;
579 state->master_state = READY;
580 } else if ((state->master_state == ICW1) || (state->master_state == READY)) {
581 PrintDebug("8259 PIC: Setting IMR = %x (wr_Master2)\n", cw);
582 state->master_imr = cw;
585 PrintError("8259 PIC: Invalid master PIC State (wr_Master2) (state=%d)\n",
586 state->master_state);
593 static int write_slave_port1(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
594 struct pic_internal * state = (struct pic_internal *)priv_data;
595 uint8_t cw = *(uint8_t *)src;
597 PrintDebug("8259 PIC: Write slave port 1 with 0x%x\n",cw);
601 PrintError("8259 PIC: Invalid Write length (wr_Slave1)\n");
605 v3_clear_pending_intr(core);
608 PrintDebug("8259 PIC: Setting ICW1 = %x (wr_Slave1)\n", cw);
609 state->slave_icw1 = cw;
610 state->slave_state = ICW2;
611 } else if (state->slave_state == READY) {
613 // handle the EOI here
614 struct ocw2 * cw2 = (struct ocw2 *)&cw;
616 PrintDebug("8259 PIC: Setting OCW2 = %x (wr_Slave1)\n", cw);
618 if ((cw2->EOI) && (!cw2->R) && (cw2->SL)) {
620 state->slave_isr &= ~(0x01 << cw2->level);
621 } else if ((cw2->EOI) & (!cw2->R) && (!cw2->SL)) {
624 PrintDebug("8259 PIC: Pre ISR = %x (wr_Slave1)\n", state->slave_isr);
625 for (i = 0; i < 8; i++) {
626 if (state->slave_isr & (0x01 << i)) {
627 state->slave_isr &= ~(0x01 << i);
631 PrintDebug("8259 PIC: Post ISR = %x (wr_Slave1)\n", state->slave_isr);
633 PrintError("8259 PIC: Command not handled or invalid (wr_Slave1)\n");
638 if (pic_get_intr_number(core, state) != -1) {
639 PrintError("Interrupt pending after EOI\n");
645 state->slave_ocw2 = cw;
646 } else if (IS_OCW3(cw)) {
647 // Basically sets the IRR/ISR read flag
648 PrintDebug("8259 PIC: Setting OCW3 = %x (wr_Slave1)\n", cw);
649 state->slave_ocw3 = cw;
651 PrintError("8259 PIC: Invalid command work (wr_Slave1)\n");
655 PrintError("8259 PIC: Invalid State writing (wr_Slave1)\n");
662 static int write_slave_port2(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
663 struct pic_internal * state = (struct pic_internal *)priv_data;
664 uint8_t cw = *(uint8_t *)src;
666 PrintDebug("8259 PIC: Write slave port 2 with 0x%x\n",cw);
669 PrintError("8259 PIC: Invalid write length (wr_Slave2)\n");
673 v3_clear_pending_intr(core);
676 if (state->slave_state == ICW2) {
677 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
679 PrintDebug("8259 PIC: Setting ICW2 = %x (wr_Slave2)\n", cw);
681 state->slave_icw2 = cw;
683 if (cw1->sngl == 0) {
684 state->slave_state = ICW3;
685 } else if (cw1->ic4 == 1) {
686 state->slave_state = ICW4;
688 state->slave_state = READY;
691 } else if (state->slave_state == ICW3) {
692 struct icw1 * cw1 = (struct icw1 *)&(state->master_icw1);
694 PrintDebug("8259 PIC: Setting ICW3 = %x (wr_Slave2)\n", cw);
696 state->slave_icw3 = cw;
699 state->slave_state = ICW4;
701 state->slave_state = READY;
704 } else if (state->slave_state == ICW4) {
705 PrintDebug("8259 PIC: Setting ICW4 = %x (wr_Slave2)\n", cw);
706 state->slave_icw4 = cw;
707 state->slave_state = READY;
708 } else if ((state->slave_state == ICW1) || (state->slave_state == READY)) {
709 PrintDebug("8259 PIC: Setting IMR = %x (wr_Slave2)\n", cw);
710 state->slave_imr = cw;
712 PrintError("8259 PIC: Invalid State at write (wr_Slave2)\n");
722 static int read_elcr_port(struct guest_info * core, ushort_t port, void * dst, uint_t length, void * priv_data) {
723 struct pic_internal * state = (struct pic_internal *)priv_data;
726 PrintError("ELCR read of invalid length %d\n", length);
730 if (port == ELCR1_PORT) {
732 *(uint8_t *)dst = state->master_elcr;
733 } else if (port == ELCR2_PORT) {
734 *(uint8_t *)dst = state->slave_elcr;
736 PrintError("Invalid port %x\n", port);
744 static int write_elcr_port(struct guest_info * core, ushort_t port, void * src, uint_t length, void * priv_data) {
745 struct pic_internal * state = (struct pic_internal *)priv_data;
748 PrintError("ELCR read of invalid length %d\n", length);
752 if (port == ELCR1_PORT) {
754 state->master_elcr = (*(uint8_t *)src) & state->master_elcr_mask;
755 } else if (port == ELCR2_PORT) {
756 state->slave_elcr = (*(uint8_t *)src) & state->slave_elcr_mask;
758 PrintError("Invalid port %x\n", port);
767 static int pic_free(struct pic_internal * state) {
768 struct guest_info * core = state->core;
770 v3_remove_intr_controller(core, state->controller_handle);
771 v3_remove_intr_router(core->vm_info, state->router_handle);
777 #ifdef V3_CONFIG_CHECKPOINT
778 static int pic_save(struct v3_chkpt_ctx * ctx, void * private_data) {
779 struct pic_internal * pic = (struct pic_internal *)private_data;
781 v3_chkpt_save_8(ctx, "MASTER_IRR", &(pic->master_irr));
782 v3_chkpt_save_8(ctx, "SLAVE_IRR", &(pic->slave_irr));
784 v3_chkpt_save_8(ctx, "MASTER_ISR", &(pic->master_isr));
785 v3_chkpt_save_8(ctx, "SLAVE_ISR", &(pic->slave_isr));
787 v3_chkpt_save_8(ctx, "MASTER_ELCR", &(pic->master_elcr));
788 v3_chkpt_save_8(ctx, "SLAVE_ELCR", &(pic->slave_elcr));
789 v3_chkpt_save_8(ctx, "MASTER_ELCR_MASK", &(pic->master_elcr_mask));
790 v3_chkpt_save_8(ctx, "SLAVE_ELCR_MASK", &(pic->slave_elcr_mask));
792 v3_chkpt_save_8(ctx, "MASTER_ICW1", &(pic->master_icw1));
793 v3_chkpt_save_8(ctx, "MASTER_ICW2", &(pic->master_icw2));
794 v3_chkpt_save_8(ctx, "MASTER_ICW3", &(pic->master_icw3));
795 v3_chkpt_save_8(ctx, "MASTER_ICW4", &(pic->master_icw4));
798 v3_chkpt_save_8(ctx, "SLAVE_ICW1", &(pic->slave_icw1));
799 v3_chkpt_save_8(ctx, "SLAVE_ICW2", &(pic->slave_icw2));
800 v3_chkpt_save_8(ctx, "SLAVE_ICW3", &(pic->slave_icw3));
801 v3_chkpt_save_8(ctx, "SLAVE_ICW4", &(pic->slave_icw4));
804 v3_chkpt_save_8(ctx, "MASTER_IMR", &(pic->master_imr));
805 v3_chkpt_save_8(ctx, "SLAVE_IMR", &(pic->slave_imr));
806 v3_chkpt_save_8(ctx, "MASTER_OCW2", &(pic->master_ocw2));
807 v3_chkpt_save_8(ctx, "MASTER_OCW3", &(pic->master_ocw3));
808 v3_chkpt_save_8(ctx, "SLAVE_OCW2", &(pic->slave_ocw2));
809 v3_chkpt_save_8(ctx, "SLAVE_OCW3", &(pic->slave_ocw3));
811 v3_chkpt_save_8(ctx, "MASTER_STATE", &(pic->master_state));
812 v3_chkpt_save_8(ctx, "SLAVE_STATE", &(pic->slave_state));
819 static int pic_load(struct v3_chkpt_ctx * ctx, void * private_data) {
820 struct pic_internal * pic = (struct pic_internal *)private_data;
823 v3_chkpt_load_8(ctx, "MASTER_IRR", &(pic->master_irr));
824 v3_chkpt_load_8(ctx, "SLAVE_IRR", &(pic->slave_irr));
826 v3_chkpt_load_8(ctx, "MASTER_ISR", &(pic->master_isr));
827 v3_chkpt_load_8(ctx, "SLAVE_ISR", &(pic->slave_isr));
829 v3_chkpt_load_8(ctx, "MASTER_ELCR", &(pic->master_elcr));
830 v3_chkpt_load_8(ctx, "SLAVE_ELCR", &(pic->slave_elcr));
831 v3_chkpt_load_8(ctx, "MASTER_ELCR_MASK", &(pic->master_elcr_mask));
832 v3_chkpt_load_8(ctx, "SLAVE_ELCR_MASK", &(pic->slave_elcr_mask));
834 v3_chkpt_load_8(ctx, "MASTER_ICW1", &(pic->master_icw1));
835 v3_chkpt_load_8(ctx, "MASTER_ICW2", &(pic->master_icw2));
836 v3_chkpt_load_8(ctx, "MASTER_ICW3", &(pic->master_icw3));
837 v3_chkpt_load_8(ctx, "MASTER_ICW4", &(pic->master_icw4));
840 v3_chkpt_load_8(ctx, "SLAVE_ICW1", &(pic->slave_icw1));
841 v3_chkpt_load_8(ctx, "SLAVE_ICW2", &(pic->slave_icw2));
842 v3_chkpt_load_8(ctx, "SLAVE_ICW3", &(pic->slave_icw3));
843 v3_chkpt_load_8(ctx, "SLAVE_ICW4", &(pic->slave_icw4));
846 v3_chkpt_load_8(ctx, "MASTER_IMR", &(pic->master_imr));
847 v3_chkpt_load_8(ctx, "SLAVE_IMR", &(pic->slave_imr));
848 v3_chkpt_load_8(ctx, "MASTER_OCW2", &(pic->master_ocw2));
849 v3_chkpt_load_8(ctx, "MASTER_OCW3", &(pic->master_ocw3));
850 v3_chkpt_load_8(ctx, "SLAVE_OCW2", &(pic->slave_ocw2));
851 v3_chkpt_load_8(ctx, "SLAVE_OCW3", &(pic->slave_ocw3));
853 v3_chkpt_load_8(ctx, "MASTER_STATE", &(pic->master_state));
854 v3_chkpt_load_8(ctx, "SLAVE_STATE", &(pic->slave_state));
862 static struct v3_device_ops dev_ops = {
863 .free = (int (*)(void *))pic_free,
864 #ifdef V3_CONFIG_CHECKPOINT
874 static int pic_init(struct v3_vm_info * vm, v3_cfg_tree_t * cfg) {
875 struct pic_internal * state = NULL;
876 char * dev_id = v3_cfg_val(cfg, "ID");
879 // PIC is only usable in non-multicore environments
880 // just hardcode the core context
881 struct guest_info * core = &(vm->cores[0]);
883 state = (struct pic_internal *)V3_Malloc(sizeof(struct pic_internal));
886 PrintError("Cannot allocate in init\n");
890 struct vm_device * dev = v3_add_device(vm, dev_id, &dev_ops, state);
893 PrintError("Could not add device %s\n", dev_id);
900 state->controller_handle = v3_register_intr_controller(core, &intr_ops, state);
901 state->router_handle = v3_register_intr_router(vm, &router_ops, state);
903 state->master_irr = 0;
904 state->master_isr = 0;
905 state->master_elcr = 0;
906 state->master_elcr_mask = 0xf8;
907 state->master_icw1 = 0;
908 state->master_icw2 = 0;
909 state->master_icw3 = 0;
910 state->master_icw4 = 0;
911 state->master_imr = 0;
912 state->master_ocw2 = 0;
913 state->master_ocw3 = 0x02;
914 state->master_state = ICW1;
917 state->slave_irr = 0;
918 state->slave_isr = 0;
919 state->slave_elcr = 0;
920 state->slave_elcr_mask = 0xde;
921 state->slave_icw1 = 0;
922 state->slave_icw2 = 0;
923 state->slave_icw3 = 0;
924 state->slave_icw4 = 0;
925 state->slave_imr = 0;
926 state->slave_ocw2 = 0;
927 state->slave_ocw3 = 0x02;
928 state->slave_state = ICW1;
931 ret |= v3_dev_hook_io(dev, MASTER_PORT1, &read_master_port1, &write_master_port1);
932 ret |= v3_dev_hook_io(dev, MASTER_PORT2, &read_master_port2, &write_master_port2);
933 ret |= v3_dev_hook_io(dev, SLAVE_PORT1, &read_slave_port1, &write_slave_port1);
934 ret |= v3_dev_hook_io(dev, SLAVE_PORT2, &read_slave_port2, &write_slave_port2);
937 ret |= v3_dev_hook_io(dev, ELCR1_PORT, &read_elcr_port, &write_elcr_port);
938 ret |= v3_dev_hook_io(dev, ELCR2_PORT, &read_elcr_port, &write_elcr_port);
941 PrintError("Error hooking io ports\n");
942 v3_remove_device(dev);
951 device_register("8259A", pic_init);