2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
20 #include <devices/8254.h>
21 #include <palacios/vmm.h>
22 #include <palacios/vmm_time.h>
23 #include <palacios/vmm_util.h>
24 #include <palacios/vmm_intr.h>
30 #define PrintDebug(fmt, args...)
36 #define OSC_HZ 1193182
39 /* The 8254 has three counters and one control port */
40 #define CHANNEL0_PORT 0x40
41 #define CHANNEL1_PORT 0x41
42 #define CHANNEL2_PORT 0x42
43 #define COMMAND_PORT 0x43
46 #define PIT_INTR_NUM 0
48 /* The order of these typedefs is important because the numerical values correspond to the
49 * values coming from the io ports
51 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
52 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
53 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
54 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
58 channel_access_mode_t access_mode;
59 channel_access_state_t access_state;
60 channel_run_state_t run_state;
62 channel_op_mode_t op_mode;
65 // Time til interrupt trigger
68 ushort_t reload_value;
70 ushort_t latched_value;
72 enum {NOTLATCHED, LATCHED} latch_state;
74 enum {LSB, MSB} read_state;
76 uint_t output_pin : 1;
77 uint_t gate_input_pin : 1;
96 uint_t access_mode : 2;
100 struct pit_rdb_cmd_word {
101 uint_t rsvd : 1; // SBZ
105 uint_t latch_status : 1;
106 uint_t latch_count : 1;
107 uint_t readback_cmd : 2; // Must Be 0x3
110 struct pit_rdb_status_word {
113 uint_t access_mode : 2;
114 uint_t null_count : 1;
115 uint_t pin_state : 1;
121 * This should call out to handle_SQR_WAVE_tics, etc...
123 // Returns true if the the output signal changed state
124 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
125 uint_t channel_cycles = 0;
126 uint_t output_changed = 0;
128 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
129 if (ch->run_state == PENDING) {
131 ch->counter = ch->reload_value;
133 if (ch->op_mode == SQR_WAVE) {
134 ch->counter -= ch->counter % 2;
137 ch->run_state = RUNNING;
138 } else if (ch->run_state != RUNNING) {
139 return output_changed;
143 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
144 PrintTraceLL(ch->counter);
147 if (ch->op_mode == SQR_WAVE) {
151 if (ch->counter > oscillations) {
152 ch->counter -= oscillations;
153 return output_changed;
155 ushort_t reload_val = ch->reload_value;
157 // TODO: Check this....
158 // Is this correct???
159 if (reload_val == 0) {
163 oscillations -= ch->counter;
167 if (ch->op_mode == SQR_WAVE) {
168 reload_val -= reload_val % 2;
171 channel_cycles += oscillations / reload_val;
172 oscillations = oscillations % reload_val;
174 ch->counter = reload_val - oscillations;
177 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
181 switch (ch->op_mode) {
182 case IRQ_ON_TERM_CNT:
183 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
189 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
195 // See the data sheet: we ignore the output pin cycle...
196 if (channel_cycles > 0) {
201 ch->output_pin = (ch->output_pin + 1) % 2;
203 if (ch->output_pin == 1) {
218 return output_changed;
223 static void pit_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
224 struct vm_device * dev = (struct vm_device *)private_data;
225 struct pit * state = (struct pit *)dev->private_data;
226 // ullong_t tmp_ctr = state->pit_counter;
228 uint_t oscillations = 0;
232 PrintDebug("updating cpu_cycles=");
233 PrintTraceLL(cpu_cycles);
236 PrintDebug("pit_counter=");
237 PrintTraceLL(state->pit_counter);
240 PrintDebug("pit_reload=");
241 PrintTraceLL(state->pit_reload);
245 if (state->pit_counter > cpu_cycles) {
247 state->pit_counter -= cpu_cycles;
249 ushort_t reload_val = state->pit_reload;
250 // Take off the first part
251 cpu_cycles -= state->pit_counter;
252 state->pit_counter = 0;
255 if (cpu_cycles > state->pit_reload) {
256 // how many full oscillations
258 //PrintError("cpu_cycles = %p, reload = %p...\n",
259 // (void *)(addr_t)cpu_cycles,
260 // (void *)(addr_t)state->pit_reload);
262 // How do we check for a one shot....
263 if (state->pit_reload == 0) {
267 tmp_cycles = cpu_cycles;
271 cpu_cycles = tmp_cycles % state->pit_reload;
272 tmp_cycles = tmp_cycles / state->pit_reload;
274 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
277 oscillations += tmp_cycles;
280 // update counter with remainder (mod reload)
281 state->pit_counter = state->pit_reload - cpu_cycles;
283 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
284 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
286 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
287 v3_raise_irq(dev->vm, 0);
290 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
291 //handle_crystal_tics(dev, &(state->ch_2), oscillations);
302 /* This should call out to handle_SQR_WAVE_write, etc...
304 static int handle_channel_write(struct channel * ch, char val) {
306 switch (ch->access_state) {
309 ushort_t tmp_val = ((ushort_t)val) << 8;
310 ch->reload_value &= 0x00ff;
311 ch->reload_value |= tmp_val;
314 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
315 ch->run_state = PENDING;
318 if (ch->access_mode == LOBYTE_HIBYTE) {
319 ch->access_state = WAITING_LOBYTE;
322 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
323 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
327 ch->reload_value &= 0xff00;
328 ch->reload_value |= val;
330 if (ch->access_mode == LOBYTE_HIBYTE) {
331 ch->access_state = WAITING_HIBYTE;
332 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
333 ch->run_state = PENDING;
336 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
337 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
344 switch (ch->op_mode) {
345 case IRQ_ON_TERM_CNT:
367 static int handle_channel_read(struct channel * ch, char * val) {
371 if (ch->latch_state == NOTLATCHED) {
372 myval = &(ch->counter);
374 myval = &(ch->latched_value);
377 if (ch->read_state == LSB) {
378 *val = ((char*)myval)[0]; // little endian
379 ch->read_state = MSB;
381 *val = ((char*)myval)[1];
382 ch->read_state = LSB;
383 if (ch->latch_state == LATCHED) {
384 ch->latch_state = NOTLATCHED;
396 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
397 ch->op_mode = cmd.op_mode;
398 ch->access_mode = cmd.access_mode;
403 switch (cmd.access_mode) {
405 if (ch->latch_state == NOTLATCHED) {
406 ch->latched_value = ch->counter;
407 ch->latch_state = LATCHED;
411 ch->access_state = WAITING_HIBYTE;
415 ch->access_state = WAITING_LOBYTE;
420 switch (cmd.op_mode) {
421 case IRQ_ON_TERM_CNT:
444 static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
445 struct pit * state = (struct pit *)dev->private_data;
446 char * val = (char *)dst;
449 PrintError("8254 PIT: Invalid Read Write length \n");
453 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
457 if (handle_channel_read(&(state->ch_0), val) == -1) {
462 if (handle_channel_read(&(state->ch_1), val) == -1) {
467 if (handle_channel_read(&(state->ch_2), val) == -1) {
472 PrintError("8254 PIT: Read from invalid port (%d)\n", port);
481 static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
482 struct pit * state = (struct pit *)dev->private_data;
483 char val = *(char *)src;
486 PrintError("8254 PIT: Invalid Write Length\n");
490 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
495 if (handle_channel_write(&(state->ch_0), val) == -1) {
500 if (handle_channel_write(&(state->ch_1), val) == -1) {
505 if (handle_channel_write(&(state->ch_2), val) == -1) {
510 PrintError("8254 PIT: Write to invalid port (%d)\n", port);
520 static int pit_write_command(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
521 struct pit * state = (struct pit *)dev->private_data;
522 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
524 PrintDebug("8254 PIT: Write to PIT Command port\n");
525 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
527 PrintError("8254 PIT: Write of Invalid length to command port\n");
531 switch (cmd->channel) {
533 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
538 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
543 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
562 static struct vm_timer_ops timer_ops = {
563 .update_time = pit_update_time,
567 static void init_channel(struct channel * ch) {
568 ch->run_state = NOT_RUNNING;
569 ch->access_state = NOT_WAITING;
574 ch->reload_value = 0;
576 ch->gate_input_pin = 0;
578 ch->latched_value = 0;
579 ch->latch_state = NOTLATCHED;
580 ch->read_state = LSB;
586 static int pit_init(struct vm_device * dev) {
587 struct pit * state = (struct pit *)dev->private_data;
588 uint_t cpu_khz = V3_CPU_KHZ();
589 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
591 v3_dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
592 v3_dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
593 v3_dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
594 v3_dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
597 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
598 PrintTraceLL(reload_val);
602 v3_add_timer(dev->vm, &timer_ops, dev);
604 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
606 do_divll(reload_val, OSC_HZ);
607 state->pit_counter = reload_val;
608 state->pit_reload = reload_val;
612 init_channel(&(state->ch_0));
613 init_channel(&(state->ch_1));
614 init_channel(&(state->ch_2));
617 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
618 PrintTraceLL(state->pit_counter);
625 static int pit_deinit(struct vm_device * dev) {
631 static struct vm_device_ops dev_ops = {
633 .deinit = pit_deinit,
641 struct vm_device * v3_create_pit() {
642 struct pit * pit_state = NULL;
643 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
644 V3_ASSERT(pit_state != NULL);
646 struct vm_device * dev = v3_create_device("PIT", &dev_ops, pit_state);