1 /* (c) 2008, Jack Lange <jarusl@cs.northwestern.edu> */
2 /* (c) 2008, The V3VEE Project <http://www.v3vee.org> */
4 #include <devices/8254.h>
5 #include <palacios/vmm.h>
6 #include <palacios/vmm_time.h>
7 #include <palacios/vmm_util.h>
8 #include <palacios/vmm_intr.h>
14 #define PrintDebug(fmt, args...)
20 #define OSC_HZ 1193182
23 /* The 8254 has three counters and one control port */
24 #define CHANNEL0_PORT 0x40
25 #define CHANNEL1_PORT 0x41
26 #define CHANNEL2_PORT 0x42
27 #define COMMAND_PORT 0x43
30 #define PIT_INTR_NUM 0
32 /* The order of these typedefs is important because the numerical values correspond to the
33 * values coming from the io ports
35 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
36 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
37 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
38 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
42 channel_access_mode_t access_mode;
43 channel_access_state_t access_state;
44 channel_run_state_t run_state;
46 channel_op_mode_t op_mode;
49 // Time til interrupt trigger
52 ushort_t reload_value;
54 ushort_t latched_value;
56 enum {NOTLATCHED, LATCHED} latch_state;
58 enum {LSB, MSB} read_state;
60 uint_t output_pin : 1;
61 uint_t gate_input_pin : 1;
80 uint_t access_mode : 2;
84 struct pit_rdb_cmd_word {
85 uint_t rsvd : 1; // SBZ
89 uint_t latch_status : 1;
90 uint_t latch_count : 1;
91 uint_t readback_cmd : 2; // Must Be 0x3
94 struct pit_rdb_status_word {
97 uint_t access_mode : 2;
98 uint_t null_count : 1;
105 * This should call out to handle_SQR_WAVE_tics, etc...
107 // Returns true if the the output signal changed state
108 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
109 uint_t channel_cycles = 0;
110 uint_t output_changed = 0;
112 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
113 if (ch->run_state == PENDING) {
115 ch->counter = ch->reload_value;
117 if (ch->op_mode == SQR_WAVE) {
118 ch->counter -= ch->counter % 2;
121 ch->run_state = RUNNING;
122 } else if (ch->run_state != RUNNING) {
123 return output_changed;
127 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
128 PrintTraceLL(ch->counter);
131 if (ch->op_mode == SQR_WAVE) {
135 if (ch->counter > oscillations) {
136 ch->counter -= oscillations;
137 return output_changed;
139 ushort_t reload_val = ch->reload_value;
140 oscillations -= ch->counter;
145 if (ch->op_mode == SQR_WAVE) {
146 reload_val -= reload_val % 2;
149 channel_cycles += oscillations / reload_val;
150 oscillations = oscillations % reload_val;
152 ch->counter = reload_val - oscillations;
155 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
159 switch (ch->op_mode) {
160 case IRQ_ON_TERM_CNT:
161 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
167 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
173 // See the data sheet: we ignore the output pin cycle...
174 if (channel_cycles > 0) {
179 ch->output_pin = (ch->output_pin + 1) % 2;
181 if (ch->output_pin == 1) {
196 return output_changed;
201 static void pit_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
202 struct vm_device * dev = (struct vm_device *)private_data;
203 struct pit * state = (struct pit *)dev->private_data;
204 // ullong_t tmp_ctr = state->pit_counter;
206 uint_t oscillations = 0;
210 PrintDebug("updating cpu_cycles=");
211 PrintTraceLL(cpu_cycles);
214 PrintDebug("pit_counter=");
215 PrintTraceLL(state->pit_counter);
218 PrintDebug("pit_reload=");
219 PrintTraceLL(state->pit_reload);
223 if (state->pit_counter > cpu_cycles) {
225 state->pit_counter -= cpu_cycles;
228 // Take off the first part
229 cpu_cycles -= state->pit_counter;
230 state->pit_counter = 0;
233 if (cpu_cycles > state->pit_reload) {
234 // how many full oscillations
235 tmp_cycles = cpu_cycles;
237 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
239 oscillations += tmp_cycles;
242 // update counter with remainder (mod reload)
243 state->pit_counter = state->pit_reload - cpu_cycles;
245 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
246 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
248 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
249 v3_raise_irq(dev->vm, 0);
252 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
253 //handle_crystal_tics(dev, &(state->ch_2), oscillations);
264 /* This should call out to handle_SQR_WAVE_write, etc...
266 static int handle_channel_write(struct channel * ch, char val) {
268 switch (ch->access_state) {
271 ushort_t tmp_val = ((ushort_t)val) << 8;
272 ch->reload_value &= 0x00ff;
273 ch->reload_value |= tmp_val;
276 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
277 ch->run_state = PENDING;
280 if (ch->access_mode == LOBYTE_HIBYTE) {
281 ch->access_state = WAITING_LOBYTE;
284 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
285 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
289 ch->reload_value &= 0xff00;
290 ch->reload_value |= val;
292 if (ch->access_mode == LOBYTE_HIBYTE) {
293 ch->access_state = WAITING_HIBYTE;
294 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
295 ch->run_state = PENDING;
298 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
299 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
306 switch (ch->op_mode) {
307 case IRQ_ON_TERM_CNT:
329 static int handle_channel_read(struct channel * ch, char * val) {
333 if (ch->latch_state == NOTLATCHED) {
334 myval = &(ch->counter);
336 myval = &(ch->latched_value);
339 if (ch->read_state == LSB) {
340 *val = ((char*)myval)[0]; // little endian
341 ch->read_state = MSB;
343 *val = ((char*)myval)[1];
344 ch->read_state = LSB;
345 if (ch->latch_state == LATCHED) {
346 ch->latch_state = NOTLATCHED;
358 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
359 ch->op_mode = cmd.op_mode;
360 ch->access_mode = cmd.access_mode;
365 switch (cmd.access_mode) {
367 if (ch->latch_state == NOTLATCHED) {
368 ch->latched_value = ch->counter;
369 ch->latch_state = LATCHED;
373 ch->access_state = WAITING_HIBYTE;
377 ch->access_state = WAITING_LOBYTE;
382 switch (cmd.op_mode) {
383 case IRQ_ON_TERM_CNT:
406 static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
407 struct pit * state = (struct pit *)dev->private_data;
408 char * val = (char *)dst;
411 PrintError("8254 PIT: Invalid Read Write length \n");
415 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
419 if (handle_channel_read(&(state->ch_0), val) == -1) {
424 if (handle_channel_read(&(state->ch_1), val) == -1) {
429 if (handle_channel_read(&(state->ch_2), val) == -1) {
434 PrintError("8254 PIT: Read from invalid port (%d)\n", port);
443 static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
444 struct pit * state = (struct pit *)dev->private_data;
445 char val = *(char *)src;
448 PrintError("8254 PIT: Invalid Write Length\n");
452 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
457 if (handle_channel_write(&(state->ch_0), val) == -1) {
462 if (handle_channel_write(&(state->ch_1), val) == -1) {
467 if (handle_channel_write(&(state->ch_2), val) == -1) {
472 PrintError("8254 PIT: Write to invalid port (%d)\n", port);
482 static int pit_write_command(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
483 struct pit * state = (struct pit *)dev->private_data;
484 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
486 PrintDebug("8254 PIT: Write to PIT Command port\n");
487 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
489 PrintError("8254 PIT: Write of Invalid length to command port\n");
493 switch (cmd->channel) {
495 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
500 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
505 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
524 static struct vm_timer_ops timer_ops = {
525 .update_time = pit_update_time,
529 static void init_channel(struct channel * ch) {
530 ch->run_state = NOT_RUNNING;
531 ch->access_state = NOT_WAITING;
536 ch->reload_value = 0;
538 ch->gate_input_pin = 0;
540 ch->latched_value = 0;
541 ch->latch_state = NOTLATCHED;
542 ch->read_state = LSB;
548 static int pit_init(struct vm_device * dev) {
549 struct pit * state = (struct pit *)dev->private_data;
550 uint_t cpu_khz = V3_CPU_KHZ();
551 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
553 dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
554 dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
555 dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
556 dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
559 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
560 PrintTraceLL(reload_val);
564 v3_add_timer(dev->vm, &timer_ops, dev);
566 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
568 do_divll(reload_val, OSC_HZ);
569 state->pit_counter = reload_val;
570 state->pit_reload = reload_val;
574 init_channel(&(state->ch_0));
575 init_channel(&(state->ch_1));
576 init_channel(&(state->ch_2));
579 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
580 PrintTraceLL(state->pit_counter);
587 static int pit_deinit(struct vm_device * dev) {
593 static struct vm_device_ops dev_ops = {
595 .deinit = pit_deinit,
603 struct vm_device * create_pit() {
604 struct pit * pit_state = NULL;
605 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
606 V3_ASSERT(pit_state != NULL);
608 struct vm_device * dev = create_device("PIT", &dev_ops, pit_state);