2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #include <palacios/vmm.h>
22 #include <palacios/vmm_dev_mgr.h>
23 #include <palacios/vmm_time.h>
24 #include <palacios/vmm_util.h>
25 #include <palacios/vmm_intr.h>
29 #ifndef CONFIG_DEBUG_PIT
31 #define PrintDebug(fmt, args...)
37 #define OSC_HZ 1193182
40 /* The 8254 has three counters and one control port */
41 #define CHANNEL0_PORT 0x40
42 #define CHANNEL1_PORT 0x41
43 #define CHANNEL2_PORT 0x42
44 #define COMMAND_PORT 0x43
47 #define PIT_INTR_NUM 0
49 /* The order of these typedefs is important because the numerical values correspond to the
50 * values coming from the io ports
52 typedef enum {NOT_RUNNING, PENDING, RUNNING} channel_run_state_t;
53 typedef enum {NOT_WAITING, WAITING_LOBYTE, WAITING_HIBYTE} channel_access_state_t;
54 typedef enum {LATCH_COUNT, LOBYTE_ONLY, HIBYTE_ONLY, LOBYTE_HIBYTE} channel_access_mode_t;
55 typedef enum {IRQ_ON_TERM_CNT, ONE_SHOT, RATE_GEN, SQR_WAVE, SW_STROBE, HW_STROBE} channel_op_mode_t;
59 channel_access_mode_t access_mode;
60 channel_access_state_t access_state;
61 channel_run_state_t run_state;
63 channel_op_mode_t op_mode;
66 // Time til interrupt trigger
69 ushort_t reload_value;
71 ushort_t latched_value;
73 enum {NOTLATCHED, LATCHED} latch_state;
75 enum {LSB, MSB} read_state;
77 uint_t output_pin : 1;
78 uint_t gate_input_pin : 1;
97 uint_t access_mode : 2;
101 struct pit_rdb_cmd_word {
102 uint_t rsvd : 1; // SBZ
106 uint_t latch_status : 1;
107 uint_t latch_count : 1;
108 uint_t readback_cmd : 2; // Must Be 0x3
111 struct pit_rdb_status_word {
114 uint_t access_mode : 2;
115 uint_t null_count : 1;
116 uint_t pin_state : 1;
122 * This should call out to handle_SQR_WAVE_tics, etc...
124 // Returns true if the the output signal changed state
125 static int handle_crystal_tics(struct vm_device * dev, struct channel * ch, uint_t oscillations) {
126 uint_t channel_cycles = 0;
127 uint_t output_changed = 0;
129 // PrintDebug("8254 PIT: %d crystal tics\n", oscillations);
130 if (ch->run_state == PENDING) {
132 ch->counter = ch->reload_value;
134 if (ch->op_mode == SQR_WAVE) {
135 ch->counter -= ch->counter % 2;
138 ch->run_state = RUNNING;
139 } else if (ch->run_state != RUNNING) {
140 return output_changed;
144 PrintDebug("8254 PIT: Channel Run State = %d, counter=", ch->run_state);
145 PrintTraceLL(ch->counter);
148 if (ch->op_mode == SQR_WAVE) {
152 if (ch->counter > oscillations) {
153 ch->counter -= oscillations;
154 return output_changed;
156 ushort_t reload_val = ch->reload_value;
158 if (ch->op_mode == SW_STROBE) {
162 // TODO: Check this....
163 // Is this correct???
164 if (reload_val == 0) {
168 oscillations -= ch->counter;
172 if (ch->op_mode == SQR_WAVE) {
173 reload_val -= reload_val % 2;
176 channel_cycles += oscillations / reload_val;
177 oscillations = oscillations % reload_val;
179 ch->counter = reload_val - oscillations;
182 // PrintDebug("8254 PIT: Channel Cycles: %d\n", channel_cycles);
186 switch (ch->op_mode) {
187 case IRQ_ON_TERM_CNT:
188 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
194 if ((channel_cycles > 0) && (ch->output_pin == 0)) {
200 // See the data sheet: we ignore the output pin cycle...
201 if (channel_cycles > 0) {
206 ch->output_pin = (ch->output_pin + 1) % 2;
208 if (ch->output_pin == 1) {
215 if (channel_cycles > 0) {
216 if (ch->output_pin == 1) {
223 PrintError("Hardware strobe not implemented\n");
230 return output_changed;
235 static void pit_update_time(ullong_t cpu_cycles, ullong_t cpu_freq, void * private_data) {
236 struct vm_device * dev = (struct vm_device *)private_data;
237 struct pit * state = (struct pit *)dev->private_data;
238 // ullong_t tmp_ctr = state->pit_counter;
240 uint_t oscillations = 0;
244 PrintDebug("updating cpu_cycles=");
245 PrintTraceLL(cpu_cycles);
248 PrintDebug("pit_counter=");
249 PrintTraceLL(state->pit_counter);
252 PrintDebug("pit_reload=");
253 PrintTraceLL(state->pit_reload);
257 if (state->pit_counter > cpu_cycles) {
259 state->pit_counter -= cpu_cycles;
261 ushort_t reload_val = state->pit_reload;
262 // Take off the first part
263 cpu_cycles -= state->pit_counter;
264 state->pit_counter = 0;
267 if (cpu_cycles > state->pit_reload) {
268 // how many full oscillations
270 //PrintError("cpu_cycles = %p, reload = %p...\n",
271 // (void *)(addr_t)cpu_cycles,
272 // (void *)(addr_t)state->pit_reload);
274 // How do we check for a one shot....
275 if (state->pit_reload == 0) {
279 tmp_cycles = cpu_cycles;
283 cpu_cycles = tmp_cycles % state->pit_reload;
284 tmp_cycles = tmp_cycles / state->pit_reload;
286 cpu_cycles = do_divll(tmp_cycles, state->pit_reload);
289 oscillations += tmp_cycles;
292 // update counter with remainder (mod reload)
293 state->pit_counter = state->pit_reload - cpu_cycles;
295 //PrintDebug("8254 PIT: Handling %d crystal tics\n", oscillations);
296 if (handle_crystal_tics(dev, &(state->ch_0), oscillations) == 1) {
298 PrintDebug("8254 PIT: Injecting Timer interrupt to guest\n");
299 v3_raise_irq(dev->vm, 0);
302 //handle_crystal_tics(dev, &(state->ch_1), oscillations);
303 //handle_crystal_tics(dev, &(state->ch_2), oscillations);
314 /* This should call out to handle_SQR_WAVE_write, etc...
316 static int handle_channel_write(struct channel * ch, char val) {
318 switch (ch->access_state) {
321 ushort_t tmp_val = ((ushort_t)val) << 8;
322 ch->reload_value &= 0x00ff;
323 ch->reload_value |= tmp_val;
326 if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)){
327 ch->run_state = PENDING;
330 if (ch->access_mode == LOBYTE_HIBYTE) {
331 ch->access_state = WAITING_LOBYTE;
334 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
335 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
339 ch->reload_value &= 0xff00;
340 ch->reload_value |= val;
342 if (ch->access_mode == LOBYTE_HIBYTE) {
343 ch->access_state = WAITING_HIBYTE;
344 } else if ((ch->op_mode != RATE_GEN) || (ch->run_state != RUNNING)) {
345 ch->run_state = PENDING;
348 PrintDebug("8254 PIT: updated channel counter: %d\n", ch->reload_value);
349 PrintDebug("8254 PIT: Channel Run State=%d\n", ch->run_state);
352 PrintError("Invalid Access state\n");
357 switch (ch->op_mode) {
358 case IRQ_ON_TERM_CNT:
374 PrintError("Invalid OP_MODE: %d\n", ch->op_mode);
384 static int handle_channel_read(struct channel * ch, char * val) {
388 if (ch->latch_state == NOTLATCHED) {
389 myval = &(ch->counter);
391 myval = &(ch->latched_value);
394 if (ch->read_state == LSB) {
395 *val = ((char*)myval)[0]; // little endian
396 ch->read_state = MSB;
398 *val = ((char*)myval)[1];
399 ch->read_state = LSB;
400 if (ch->latch_state == LATCHED) {
401 ch->latch_state = NOTLATCHED;
413 static int handle_channel_cmd(struct channel * ch, struct pit_cmd_word cmd) {
414 ch->op_mode = cmd.op_mode;
415 ch->access_mode = cmd.access_mode;
420 switch (cmd.access_mode) {
422 if (ch->latch_state == NOTLATCHED) {
423 ch->latched_value = ch->counter;
424 ch->latch_state = LATCHED;
428 ch->access_state = WAITING_HIBYTE;
432 ch->access_state = WAITING_LOBYTE;
437 switch (cmd.op_mode) {
438 case IRQ_ON_TERM_CNT:
454 PrintError("Invalid OP_MODE: %d\n", cmd.op_mode);
465 static int pit_read_channel(ushort_t port, void * dst, uint_t length, struct vm_device * dev) {
466 struct pit * state = (struct pit *)dev->private_data;
467 char * val = (char *)dst;
470 PrintError("8254 PIT: Invalid Read Write length \n");
474 PrintDebug("8254 PIT: Read of PIT Channel %d\n", port - CHANNEL0_PORT);
478 if (handle_channel_read(&(state->ch_0), val) == -1) {
479 PrintError("CHANNEL0 read error\n");
484 if (handle_channel_read(&(state->ch_1), val) == -1) {
485 PrintError("CHANNEL1 read error\n");
490 if (handle_channel_read(&(state->ch_2), val) == -1) {
491 PrintError("CHANNEL2 read error\n");
496 PrintError("8254 PIT: Read from invalid port (%d)\n", port);
505 static int pit_write_channel(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
506 struct pit * state = (struct pit *)dev->private_data;
507 char val = *(char *)src;
510 PrintError("8254 PIT: Invalid Write Length\n");
514 PrintDebug("8254 PIT: Write to PIT Channel %d (%x)\n", port - CHANNEL0_PORT, *(char*)src);
519 if (handle_channel_write(&(state->ch_0), val) == -1) {
520 PrintError("CHANNEL0 write error\n");
525 if (handle_channel_write(&(state->ch_1), val) == -1) {
526 PrintError("CHANNEL1 write error\n");
531 if (handle_channel_write(&(state->ch_2), val) == -1) {
532 PrintError("CHANNEL2 write error\n");
537 PrintError("8254 PIT: Write to invalid port (%d)\n", port);
547 static int pit_write_command(ushort_t port, void * src, uint_t length, struct vm_device * dev) {
548 struct pit * state = (struct pit *)dev->private_data;
549 struct pit_cmd_word * cmd = (struct pit_cmd_word *)src;
551 PrintDebug("8254 PIT: Write to PIT Command port\n");
552 PrintDebug("8254 PIT: Writing to channel %d (access_mode = %d, op_mode = %d)\n", cmd->channel, cmd->access_mode, cmd->op_mode);
554 PrintError("8254 PIT: Write of Invalid length to command port\n");
558 switch (cmd->channel) {
560 if (handle_channel_cmd(&(state->ch_0), *cmd) == -1) {
561 PrintError("CHANNEL0 command error\n");
566 if (handle_channel_cmd(&(state->ch_1), *cmd) == -1) {
567 PrintError("CHANNEL1 command error\n");
572 if (handle_channel_cmd(&(state->ch_2), *cmd) == -1) {
573 PrintError("CHANNEL2 command error\n");
579 PrintError("Read back command not implemented\n");
593 static struct vm_timer_ops timer_ops = {
594 .update_time = pit_update_time,
598 static void init_channel(struct channel * ch) {
599 ch->run_state = NOT_RUNNING;
600 ch->access_state = NOT_WAITING;
605 ch->reload_value = 0;
607 ch->gate_input_pin = 0;
609 ch->latched_value = 0;
610 ch->latch_state = NOTLATCHED;
611 ch->read_state = LSB;
619 static int pit_free(struct vm_device * dev) {
625 static struct v3_device_ops dev_ops = {
634 static int pit_init(struct guest_info * info, void * cfg_data) {
635 struct pit * pit_state = NULL;
636 struct vm_device * dev = NULL;
638 uint_t cpu_khz = V3_CPU_KHZ();
639 ullong_t reload_val = (ullong_t)cpu_khz * 1000;
641 pit_state = (struct pit *)V3_Malloc(sizeof(struct pit));
642 V3_ASSERT(pit_state != NULL);
644 dev = v3_allocate_device("PIT", &dev_ops, pit_state);
646 if (v3_attach_device(info, dev) == -1) {
647 PrintError("Could not attach device %s\n", "PIT");
651 v3_dev_hook_io(dev, CHANNEL0_PORT, &pit_read_channel, &pit_write_channel);
652 v3_dev_hook_io(dev, CHANNEL1_PORT, &pit_read_channel, &pit_write_channel);
653 v3_dev_hook_io(dev, CHANNEL2_PORT, &pit_read_channel, &pit_write_channel);
654 v3_dev_hook_io(dev, COMMAND_PORT, NULL, &pit_write_command);
656 #ifdef CONFIG_DEBUG_PIT
657 PrintDebug("8254 PIT: OSC_HZ=%d, reload_val=", OSC_HZ);
658 PrintTraceLL(reload_val);
662 v3_add_timer(info, &timer_ops, dev);
664 // Get cpu frequency and calculate the global pit oscilattor counter/cycle
666 do_divll(reload_val, OSC_HZ);
667 pit_state->pit_counter = reload_val;
668 pit_state->pit_reload = reload_val;
672 init_channel(&(pit_state->ch_0));
673 init_channel(&(pit_state->ch_1));
674 init_channel(&(pit_state->ch_2));
676 #ifdef CONFIG_DEBUG_PIT
677 PrintDebug("8254 PIT: CPU MHZ=%d -- pit count=", cpu_khz / 1000);
678 PrintTraceLL(pit_state->pit_counter);
686 device_register("8254_PIT", pit_init);