2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Jack Lange <jarusl@cs.northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
21 #ifndef __VMM_PAGING_H__
22 #define __VMM_PAGING_H__
27 #include <palacios/vmm_types.h>
28 #include <palacios/vmm_util.h>
33 In the following, when we say "page table", we mean the whole 2 or 4 layer
34 page table (PDEs, PTEs), etc.
37 guest-visible paging state
38 This is the state that the guest thinks the machine is using
40 - guest physical memory
41 The physical memory addresses the guest is allowed to use
42 (see shadow page maps, below)
44 (we care about when the current one changes)
45 - guest paging registers (these are never written to hardware)
51 This the state that the machine will actually use when the guest
52 is running. It consists of:
53 - current shadow page table
54 This is the page table actually useed when the guest is running.
55 It is changed/regenerated when the guest page table changes
56 It mostly reflects the guest page table, except that it restricts
57 physical addresses to those the VMM allocates to the guest.
59 This is a mapping from guest physical memory addresses to
60 the current location of the guest physical memory content.
61 It maps from regions of physical memory addresses to regions
62 located in physical memory or elsewhere.
63 (8192,16384) -> MEM(8912,...)
64 (0,8191) -> DISK(65536,..)
65 - guest paging registers (these are written to guest state)
70 This is the state we expect to be operative when the VMM is running.
71 Typically, this is set up by the host os into which we have embedded
72 the VMM, but we include the description here for clarity.
74 This is the page table we use when we are executing in
75 the VMM (or the host os)
81 The reason why the shadow paging state and the host paging state are
82 distinct is to permit the guest to use any virtual address it wants,
83 irrespective of the addresses the VMM or the host os use. These guest
84 virtual addresses are reflected in the shadow paging state. When we
85 exit from the guest, we switch to the host paging state so that any
86 virtual addresses that overlap between the guest and VMM/host now map
87 to the physical addresses epxected by the VMM/host. On AMD SVM, this
88 switch is done by the hardware. On Intel VT, the switch is done
89 by the hardware as well, but we are responsible for manually updating
90 the host state in the vmcs before entering the guest.
96 #define MAX_PTE32_ENTRIES 1024
97 #define MAX_PDE32_ENTRIES 1024
99 #define MAX_PTE32PAE_ENTRIES 512
100 #define MAX_PDE32PAE_ENTRIES 512
101 #define MAX_PDPE32PAE_ENTRIES 4
103 #define MAX_PTE64_ENTRIES 512
104 #define MAX_PDE64_ENTRIES 512
105 #define MAX_PDPE64_ENTRIES 512
106 #define MAX_PML4E64_ENTRIES 512
109 /* Converts an address into a page table index */
110 #define PDE32_INDEX(x) ((((uint_t)x) >> 22) & 0x3ff)
111 #define PTE32_INDEX(x) ((((uint_t)x) >> 12) & 0x3ff)
114 #define PDPE32PAE_INDEX(x) ((((uint_t)x) >> 30) & 0x3)
115 #define PDE32PAE_INDEX(x) ((((uint_t)x) >> 21) & 0x1ff)
116 #define PTE32PAE_INDEX(x) ((((uint_t)x) >> 12) & 0x1ff)
118 #define PML4E64_INDEX(x) ((((ullong_t)x) >> 39) & 0x1ff)
119 #define PDPE64_INDEX(x) ((((ullong_t)x) >> 30) & 0x1ff)
120 #define PDE64_INDEX(x) ((((ullong_t)x) >> 21) & 0x1ff)
121 #define PTE64_INDEX(x) ((((ullong_t)x) >> 12) & 0x1ff)
124 /* Gets the base address needed for a Page Table entry */
125 /* Deprecate these :*/
126 #define PD32_BASE_ADDR(x) (((uint_t)x) >> 12)
127 #define PT32_BASE_ADDR(x) (((uint_t)x) >> 12)
128 #define PD32_4MB_BASE_ADDR(x) (((uint_t)x) >> 22)
130 #define PML4E64_BASE_ADDR(x) (((ullong_t)x) >> 12)
131 #define PDPE64_BASE_ADDR(x) (((ullong_t)x) >> 12)
132 #define PDE64_BASE_ADDR(x) (((ullong_t)x) >> 12)
133 #define PTE64_BASE_ADDR(x) (((ullong_t)x) >> 12)
134 /* Accessor functions for the page table structures */
135 #define PDE32_T_ADDR(x) (((x).pt_base_addr) << 12)
136 #define PTE32_T_ADDR(x) (((x).page_base_addr) << 12)
137 #define PDE32_4MB_T_ADDR(x) (((x).page_base_addr) << 22)
139 /* Replace The above with these... */
140 #define PAGE_BASE_ADDR(x) (((uint_t)x) >> 12)
141 #define LARGE_PAGE_BASE_ADDR(x) (((uint_t)x) >> 22)
142 #define BASE_TO_PAGE_ADDR(x) (((uint_t)x) << 12)
143 #define LARGE_BASE_TO_PAGE_ADDR(x) (((uint_t)x) << 22)
147 #define PT32_PAGE_ADDR(x) (((uint_t)x) & 0xfffff000)
148 #define PT32_PAGE_OFFSET(x) (((uint_t)x) & 0xfff)
149 #define PT32_PAGE_POWER 12
151 #define PD32_4MB_PAGE_ADDR(x) (((uint_t)x) & 0xffc00000)
152 #define PD32_4MB_PAGE_OFFSET(x) (((uint_t)x) & 0x003fffff)
153 #define PAGE_SIZE_4MB (4096 * 1024)
155 /* The following should be phased out */
156 #define PAGE_OFFSET(x) ((((uint_t)x) & 0xfff))
157 #define PAGE_ALIGNED_ADDR(x) (((uint_t) (x)) >> 12)
158 #define PAGE_ADDR(x) (PAGE_ALIGNED_ADDR(x) << 12)
159 #define PAGE_POWER 12
160 #define PAGE_SIZE 4096
166 #define CR3_TO_PDE32(cr3) ((pde32_t *)V3_VAddr((void *)(((ulong_t)cr3) & 0xfffff000)))
167 #define CR3_TO_PDPTRE(cr3) (V3_VAddr((void *)(((ulong_t)cr3) & 0xffffffe0)))
168 #define CR3_TO_PML4E64(cr3) ((pml4e64_t *)V3_VAddr((void *)(((ullong_t)cr3) & 0x000ffffffffff000LL)))
175 /* Page Table Flag Values */
176 #define PT32_HOOK 0x1
177 #define PT32_GUEST_PT 0x2
182 /* PDE 32 bit PAGE STRUCTURES */
183 typedef enum {PDE32_ENTRY_NOT_PRESENT, PDE32_ENTRY_PTE32, PDE32_ENTRY_LARGE_PAGE} pde32_entry_type_t;
184 typedef enum {PT_ACCESS_OK, PT_ENTRY_NOT_PRESENT, PT_WRITE_ERROR, PT_USER_ERROR} pt_access_status_t;
186 typedef struct pde32 {
189 uint_t user_page : 1;
190 uint_t write_through : 1;
191 uint_t cache_disable : 1;
194 uint_t large_page : 1;
195 uint_t global_page : 1;
197 uint_t pt_base_addr : 20;
198 } __attribute__((packed)) pde32_t;
200 typedef struct pde32_4MB {
203 uint_t user_page : 1;
204 uint_t write_through : 1;
205 uint_t cache_disable : 1;
209 uint_t global_page : 1;
213 uint_t page_base_addr : 10;
215 } __attribute__((packed)) pde32_4MB_t;
217 typedef struct pte32 {
220 uint_t user_page : 1;
221 uint_t write_through : 1;
222 uint_t cache_disable : 1;
226 uint_t global_page : 1;
228 uint_t page_base_addr : 20;
229 } __attribute__((packed)) pte32_t;
232 /* 32 bit PAE PAGE STRUCTURES */
233 typedef struct pdpe32pae {
235 uint_t rsvd : 2; // MBZ
236 uint_t write_through : 1;
237 uint_t cache_disable : 1;
240 uint_t rsvd2 : 2; // MBZ
242 uint_t pd_base_addr : 24;
243 uint_t rsvd3 : 28; // MBZ
244 } __attribute__((packed)) pdpe32pae_t;
248 typedef struct pde32pae {
251 uint_t user_page : 1;
252 uint_t write_through : 1;
253 uint_t cache_disable : 1;
256 uint_t large_page : 1;
257 uint_t global_page : 1;
259 uint_t pt_base_addr : 24;
261 } __attribute__((packed)) pde32pae_t;
263 typedef struct pde32pae_4MB {
266 uint_t user_page : 1;
267 uint_t write_through : 1;
268 uint_t cache_disable : 1;
272 uint_t global_page : 1;
276 uint_t page_base_addr : 14;
279 } __attribute__((packed)) pde32pae_4MB_t;
281 typedef struct pte32pae {
284 uint_t user_page : 1;
285 uint_t write_through : 1;
286 uint_t cache_disable : 1;
290 uint_t global_page : 1;
292 uint_t page_base_addr : 24;
294 } __attribute__((packed)) pte32pae_t;
303 /* LONG MODE 64 bit PAGE STRUCTURES */
304 typedef struct pml4e64 {
307 uint_t user_page : 1;
308 uint_t write_through : 1;
309 uint_t cache_disable : 1;
314 ullong_t pdp_base_addr : 40;
315 uint_t available : 11;
316 uint_t no_execute : 1;
317 } __attribute__((packed)) pml4e64_t;
320 typedef struct pdpe64 {
323 uint_t user_page : 1;
324 uint_t write_through : 1;
325 uint_t cache_disable : 1;
328 uint_t large_page : 1;
331 ullong_t pd_base_addr : 40;
332 uint_t available : 11;
333 uint_t no_execute : 1;
334 } __attribute__((packed)) pdpe64_t;
339 typedef struct pde64 {
342 uint_t user_page : 1;
343 uint_t write_through : 1;
344 uint_t cache_disable : 1;
347 uint_t large_page : 1;
348 uint_t reserved2 : 1;
350 ullong_t pt_base_addr : 40;
351 uint_t available : 11;
352 uint_t no_execute : 1;
353 } __attribute__((packed)) pde64_t;
355 typedef struct pte64 {
358 uint_t user_page : 1;
359 uint_t write_through : 1;
360 uint_t cache_disable : 1;
364 uint_t global_page : 1;
366 ullong_t page_base_addr : 40;
367 uint_t available : 11;
368 uint_t no_execute : 1;
369 } __attribute__((packed)) pte64_t;
371 /* *************** */
373 typedef struct pf_error_code {
374 uint_t present : 1; // if 0, fault due to page not present
375 uint_t write : 1; // if 1, faulting access was a write
376 uint_t user : 1; // if 1, faulting access was in user mode
377 uint_t rsvd_access : 1; // if 1, fault from reading a 1 from a reserved field (?)
378 uint_t ifetch : 1; // if 1, faulting access was an instr fetch (only with NX)
380 } __attribute__((packed)) pf_error_t;
385 void delete_page_tables_32(pde32_t * pde);
386 void delete_page_tables_32PAE(pdpe32pae_t * pdpe);
387 void delete_page_tables_64(pml4e64_t * pml4);
389 pde32_entry_type_t pde32_lookup(pde32_t * pd, addr_t addr, addr_t * entry);
390 int pte32_lookup(pte32_t * pte, addr_t addr, addr_t * entry);
392 // This assumes that the page table resides in the host address space
393 // IE. IT DOES NO VM ADDR TRANSLATION
394 int pt32_lookup(pde32_t * pd, addr_t vaddr, addr_t * paddr);
398 pt_access_status_t can_access_pde32(pde32_t * pde, addr_t addr, pf_error_t access_type);
399 pt_access_status_t can_access_pte32(pte32_t * pte, addr_t addr, pf_error_t access_type);
407 pde32_t * create_passthrough_pts_32(struct guest_info * guest_info);
408 pdpe32pae_t * create_passthrough_pts_32PAE(struct guest_info * guest_info);
409 pml4e64_t * create_passthrough_pts_64(struct guest_info * info);
414 //#include <palacios/vm_guest.h>
416 void PrintDebugPageTables(pde32_t * pde);
419 void PrintPageTree(v3_vm_cpu_mode_t cpu_mode, addr_t virtual_addr, addr_t cr3);
420 void PrintPageTree_64(addr_t virtual_addr, pml4e64_t * pml);
423 void PrintPT32(addr_t starting_address, pte32_t * pte);
424 void PrintPD32(pde32_t * pde);
425 void PrintPTE32(addr_t virtual_address, pte32_t * pte);
426 void PrintPDE32(addr_t virtual_address, pde32_t * pde);
428 void PrintDebugPageTables32PAE(pdpe32pae_t * pde);
429 void PrintPTE32PAE(addr_t virtual_address, pte32pae_t * pte);
430 void PrintPDE32PAE(addr_t virtual_address, pde32pae_t * pde);
431 void PrintPTE64(addr_t virtual_address, pte64_t * pte);