1 /* (c) 2008, Jack Lange <jarusl@cs.northwestern.edu> */
2 /* (c) 2008, The V3VEE Project <http://www.v3vee.org> */
10 #include <palacios/vmm_types.h>
11 #include <palacios/vmm_util.h>
15 In the following, when we say "page table", we mean the whole 2 or 4 layer
16 page table (PDEs, PTEs), etc.
19 guest-visible paging state
20 This is the state that the guest thinks the machine is using
22 - guest physical memory
23 The physical memory addresses the guest is allowed to use
24 (see shadow page maps, below)
26 (we care about when the current one changes)
27 - guest paging registers (these are never written to hardware)
33 This the state that the machine will actually use when the guest
34 is running. It consists of:
35 - current shadow page table
36 This is the page table actually useed when the guest is running.
37 It is changed/regenerated when the guest page table changes
38 It mostly reflects the guest page table, except that it restricts
39 physical addresses to those the VMM allocates to the guest.
41 This is a mapping from guest physical memory addresses to
42 the current location of the guest physical memory content.
43 It maps from regions of physical memory addresses to regions
44 located in physical memory or elsewhere.
45 (8192,16384) -> MEM(8912,...)
46 (0,8191) -> DISK(65536,..)
47 - guest paging registers (these are written to guest state)
52 This is the state we expect to be operative when the VMM is running.
53 Typically, this is set up by the host os into which we have embedded
54 the VMM, but we include the description here for clarity.
56 This is the page table we use when we are executing in
57 the VMM (or the host os)
63 The reason why the shadow paging state and the host paging state are
64 distinct is to permit the guest to use any virtual address it wants,
65 irrespective of the addresses the VMM or the host os use. These guest
66 virtual addresses are reflected in the shadow paging state. When we
67 exit from the guest, we switch to the host paging state so that any
68 virtual addresses that overlap between the guest and VMM/host now map
69 to the physical addresses epxected by the VMM/host. On AMD SVM, this
70 switch is done by the hardware. On Intel VT, the switch is done
71 by the hardware as well, but we are responsible for manually updating
72 the host state in the vmcs before entering the guest.
78 #define MAX_PTE32_ENTRIES 1024
79 #define MAX_PDE32_ENTRIES 1024
81 #define MAX_PTE64_ENTRIES 512
82 #define MAX_PDE64_ENTRIES 512
83 #define MAX_PDPE64_ENTRIES 512
84 #define MAX_PML4E64_ENTRIES 512
87 /* Converts an address into a page table index */
88 #define PDE32_INDEX(x) ((((uint_t)x) >> 22) & 0x3ff)
89 #define PTE32_INDEX(x) ((((uint_t)x) >> 12) & 0x3ff)
91 /* Gets the base address needed for a Page Table entry */
92 #define PD32_BASE_ADDR(x) (((uint_t)x) >> 12)
93 #define PT32_BASE_ADDR(x) (((uint_t)x) >> 12)
94 #define PD32_4MB_BASE_ADDR(x) (((uint_t)x) >> 22)
96 #define PT32_PAGE_ADDR(x) (((uint_t)x) & 0xfffff000)
97 #define PT32_PAGE_OFFSET(x) (((uint_t)x) & 0xfff)
98 #define PT32_PAGE_POWER 12
100 #define PD32_4MB_PAGE_ADDR(x) (((uint_t)x) & 0xffc00000)
101 #define PD32_4MB_PAGE_OFFSET(x) (((uint_t)x) & 0x003fffff)
102 #define PAGE_SIZE_4MB (4096 * 1024)
104 /* The following should be phased out */
105 #define PAGE_OFFSET(x) ((((uint_t)x) & 0xfff))
106 #define PAGE_ALIGNED_ADDR(x) (((uint_t) (x)) >> 12)
107 #define PAGE_ADDR(x) (PAGE_ALIGNED_ADDR(x) << 12)
108 #define PAGE_POWER 12
109 #define PAGE_SIZE 4096
115 #define CR3_TO_PDE32(cr3) (((ulong_t)cr3) & 0xfffff000)
116 #define CR3_TO_PDPTRE(cr3) (((ulong_t)cr3) & 0xffffffe0)
117 #define CR3_TO_PML4E64(cr3) (((ullong_t)cr3) & 0x000ffffffffff000LL)
122 /* Accessor functions for the page table structures */
123 #define PDE32_T_ADDR(x) (((x).pt_base_addr) << 12)
124 #define PTE32_T_ADDR(x) (((x).page_base_addr) << 12)
125 #define PDE32_4MB_T_ADDR(x) (((x).page_base_addr) << 22)
127 /* Page Table Flag Values */
128 #define PT32_HOOK 0x1
129 #define PT32_GUEST_PT 0x2
134 /* PDE 32 bit PAGE STRUCTURES */
135 typedef enum {PDE32_ENTRY_NOT_PRESENT, PDE32_ENTRY_PTE32, PDE32_ENTRY_LARGE_PAGE} pde32_entry_type_t;
136 typedef enum {PT_ACCESS_OK, PT_ENTRY_NOT_PRESENT, PT_WRITE_ERROR, PT_USER_ERROR} pt_access_status_t;
138 typedef struct pde32 {
141 uint_t user_page : 1;
142 uint_t write_through : 1;
143 uint_t cache_disable : 1;
146 uint_t large_page : 1;
147 uint_t global_page : 1;
149 uint_t pt_base_addr : 20;
152 typedef struct pde32_4MB {
155 uint_t user_page : 1;
156 uint_t write_through : 1;
157 uint_t cache_disable : 1;
161 uint_t global_page : 1;
165 uint_t page_base_addr : 10;
169 typedef struct pte32 {
172 uint_t user_page : 1;
173 uint_t write_through : 1;
174 uint_t cache_disable : 1;
178 uint_t global_page : 1;
180 uint_t page_base_addr : 20;
184 /* 32 bit PAE PAGE STRUCTURES */
193 /* LONG MODE 64 bit PAGE STRUCTURES */
194 typedef struct pml4e64 {
204 uint_t pdp_base_addr_lo : 20;
205 uint_t pdp_base_addr_hi : 20;
206 uint_t available : 11;
207 uint_t no_execute : 1;
211 typedef struct pdpe64 {
219 uint_t large_pages : 1;
222 uint_t pd_base_addr_lo : 20;
223 uint_t pd_base_addr_hi : 20;
224 uint_t available : 11;
225 uint_t no_execute : 1;
231 typedef struct pde64 {
236 uint_t large_pages : 1;
237 uint_t reserved2 : 1;
239 uint_t pt_base_addr_lo : 20;
240 uint_t pt_base_addr_hi : 20;
241 uint_t available : 11;
242 uint_t no_execute : 1;
245 typedef struct pte64 {
251 uint_t global_page : 1;
253 uint_t page_base_addr_lo : 20;
254 uint_t page_base_addr_hi : 20;
255 uint_t available : 11;
256 uint_t no_execute : 1;
259 /* *************** */
261 typedef struct pf_error_code {
262 uint_t present : 1; // if 0, fault due to page not present
263 uint_t write : 1; // if 1, faulting access was a write
264 uint_t user : 1; // if 1, faulting access was in user mode
265 uint_t rsvd_access : 1; // if 1, fault from reading a 1 from a reserved field (?)
266 uint_t ifetch : 1; // if 1, faulting access was an instr fetch (only with NX)
270 typedef enum { PDE32 } paging_mode_t;
275 void delete_page_tables_pde32(pde32_t * pde);
278 pde32_entry_type_t pde32_lookup(pde32_t * pd, addr_t addr, addr_t * entry);
279 int pte32_lookup(pte32_t * pte, addr_t addr, addr_t * entry);
281 // This assumes that the page table resides in the host address space
282 // IE. IT DOES NO VM ADDR TRANSLATION
283 int pt32_lookup(pde32_t * pd, addr_t vaddr, addr_t * paddr);
287 pt_access_status_t can_access_pde32(pde32_t * pde, addr_t addr, pf_error_t access_type);
288 pt_access_status_t can_access_pte32(pte32_t * pte, addr_t addr, pf_error_t access_type);
296 pde32_t * create_passthrough_pde32_pts(struct guest_info * guest_info);
303 void PrintDebugPageTables(pde32_t * pde);
309 void PrintPT32(addr_t starting_address, pte32_t * pte);
310 void PrintPD32(pde32_t * pde);
311 void PrintPTE32(addr_t virtual_address, pte32_t * pte);
312 void PrintPDE32(addr_t virtual_address, pde32_t * pde);