2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2008, Peter Dinda <pdinda@northwestern.edu>
11 * Copyright (c) 2008, Jack Lange <jarusl@cs.northwestern.edu>
12 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Peter Dinda <pdinda@northwestern.edu>
16 * Jack Lange <jarusl@cs.northwestern.edu>
18 * This is free software. You are permitted to use,
19 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
29 #include <palacios/vmm_types.h>
30 /* Pin Based VM Execution Controls */
31 /* INTEL MANUAL: 20-10 vol 3B */
32 #define EXT_INTR_EXIT 0x00000001
33 #define NMI_EXIT 0x00000008
34 #define VIRTUAL_NMIS 0x00000020
35 /* Processor Based VM Execution Controls */
36 /* INTEL MANUAL: 20-11 vol. 3B */
37 #define INTR_WIN_EXIT 0x00000004
38 #define USE_TSC_OFFSET 0x00000008
39 #define HLT_EXIT 0x00000080
40 #define INVLPG_EXIT 0x00000200
41 #define MWAIT_EXIT 0x00000400
42 #define RDPMC_EXIT 0x00000800
43 #define RDTSC_EXIT 0x00001000
44 #define CR3_LOAD_EXIT 0x00008000
45 #define CR3_STORE_EXIT 0x00010000
46 #define CR8_LOAD_EXIT 0x00080000
47 #define CR8_STORE_EXIT 0x00100000
48 #define USE_TPR_SHADOW 0x00200000
49 #define NMI_WINDOW_EXIT 0x00400000
50 #define MOVDR_EXIT 0x00800000
51 #define UNCOND_IO_EXIT 0x01000000
52 #define USE_IO_BITMAPS 0x02000000
53 #define USE_MSR_BITMAPS 0x10000000
54 #define MONITOR_EXIT 0x20000000
55 #define PAUSE_EXIT 0x40000000
56 #define ACTIVE_SEC_CTRLS 0x80000000
57 /* VM-Exit Controls */
58 /* INTEL MANUAL: 20-16 vol. 3B */
59 #define HOST_ADDR_SPACE_SIZE 0x00000200
60 #define ACK_IRQ_ON_EXIT 0x00008000
62 /* Control register exit masks */
63 #define CR0_PE 0x00000001
64 #define CR0_PG 0x80000000
65 #define CR4_VMXE 0x00002000
68 VMCS_GUEST_ES_SELECTOR = 0x00000800,
69 VMCS_GUEST_CS_SELECTOR = 0x00000802,
70 VMCS_GUEST_SS_SELECTOR = 0x00000804,
71 VMCS_GUEST_DS_SELECTOR = 0x00000806,
72 VMCS_GUEST_FS_SELECTOR = 0x00000808,
73 VMCS_GUEST_GS_SELECTOR = 0x0000080A,
74 VMCS_GUEST_LDTR_SELECTOR = 0x0000080C,
75 VMCS_GUEST_TR_SELECTOR = 0x0000080E,
76 /* 16 bit host state */
77 VMCS_HOST_ES_SELECTOR = 0x00000C00,
78 VMCS_HOST_CS_SELECTOR = 0x00000C02,
79 VMCS_HOST_SS_SELECTOR = 0x00000C04,
80 VMCS_HOST_DS_SELECTOR = 0x00000C06,
81 VMCS_HOST_FS_SELECTOR = 0x00000C08,
82 VMCS_HOST_GS_SELECTOR = 0x00000C0A,
83 VMCS_HOST_TR_SELECTOR = 0x00000C0C,
84 /* 64 bit control fields */
85 VMCS_IO_BITMAP_A_ADDR = 0x00002000,
86 VMCS_IO_BITMAP_A_ADDR_HIGH = 0x00002001,
87 VMCS_IO_BITMAP_B_ADDR = 0x00002002,
88 VMCS_IO_BITMAP_B_ADDR_HIGH = 0x00002003,
89 VMCS_MSR_BITMAP = 0x00002004,
90 VMCS_MSR_BITMAP_HIGH = 0x00002005,
91 VMCS_EXIT_MSR_STORE_ADDR = 0x00002006,
92 VMCS_EXIT_MSR_STORE_ADDR_HIGH = 0x00002007,
93 VMCS_EXIT_MSR_LOAD_ADDR = 0x00002008,
94 VMCS_EXIT_MSR_LOAD_ADDR_HIGH = 0x00002009,
95 VMCS_ENTRY_MSR_LOAD_ADDR = 0x0000200A,
96 VMCS_ENTRY_MSR_LOAD_ADDR_HIGH = 0x0000200B,
97 VMCS_EXEC_PTR = 0x0000200C,
98 VMCS_EXEC_PTR_HIGH = 0x0000200D,
99 VMCS_TSC_OFFSET = 0x00002010,
100 VMCS_TSC_OFFSET_HIGH = 0x00002011,
101 VMCS_VAPIC_ADDR = 0x00002012,
102 VMCS_VAPIC_ADDR_HIGH = 0x00002013,
103 VMCS_APIC_ACCESS_ADDR = 0x00002014,
104 VMCS_APIC_ACCESS_ADDR_HIGH = 0x00002015,
105 /* 64 bit guest state fields */
106 VMCS_LINK_PTR = 0x00002800,
107 VMCS_LINK_PTR_HIGH = 0x00002801,
108 VMCS_GUEST_DBG_CTL = 0x00002802,
109 VMCS_GUEST_DBG_CTL_HIGH = 0x00002803,
110 VMCS_GUEST_PERF_GLOBAL_CTRL = 0x00002808,
111 VMCS_GUEST_PERF_GLOBAL_CTRL_HIGH = 0x00002809,
113 VMCS_HOST_PERF_GLOBAL_CTRL = 0x00002c04,
114 VMCS_HOST_PERF_GLOBAL_CTRL_HIGH = 0x00002c05,
115 /* 32 bit control fields */
116 VMCS_PIN_CTRLS = 0x00004000,
117 VMCS_PROC_CTRLS = 0x00004002,
118 VMCS_EXCP_BITMAP = 0x00004004,
119 VMCS_PG_FAULT_ERR_MASK = 0x00004006,
120 VMCS_PG_FAULT_ERR_MATCH = 0x00004008,
121 VMCS_CR3_TGT_CNT = 0x0000400A,
122 VMCS_EXIT_CTRLS = 0x0000400C,
123 VMCS_EXIT_MSR_STORE_CNT = 0x0000400E,
124 VMCS_EXIT_MSR_LOAD_CNT = 0x00004010,
125 VMCS_ENTRY_CTRLS = 0x00004012,
126 VMCS_ENTRY_MSR_LOAD_CNT = 0x00004014,
127 VMCS_ENTRY_INT_INFO = 0x00004016,
128 VMCS_ENTRY_EXCP_ERR = 0x00004018,
129 VMCS_ENTRY_INSTR_LEN = 0x0000401A,
130 VMCS_TPR_THRESHOLD = 0x0000401C,
131 VMCS_SEC_PROC_CTRLS = 0x0000401e,
132 /* 32 bit Read Only data fields */
133 VMCS_INSTR_ERR = 0x00004400,
134 VMCS_EXIT_REASON = 0x00004402,
135 VMCS_EXIT_INT_INFO = 0x00004404,
136 VMCS_EXIT_INT_ERR = 0x00004406,
137 VMCS_IDT_VECTOR_INFO = 0x00004408,
138 VMCS_IDT_VECTOR_ERR = 0x0000440A,
139 VMCS_EXIT_INSTR_LEN = 0x0000440C,
140 VMCS_VMX_INSTR_INFO = 0x0000440E,
141 /* 32 bit Guest state fields */
142 VMCS_GUEST_ES_LIMIT = 0x00004800,
143 VMCS_GUEST_CS_LIMIT = 0x00004802,
144 VMCS_GUEST_SS_LIMIT = 0x00004804,
145 VMCS_GUEST_DS_LIMIT = 0x00004806,
146 VMCS_GUEST_FS_LIMIT = 0x00004808,
147 VMCS_GUEST_GS_LIMIT = 0x0000480A,
148 VMCS_GUEST_LDTR_LIMIT = 0x0000480C,
149 VMCS_GUEST_TR_LIMIT = 0x0000480E,
150 VMCS_GUEST_GDTR_LIMIT = 0x00004810,
151 VMCS_GUEST_IDTR_LIMIT = 0x00004812,
152 VMCS_GUEST_ES_ACCESS = 0x00004814,
153 VMCS_GUEST_CS_ACCESS = 0x00004816,
154 VMCS_GUEST_SS_ACCESS = 0x00004818,
155 VMCS_GUEST_DS_ACCESS = 0x0000481A,
156 VMCS_GUEST_FS_ACCESS = 0x0000481C,
157 VMCS_GUEST_GS_ACCESS = 0x0000481E,
158 VMCS_GUEST_LDTR_ACCESS = 0x00004820,
159 VMCS_GUEST_TR_ACCESS = 0x00004822,
160 VMCS_GUEST_INT_STATE = 0x00004824,
161 VMCS_GUEST_ACTIVITY_STATE = 0x00004826,
162 VMCS_GUEST_SMBASE = 0x00004828,
163 VMCS_GUEST_SYSENTER_CS = 0x0000482A,
164 /* 32 bit host state field */
165 VMCS_HOST_SYSENTER_CS = 0x00004C00,
166 /* Natural Width Control Fields */
167 VMCS_CR0_MASK = 0x00006000,
168 VMCS_CR4_MASK = 0x00006002,
169 VMCS_CR0_READ_SHDW = 0x00006004,
170 VMCS_CR4_READ_SHDW = 0x00006006,
171 VMCS_CR3_TGT_VAL_0 = 0x00006008,
172 VMCS_CR3_TGT_VAL_1 = 0x0000600A,
173 VMCS_CR3_TGT_VAL_2 = 0x0000600C,
174 VMCS_CR3_TGT_VAL_3 = 0x0000600E,
175 /* Natural Width Read Only Fields */
176 VMCS_EXIT_QUAL = 0x00006400,
177 VMCS_IO_RCX = 0x00006402,
178 VMCS_IO_RSI = 0x00006404,
179 VMCS_IO_RDI = 0x00006406,
180 VMCS_IO_RIP = 0x00006408,
181 VMCS_GUEST_LINEAR_ADDR = 0x0000640A,
182 /* Natural Width Guest State Fields */
183 VMCS_GUEST_CR0 = 0x00006800,
184 VMCS_GUEST_CR3 = 0x00006802,
185 VMCS_GUEST_CR4 = 0x00006804,
186 VMCS_GUEST_ES_BASE = 0x00006806,
187 VMCS_GUEST_CS_BASE = 0x00006808,
188 VMCS_GUEST_SS_BASE = 0x0000680A,
189 VMCS_GUEST_DS_BASE = 0x0000680C,
190 VMCS_GUEST_FS_BASE = 0x0000680E,
191 VMCS_GUEST_GS_BASE = 0x00006810,
192 VMCS_GUEST_LDTR_BASE = 0x00006812,
193 VMCS_GUEST_TR_BASE = 0x00006814,
194 VMCS_GUEST_GDTR_BASE = 0x00006816,
195 VMCS_GUEST_IDTR_BASE = 0x00006818,
196 VMCS_GUEST_DR7 = 0x0000681A,
197 VMCS_GUEST_RSP = 0x0000681C,
198 VMCS_GUEST_RIP = 0x0000681E,
199 VMCS_GUEST_RFLAGS = 0x00006820,
200 VMCS_GUEST_PENDING_DBG_EXCP = 0x00006822,
201 VMCS_GUEST_SYSENTER_ESP = 0x00006824,
202 VMCS_GUEST_SYSENTER_EIP = 0x00006826,
203 /* Natural Width Host State Fields */
204 VMCS_HOST_CR0 = 0x00006C00,
205 VMCS_HOST_CR3 = 0x00006C02,
206 VMCS_HOST_CR4 = 0x00006C04,
207 VMCS_HOST_FS_BASE = 0x00006C06,
208 VMCS_HOST_GS_BASE = 0x00006C08,
209 VMCS_HOST_TR_BASE = 0x00006C0A,
210 VMCS_HOST_GDTR_BASE = 0x00006C0C,
211 VMCS_HOST_IDTR_BASE = 0x00006C0E,
212 VMCS_HOST_SYSENTER_ESP = 0x00006C10,
213 VMCS_HOST_SYSENTER_EIP = 0x00006C12,
214 VMCS_HOST_RSP = 0x00006C14,
215 VMCS_HOST_RIP = 0x00006C16,
218 int v3_vmcs_get_field_len(vmcs_field_t field);
219 const char* v3_vmcs_field_to_str(vmcs_field_t field);
220 void v3_print_vmcs();
224 /* Exit Vector Info */
225 struct VMExitIntInfo {
226 uint32_t nr : 8; // IRQ number, exception vector, NMI = 2
227 uint32_t type : 3; // (0: ext. IRQ , 2: NMI , 3: hw exception , 6: sw exception
228 uint32_t errorCode : 1; // 1: error Code present
229 uint32_t iret : 1; // something to do with NMIs and IRETs (Intel 3B, sec. 23.2.2)
230 uint32_t rsvd : 18; // always 0
231 uint32_t valid : 1; // always 1 if valid
232 } __attribute__((packed));
237 /* End Exit Vector Info */
239 struct vmx_exception_bitmap {
243 uint_t de : 1; // (0) divide by zero
244 uint_t db : 1; // (1) Debug
245 uint_t nmi : 1; // (2) Non-maskable interrupt
246 uint_t bp : 1; // (3) Breakpoint
247 uint_t of : 1; // (4) Overflow
248 uint_t br : 1; // (5) Bound-Range
249 uint_t ud : 1; // (6) Invalid-Opcode
250 uint_t nm : 1; // (7) Device-not-available
251 uint_t df : 1; // (8) Double Fault
253 uint_t ts : 1; // (10) Invalid TSS
254 uint_t np : 1; // (11) Segment-not-present
255 uint_t ss : 1; // (12) Stack
256 uint_t gp : 1; // (13) General Protection Fault
257 uint_t pf : 1; // (14) Page fault
259 uint_t mf : 1; // (15) Floating point exception
260 uint_t ac : 1; // (16) Alignment-check
261 uint_t mc : 1; // (17) Machine Check
262 uint_t xf : 1; // (18) SIMD floating-point
273 uint_t sx : 1; // (30) Security Exception
275 } __attribute__ ((packed));
276 } __attribute__ ((packed));
277 } __attribute__((packed));
282 /* Segment Selector Access Rights (32 bits) */
283 /* INTEL Manual: 20-4 vol 3B */
286 struct vmcs_segment_access {
291 uint32_t desc_type : 1;
293 uint32_t present : 1;
296 uint32_t long_mode : 1; // CS only (64 bit active), reserved otherwise
298 uint32_t granularity : 1;
299 uint32_t unusable : 1;
301 } __attribute__((packed));
302 } __attribute__((packed));
303 }__attribute__((packed));
306 struct vmcs_interrupt_state {
307 uint32_t sti_blocking : 1;
308 uint32_t mov_ss_blocking : 1;
309 uint32_t smi_blocking : 1;
310 uint32_t nmi_blocking : 1;
312 } __attribute__((packed));
319 } __attribute__((packed));
322 //uint_t VMCSRead(uint_t tag, void * val);
325 #endif // ! __V3VEE__