1 /* (c) 2008, Peter Dinda <pdinda@northwestern.edu> */
2 /* (c) 2008, Jack Lange <jarusl@cs.northwestern.edu> */
3 /* (c) 2008, The V3VEE Project <http://www.v3vee.org> */
12 #include <palacios/vmm_types.h>
15 /* 16 bit guest state */
16 #define VMCS_GUEST_ES_SELECTOR 0x00000800
17 #define VMCS_GUEST_CS_SELECTOR 0x00000802
18 #define VMCS_GUEST_SS_SELECTOR 0x00000804
19 #define VMCS_GUEST_DS_SELECTOR 0x00000806
20 #define VMCS_GUEST_FS_SELECTOR 0x00000808
21 #define VMCS_GUEST_GS_SELECTOR 0x0000080A
22 #define VMCS_GUEST_LDTR_SELECTOR 0x0000080C
23 #define VMCS_GUEST_TR_SELECTOR 0x0000080E
25 /* 16 bit host state */
26 #define VMCS_HOST_ES_SELECTOR 0x00000C00
27 #define VMCS_HOST_CS_SELECTOR 0x00000C02
28 #define VMCS_HOST_SS_SELECTOR 0x00000C04
29 #define VMCS_HOST_DS_SELECTOR 0x00000C06
30 #define VMCS_HOST_FS_SELECTOR 0x00000C08
31 #define VMCS_HOST_GS_SELECTOR 0x00000C0A
32 #define VMCS_HOST_TR_SELECTOR 0x00000C0C
34 /* 64 bit control fields */
35 #define IO_BITMAP_A_ADDR 0x00002000
36 #define IO_BITMAP_A_ADDR_HIGH 0x00002001
37 #define IO_BITMAP_B_ADDR 0x00002002
38 #define IO_BITMAP_B_ADDR_HIGH 0x00002003
39 // Only with "Use MSR Bitmaps" enabled
40 #define MSR_BITMAPS 0x00002004
41 #define MSR_BITMAPS_HIGH 0x00002005
43 #define VM_EXIT_MSR_STORE_ADDR 0x00002006
44 #define VM_EXIT_MSR_STORE_ADDR_HIGH 0x00002007
45 #define VM_EXIT_MSR_LOAD_ADDR 0x00002008
46 #define VM_EXIT_MSR_LOAD_ADDR_HIGH 0x00002009
47 #define VM_ENTRY_MSR_LOAD_ADDR 0x0000200A
48 #define VM_ENTRY_MSR_LOAD_ADDR_HIGH 0x0000200B
49 #define VMCS_EXEC_PTR 0x0000200C
50 #define VMCS_EXEC_PTR_HIGH 0x0000200D
51 #define TSC_OFFSET 0x00002010
52 #define TSC_OFFSET_HIGH 0x00002011
53 // Only with "Use TPR Shadow" enabled
54 #define VIRT_APIC_PAGE_ADDR 0x00002012
55 #define VIRT_APIC_PAGE_ADDR_HIGH 0x00002013
59 /* 64 bit guest state fields */
60 #define VMCS_LINK_PTR 0x00002800
61 #define VMCS_LINK_PTR_HIGH 0x00002801
62 #define GUEST_IA32_DEBUGCTL 0x00002802
63 #define GUEST_IA32_DEBUGCTL_HIGH 0x00002803
66 /* 32 bit control fields */
67 #define PIN_VM_EXEC_CTRLS 0x00004000
68 #define PROC_VM_EXEC_CTRLS 0x00004002
69 #define EXCEPTION_BITMAP 0x00004004
70 #define PAGE_FAULT_ERROR_MASK 0x00004006
71 #define PAGE_FAULT_ERROR_MATCH 0x00004008
72 #define CR3_TARGET_COUNT 0x0000400A
73 #define VM_EXIT_CTRLS 0x0000400C
74 #define VM_EXIT_MSR_STORE_COUNT 0x0000400E
75 #define VM_EXIT_MSR_LOAD_COUNT 0x00004010
76 #define VM_ENTRY_CTRLS 0x00004012
77 #define VM_ENTRY_MSR_LOAD_COUNT 0x00004014
78 #define VM_ENTRY_INT_INFO_FIELD 0x00004016
79 #define VM_ENTRY_EXCEPTION_ERROR 0x00004018
80 #define VM_ENTRY_INSTR_LENGTH 0x0000401A
81 // Only with "Use TPR Shadow" Enabled
82 #define TPR_THRESHOLD 0x0000401C
86 /* 32 bit Read Only data fields */
87 #define VM_INSTR_ERROR 0x00004400
88 #define EXIT_REASON 0x00004402
89 #define VM_EXIT_INT_INFO 0x00004404
90 #define VM_EXIT_INT_ERROR 0x00004406
91 #define IDT_VECTOR_INFO 0x00004408
92 #define IDT_VECTOR_ERROR 0x0000440A
93 #define VM_EXIT_INSTR_LENGTH 0x0000440C
94 #define VMX_INSTR_INFO 0x0000440E
96 /* 32 bit Guest state fields */
97 #define GUEST_ES_LIMIT 0x00004800
98 #define GUEST_CS_LIMIT 0x00004802
99 #define GUEST_SS_LIMIT 0x00004804
100 #define GUEST_DS_LIMIT 0x00004806
101 #define GUEST_FS_LIMIT 0x00004808
102 #define GUEST_GS_LIMIT 0x0000480A
103 #define GUEST_LDTR_LIMIT 0x0000480C
104 #define GUEST_TR_LIMIT 0x0000480E
105 #define GUEST_GDTR_LIMIT 0x00004810
106 #define GUEST_IDTR_LIMIT 0x00004812
107 #define GUEST_ES_ACCESS 0x00004814
108 #define GUEST_CS_ACCESS 0x00004816
109 #define GUEST_SS_ACCESS 0x00004818
110 #define GUEST_DS_ACCESS 0x0000481A
111 #define GUEST_FS_ACCESS 0x0000481C
112 #define GUEST_GS_ACCESS 0x0000481E
113 #define GUEST_LDTR_ACCESS 0x00004820
114 #define GUEST_TR_ACCESS 0x00004822
115 #define GUEST_INT_STATE 0x00004824
116 #define GUEST_ACTIVITY_STATE 0x00004826
117 #define GUEST_SMBASE 0x00004828
118 #define GUEST_IA32_SYSENTER_CS 0x0000482A
121 /* 32 bit host state field */
122 #define HOST_IA32_SYSENTER_CS 0x00004C00
124 /* Natural Width Control Fields */
125 #define CR0_GUEST_HOST_MASK 0x00006000
126 #define CR4_GUEST_HOST_MASK 0x00006002
127 #define CR0_READ_SHADOW 0x00006004
128 #define CR4_READ_SHADOW 0x00006006
129 #define CR3_TARGET_VALUE_0 0x00006008
130 #define CR3_TARGET_VALUE_1 0x0000600A
131 #define CR3_TARGET_VALUE_2 0x0000600C
132 #define CR3_TARGET_VALUE_3 0x0000600E
135 /* Natural Width Read Only Fields */
136 #define EXIT_QUALIFICATION 0x00006400
137 #define IO_RCX 0x00006402
138 #define IO_RSI 0x00006404
139 #define IO_RDI 0x00006406
140 #define IO_RIP 0x00006408
141 #define GUEST_LINEAR_ADDR 0x0000640A
143 /* Natural Width Guest State Fields */
144 #define GUEST_CR0 0x00006800
145 #define GUEST_CR3 0x00006802
146 #define GUEST_CR4 0x00006804
147 #define GUEST_ES_BASE 0x00006806
148 #define GUEST_CS_BASE 0x00006808
149 #define GUEST_SS_BASE 0x0000680A
150 #define GUEST_DS_BASE 0x0000680C
151 #define GUEST_FS_BASE 0x0000680E
152 #define GUEST_GS_BASE 0x00006810
153 #define GUEST_LDTR_BASE 0x00006812
154 #define GUEST_TR_BASE 0x00006814
155 #define GUEST_GDTR_BASE 0x00006816
156 #define GUEST_IDTR_BASE 0x00006818
157 #define GUEST_DR7 0x0000681A
158 #define GUEST_RSP 0x0000681C
159 #define GUEST_RIP 0x0000681E
160 #define GUEST_RFLAGS 0x00006820
161 #define GUEST_PENDING_DEBUG_EXCS 0x00006822
162 #define GUEST_IA32_SYSENTER_ESP 0x00006824
163 #define GUEST_IA32_SYSENTER_EIP 0x00006826
166 /* Natural Width Host State Fields */
167 #define HOST_CR0 0x00006C00
168 #define HOST_CR3 0x00006C02
169 #define HOST_CR4 0x00006C04
170 #define HOST_FS_BASE 0x00006C06
171 #define HOST_GS_BASE 0x00006C08
172 #define HOST_TR_BASE 0x00006C0A
173 #define HOST_GDTR_BASE 0x00006C0C
174 #define HOST_IDTR_BASE 0x00006C0E
175 #define HOST_IA32_SYSENTER_ESP 0x00006C10
176 #define HOST_IA32_SYSENTER_EIP 0x00006C12
177 #define HOST_RSP 0x00006C14
178 #define HOST_RIP 0x00006C16
180 /* Pin Based VM Execution Controls */
181 /* INTEL MANUAL: 20-10 vol 3B */
182 #define EXTERNAL_INTERRUPT_EXITING 0x00000001
183 #define NMI_EXITING 0x00000008
184 #define VIRTUAL_NMIS 0x00000020
187 /* Processor Based VM Execution Controls */
188 /* INTEL MANUAL: 20-11 vol. 3B */
189 #define INTERRUPT_WINDOWS_EXIT 0x00000004
190 #define USE_TSC_OFFSETTING 0x00000008
191 #define HLT_EXITING 0x00000080
192 #define INVLPG_EXITING 0x00000200
193 #define MWAIT_EXITING 0x00000400
194 #define RDPMC_EXITING 0x00000800
195 #define RDTSC_EXITING 0x00001000
196 #define CR8_LOAD_EXITING 0x00080000
197 #define CR8_STORE_EXITING 0x00100000
198 #define USE_TPR_SHADOW 0x00200000
199 #define NMI_WINDOW_EXITING 0x00400000
200 #define MOVDR_EXITING 0x00800000
201 #define UNCONDITION_IO_EXITING 0x01000000
202 #define USE_IO_BITMAPS 0x02000000
203 #define USE_MSR_BITMAPS 0x10000000
204 #define MONITOR_EXITING 0x20000000
205 #define PAUSE_EXITING 0x40000000
207 /* VM-Exit Controls */
208 /* INTEL MANUAL: 20-16 vol. 3B */
209 #define HOST_ADDR_SPACE_SIZE 0x00000200
210 #define ACK_IRQ_ON_EXIT 0x00008000
213 #define VM_EXIT_REASON_INFO_EXCEPTION_OR_NMI 0
214 #define VM_EXIT_REASON_EXTERNAL_INTR 1
215 #define VM_EXIT_REASON_TRIPLE_FAULT 2
216 #define VM_EXIT_REASON_INIT_SIGNAL 3
217 #define VM_EXIT_REASON_STARTUP_IPI 4
218 #define VM_EXIT_REASON_IO_SMI 5
219 #define VM_EXIT_REASON_OTHER_SMI 6
220 #define VM_EXIT_REASON_INTR_WINDOW 7
221 #define VM_EXIT_REASON_NMI_WINDOW 8
222 #define VM_EXIT_REASON_TASK_SWITCH 9
223 #define VM_EXIT_REASON_CPUID 10
224 #define VM_EXIT_REASON_HLT 12
225 #define VM_EXIT_REASON_INVD 13
226 #define VM_EXIT_REASON_INVLPG 14
227 #define VM_EXIT_REASON_RDPMC 15
228 #define VM_EXIT_REASON_RDTSC 16
229 #define VM_EXIT_REASON_RSM 17
230 #define VM_EXIT_REASON_VMCALL 18
231 #define VM_EXIT_REASON_VMCLEAR 19
232 #define VM_EXIT_REASON_VMLAUNCH 20
233 #define VM_EXIT_REASON_VMPTRLD 21
234 #define VM_EXIT_REASON_VMPTRST 22
235 #define VM_EXIT_REASON_VMREAD 23
236 #define VM_EXIT_REASON_VMRESUME 24
237 #define VM_EXIT_REASON_VMWRITE 25
238 #define VM_EXIT_REASON_VMXOFF 26
239 #define VM_EXIT_REASON_VMXON 27
240 #define VM_EXIT_REASON_CR_REG_ACCESSES 28
241 #define VM_EXIT_REASON_MOV_DR 29
242 #define VM_EXIT_REASON_IO_INSTR 30
243 #define VM_EXIT_REASON_RDMSR 31
244 #define VM_EXIT_REASON_WRMSR 32
245 #define VM_EXIT_REASON_ENTRY_FAIL_INVALID_GUEST_STATE 33
246 #define VM_EXIT_REASON_ENTRY_FAIL_MSR_LOAD 34
247 #define VM_EXIT_REASON_MWAIT 36
248 #define VM_EXIT_REASON_MONITOR 39
249 #define VM_EXIT_REASON_PAUSE 40
250 #define VM_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK 41
251 #define VM_EXIT_REASON_TPR_BELOW_THRESHOLD 43
254 extern char *exception_names[];
255 extern char *exception_type_names[];
266 #define PACKED __attribute__((packed))
271 /* VMCS Exit QUALIFICATIONs */
272 struct VMExitIOQual {
273 uint_t accessSize : 3 PACKED; // (0: 1 Byte ;; 1: 2 Bytes ;; 3: 4 Bytes)
274 uint_t dir : 1 PACKED; // (0: Out ;; 1: In)
275 uint_t string : 1 PACKED; // (0: not string ;; 1: string)
276 uint_t REP : 1 PACKED; // (0: not REP ;; 1: REP)
277 uint_t opEnc : 1 PACKED; // (0: DX ;; 1: immediate)
278 uint_t rsvd : 9 PACKED; // Set to 0
279 uint_t port : 16 PACKED; // IO Port Number
284 struct VMExitDBGQual {
285 uint_t B0 : 1 PACKED; // Breakpoint 0 condition met
286 uint_t B1 : 1 PACKED; // Breakpoint 1 condition met
287 uint_t B2 : 1 PACKED; // Breakpoint 2 condition met
288 uint_t B3 : 1 PACKED; // Breakpoint 3 condition met
289 uint_t rsvd : 9 PACKED; // reserved to 0
290 uint_t BD : 1 PACKED; // detected DBG reg access
291 uint_t BS : 1 PACKED; // cause either single instr or taken branch
295 struct VMExitTSQual {
296 uint_t selector : 16 PACKED; // selector of destination TSS
297 uint_t rsvd : 14 PACKED; // reserved to 0
298 uint_t src : 2 PACKED; // (0: CALL ; 1: IRET ; 2: JMP ; 3: Task gate in IDT)
301 struct VMExitCRQual {
302 uint_t crID : 4 PACKED; // cr number (0 for CLTS and LMSW) (bit 3 always 0, on 32bit)
303 uint_t accessType : 2 PACKED; // (0: MOV to CR ; 1: MOV from CR ; 2: CLTS ; 3: LMSW)
304 uint_t lmswOpType : 1 PACKED; // (0: register ; 1: memory)
305 uint_t rsvd1 : 1 PACKED; // reserved to 0
306 uint_t gpr : 4 PACKED; // (0:RAX+[CLTS/LMSW], 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
307 uint_t rsvd2 : 4 PACKED; // reserved to 0
308 uint_t lmswSrc : 16 PACKED; // src data for lmsw
311 struct VMExitMovDRQual {
312 uint_t regID : 3 PACKED; // debug register number
313 uint_t rsvd1 : 1 PACKED; // reserved to 0
314 uint_t dir : 1 PACKED; // (0: MOV to DR , 1: MOV from DR)
315 uint_t rsvd2 : 3 PACKED; // reserved to 0
316 uint_t gpr : 4 PACKED; // (0:RAX, 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
319 /* End Exit Qualifications */
321 /* Exit Vector Info */
322 struct VMExitIntInfo {
323 uint_t nr : 8 PACKED; // IRQ number, exception vector, NMI = 2
324 uint_t type : 3 PACKED; // (0: ext. IRQ , 2: NMI , 3: hw exception , 6: sw exception
325 uint_t errorCode : 1 PACKED; // 1: error Code present
326 uint_t iret : 1 PACKED; // something to do with NMIs and IRETs (Intel 3B, sec. 23.2.2)
327 uint_t rsvd : 18 PACKED; // always 0
328 uint_t valid : 1 PACKED; // always 1 if valid
334 /* End Exit Vector Info */
339 /* Segment Selector Access Rights (32 bits) */
340 /* INTEL Manual: 20-4 vol 3B */
344 uint_t descType : 1 PACKED;
345 uint_t dpl : 2 PACKED;
346 uint_t present : 1 PACKED;
347 uchar_t rsvd1 PACKED;
348 uint_t avail : 1 PACKED ;
349 uint_t L : 1 PACKED ; // CS only (64 bit active), reserved otherwise
350 uint_t DB : 1 PACKED ;
351 uint_t granularity : 1 PACKED ;
352 uint_t unusable : 1 PACKED ;
353 uint_t rsvd2 : 15 PACKED ;
361 union SegAccess access;
363 uint_t baseAddr ; // should be 64 bits?
368 struct VMCSGuestStateArea {
369 /* (1) Guest State Area */
370 /* (1.1) Guest Register State */
371 uint_t cr0 ; // should be 64 bits?
372 uint_t cr3 ; // should be 64 bits?
373 uint_t cr4 ; // should be 64 bits?
374 uint_t dr7 ; // should be 64 bits?
375 uint_t rsp ; // should be 64 bits?
376 uint_t rip ; // should be 64 bits?
377 uint_t rflags ; // should be 64 bits?
380 struct VMCSSegment cs ;
381 struct VMCSSegment ss ;
382 struct VMCSSegment ds ;
383 struct VMCSSegment es ;
384 struct VMCSSegment fs ;
385 struct VMCSSegment gs ;
386 struct VMCSSegment ldtr ;
387 struct VMCSSegment tr ;
389 struct VMCSSegment gdtr ;
390 struct VMCSSegment idtr ;
395 ullong_t sysenter_esp ; // should be 64 bits?
396 ullong_t sysenter_eip ; // should be 64 bits?
400 /* (1.2) Guest Non-register State */
401 uint_t activity ; /* (0=Active, 1=HLT, 2=Shutdown, 3=Wait-for-SIPI)
402 (listed in MSR: IA32_VMX_MISC) */
404 uint_t interrupt_state ; // see Table 20-3 (page 20-6) INTEL MANUAL 3B
406 ullong_t pending_dbg_exceptions ; // should be 64 bits?
407 /* Table 20-4 page 20-8 INTEL MANUAL 3B */
409 ullong_t vmcs_link ; // should be set to 0xffffffff_ffffffff
413 int CopyOutVMCSGuestStateArea(struct VMCSGuestStateArea *p);
414 int CopyInVMCSGuestStateArea(struct VMCSGuestStateArea *p);
418 struct VMCSHostStateArea {
419 /* (2) Host State Area */
420 ullong_t cr0 ; // Should be 64 bits?
421 ullong_t cr3 ; // should be 64 bits?
422 ullong_t cr4 ; // should be 64 bits?
423 ullong_t rsp ; // should be 64 bits?
424 ullong_t rip ; // should be 64 bits?
426 ushort_t csSelector ;
427 ushort_t ssSelector ;
428 ushort_t dsSelector ;
429 ushort_t esSelector ;
430 ushort_t fsSelector ;
431 ushort_t gsSelector ;
432 ushort_t trSelector ;
434 ullong_t fsBaseAddr ; // Should be 64 bits?
435 ullong_t gsBaseAddr ; // Should be 64 bits?
436 ullong_t trBaseAddr ; // Should be 64 bits?
437 ullong_t gdtrBaseAddr ; // Should be 64 bits?
438 ullong_t idtrBaseAddr ; // Should be 64 bits?
443 ullong_t sysenter_esp ; // Should be 64 bits?
444 ullong_t sysenter_eip ; // Should be 64 bits?
448 int CopyOutVMCSHostStateArea(struct VMCSHostStateArea *p);
449 int CopyInVMCSHostStateArea(struct VMCSHostStateArea *p);
452 struct VMCSExecCtrlFields {
453 uint_t pinCtrls ; // Table 20-5, Vol 3B. (pg. 20-10)
454 uint_t procCtrls ; // Table 20-6, Vol 3B. (pg. 20-11)
456 uint_t pageFaultErrorMask ;
457 uint_t pageFaultErrorMatch ;
461 uint_t cr0GuestHostMask ; // Should be 64 bits?
462 uint_t cr0ReadShadow ; // Should be 64 bits?
463 uint_t cr4GuestHostMask ; // Should be 64 bits?
464 uint_t cr4ReadShadow ; // Should be 64 bits?
465 uint_t cr3TargetValue0 ; // should be 64 bits?
466 uint_t cr3TargetValue1 ; // should be 64 bits?
467 uint_t cr3TargetValue2 ; // should be 64 bits?
468 uint_t cr3TargetValue3 ; // should be 64 bits?
469 uint_t cr3TargetCount ;
473 /* these fields enabled if "use TPR shadow"==1 */
474 /* may not need them */
475 ullong_t virtApicPageAddr ;
476 // uint_t virtApicPageAddrHigh
477 uint_t tprThreshold ;
480 ullong_t MSRBitmapsBaseAddr;
483 ullong_t vmcsExecPtr ;
487 int CopyOutVMCSExecCtrlFields(struct VMCSExecCtrlFields *p);
488 int CopyInVMCSExecCtrlFields(struct VMCSExecCtrlFields *p);
493 struct VMCSExitCtrlFields {
494 uint_t exitCtrls ; // Table 20-7, Vol. 3B (pg. 20-16)
495 uint_t msrStoreCount ;
496 ullong_t msrStoreAddr ;
497 uint_t msrLoadCount ;
498 ullong_t msrLoadAddr ;
501 int CopyOutVMCSExitCtrlFields(struct VMCSExitCtrlFields *p);
502 int CopyInVMCSExitCtrlFields(struct VMCSExitCtrlFields *p);
506 struct VMCSEntryCtrlFields {
507 uint_t entryCtrls ; // Table 20-9, Vol. 3B (pg. 20-18)
508 uint_t msrLoadCount ;
509 ullong_t msrLoadAddr ;
510 uint_t intInfo ; // Table 20-10, Vol. 3B (pg. 20-19)
511 uint_t exceptionErrorCode ;
516 int CopyOutVMCSEntryCtrlFields(struct VMCSEntryCtrlFields *p);
517 int CopyInVMCSEntryCtrlFields(struct VMCSEntryCtrlFields *p);
520 struct VMCSExitInfoFields {
521 uint_t reason; // Table 20-11, Vol. 3B (pg. 20-20)
522 uint_t qualification ; // Should be 64 bits?
524 uint_t intErrorCode ;
525 uint_t idtVectorInfo ;
526 uint_t idtVectorErrorCode ;
528 ullong_t guestLinearAddr ; // Should be 64 bits?
530 ullong_t ioRCX ; // Should be 64 bits?
531 ullong_t ioRSI ; // Should be 64 bits?
532 ullong_t ioRDI ; // Should be 64 bits?
533 ullong_t ioRIP ; // Should be 64 bits?
534 uint_t instrErrorField ;
539 int CopyOutVMCSExitInfoFields(struct VMCSExitInfoFields *p);
546 uint_t exitCtrlFlags;
547 struct VMCSGuestStateArea guestStateArea ;
548 struct VMCSHostStateArea hostStateArea ;
549 struct VMCSExecCtrlFields execCtrlFields ;
550 struct VMCSExitCtrlFields exitCtrlFields ;
551 struct VMCSEntryCtrlFields entryCtrlFields ;
552 struct VMCSExitInfoFields exitInfoFields ;
556 int CopyOutVMCSData(struct VMCSData *p);
557 int CopyInVMCSData(struct VMCSData *p);
570 void PrintTrace_VMX_Regs(struct VMXRegs *regs);
571 void PrintTrace_VMCSData(struct VMCSData * vmcs);
572 void PrintTrace_VMCSGuestStateArea(struct VMCSGuestStateArea * guestState);
573 void PrintTrace_VMCSHostStateArea(struct VMCSHostStateArea * hostState);
574 void PrintTrace_VMCSExecCtrlFields(struct VMCSExecCtrlFields * execCtrls);
575 void PrintTrace_VMCSExitCtrlFields(struct VMCSExitCtrlFields * exitCtrls);
576 void PrintTrace_VMCSEntryCtrlFields(struct VMCSEntryCtrlFields * entryCtrls);
577 void PrintTrace_VMCSExitInfoFields(struct VMCSExitInfoFields * exitInfo);
578 void PrintTrace_VMCSSegment(char * segname, struct VMCSSegment * seg, int abbr);
581 extern uint_t VMCS_WRITE();
582 extern uint_t VMCS_READ();
584 //uint_t VMCSRead(uint_t tag, void * val);
587 #include <palacios/vmcs_gen.h>
589 #endif // ! __V3VEE__