1 /* (c) 2008, Peter Dinda <pdinda@northwestern.edu> */
2 /* (c) 2008, Jack Lange <jarusl@cs.northwestern.edu> */
3 /* (c) 2008, The V3VEE Project <http://www.v3vee.org> */
10 #include <palacios/vmm_types.h>
13 /* 16 bit guest state */
14 #define VMCS_GUEST_ES_SELECTOR 0x00000800
15 #define VMCS_GUEST_CS_SELECTOR 0x00000802
16 #define VMCS_GUEST_SS_SELECTOR 0x00000804
17 #define VMCS_GUEST_DS_SELECTOR 0x00000806
18 #define VMCS_GUEST_FS_SELECTOR 0x00000808
19 #define VMCS_GUEST_GS_SELECTOR 0x0000080A
20 #define VMCS_GUEST_LDTR_SELECTOR 0x0000080C
21 #define VMCS_GUEST_TR_SELECTOR 0x0000080E
23 /* 16 bit host state */
24 #define VMCS_HOST_ES_SELECTOR 0x00000C00
25 #define VMCS_HOST_CS_SELECTOR 0x00000C02
26 #define VMCS_HOST_SS_SELECTOR 0x00000C04
27 #define VMCS_HOST_DS_SELECTOR 0x00000C06
28 #define VMCS_HOST_FS_SELECTOR 0x00000C08
29 #define VMCS_HOST_GS_SELECTOR 0x00000C0A
30 #define VMCS_HOST_TR_SELECTOR 0x00000C0C
32 /* 64 bit control fields */
33 #define IO_BITMAP_A_ADDR 0x00002000
34 #define IO_BITMAP_A_ADDR_HIGH 0x00002001
35 #define IO_BITMAP_B_ADDR 0x00002002
36 #define IO_BITMAP_B_ADDR_HIGH 0x00002003
37 // Only with "Use MSR Bitmaps" enabled
38 #define MSR_BITMAPS 0x00002004
39 #define MSR_BITMAPS_HIGH 0x00002005
41 #define VM_EXIT_MSR_STORE_ADDR 0x00002006
42 #define VM_EXIT_MSR_STORE_ADDR_HIGH 0x00002007
43 #define VM_EXIT_MSR_LOAD_ADDR 0x00002008
44 #define VM_EXIT_MSR_LOAD_ADDR_HIGH 0x00002009
45 #define VM_ENTRY_MSR_LOAD_ADDR 0x0000200A
46 #define VM_ENTRY_MSR_LOAD_ADDR_HIGH 0x0000200B
47 #define VMCS_EXEC_PTR 0x0000200C
48 #define VMCS_EXEC_PTR_HIGH 0x0000200D
49 #define TSC_OFFSET 0x00002010
50 #define TSC_OFFSET_HIGH 0x00002011
51 // Only with "Use TPR Shadow" enabled
52 #define VIRT_APIC_PAGE_ADDR 0x00002012
53 #define VIRT_APIC_PAGE_ADDR_HIGH 0x00002013
57 /* 64 bit guest state fields */
58 #define VMCS_LINK_PTR 0x00002800
59 #define VMCS_LINK_PTR_HIGH 0x00002801
60 #define GUEST_IA32_DEBUGCTL 0x00002802
61 #define GUEST_IA32_DEBUGCTL_HIGH 0x00002803
64 /* 32 bit control fields */
65 #define PIN_VM_EXEC_CTRLS 0x00004000
66 #define PROC_VM_EXEC_CTRLS 0x00004002
67 #define EXCEPTION_BITMAP 0x00004004
68 #define PAGE_FAULT_ERROR_MASK 0x00004006
69 #define PAGE_FAULT_ERROR_MATCH 0x00004008
70 #define CR3_TARGET_COUNT 0x0000400A
71 #define VM_EXIT_CTRLS 0x0000400C
72 #define VM_EXIT_MSR_STORE_COUNT 0x0000400E
73 #define VM_EXIT_MSR_LOAD_COUNT 0x00004010
74 #define VM_ENTRY_CTRLS 0x00004012
75 #define VM_ENTRY_MSR_LOAD_COUNT 0x00004014
76 #define VM_ENTRY_INT_INFO_FIELD 0x00004016
77 #define VM_ENTRY_EXCEPTION_ERROR 0x00004018
78 #define VM_ENTRY_INSTR_LENGTH 0x0000401A
79 // Only with "Use TPR Shadow" Enabled
80 #define TPR_THRESHOLD 0x0000401C
84 /* 32 bit Read Only data fields */
85 #define VM_INSTR_ERROR 0x00004400
86 #define EXIT_REASON 0x00004402
87 #define VM_EXIT_INT_INFO 0x00004404
88 #define VM_EXIT_INT_ERROR 0x00004406
89 #define IDT_VECTOR_INFO 0x00004408
90 #define IDT_VECTOR_ERROR 0x0000440A
91 #define VM_EXIT_INSTR_LENGTH 0x0000440C
92 #define VMX_INSTR_INFO 0x0000440E
94 /* 32 bit Guest state fields */
95 #define GUEST_ES_LIMIT 0x00004800
96 #define GUEST_CS_LIMIT 0x00004802
97 #define GUEST_SS_LIMIT 0x00004804
98 #define GUEST_DS_LIMIT 0x00004806
99 #define GUEST_FS_LIMIT 0x00004808
100 #define GUEST_GS_LIMIT 0x0000480A
101 #define GUEST_LDTR_LIMIT 0x0000480C
102 #define GUEST_TR_LIMIT 0x0000480E
103 #define GUEST_GDTR_LIMIT 0x00004810
104 #define GUEST_IDTR_LIMIT 0x00004812
105 #define GUEST_ES_ACCESS 0x00004814
106 #define GUEST_CS_ACCESS 0x00004816
107 #define GUEST_SS_ACCESS 0x00004818
108 #define GUEST_DS_ACCESS 0x0000481A
109 #define GUEST_FS_ACCESS 0x0000481C
110 #define GUEST_GS_ACCESS 0x0000481E
111 #define GUEST_LDTR_ACCESS 0x00004820
112 #define GUEST_TR_ACCESS 0x00004822
113 #define GUEST_INT_STATE 0x00004824
114 #define GUEST_ACTIVITY_STATE 0x00004826
115 #define GUEST_SMBASE 0x00004828
116 #define GUEST_IA32_SYSENTER_CS 0x0000482A
119 /* 32 bit host state field */
120 #define HOST_IA32_SYSENTER_CS 0x00004C00
122 /* Natural Width Control Fields */
123 #define CR0_GUEST_HOST_MASK 0x00006000
124 #define CR4_GUEST_HOST_MASK 0x00006002
125 #define CR0_READ_SHADOW 0x00006004
126 #define CR4_READ_SHADOW 0x00006006
127 #define CR3_TARGET_VALUE_0 0x00006008
128 #define CR3_TARGET_VALUE_1 0x0000600A
129 #define CR3_TARGET_VALUE_2 0x0000600C
130 #define CR3_TARGET_VALUE_3 0x0000600E
133 /* Natural Width Read Only Fields */
134 #define EXIT_QUALIFICATION 0x00006400
135 #define IO_RCX 0x00006402
136 #define IO_RSI 0x00006404
137 #define IO_RDI 0x00006406
138 #define IO_RIP 0x00006408
139 #define GUEST_LINEAR_ADDR 0x0000640A
141 /* Natural Width Guest State Fields */
142 #define GUEST_CR0 0x00006800
143 #define GUEST_CR3 0x00006802
144 #define GUEST_CR4 0x00006804
145 #define GUEST_ES_BASE 0x00006806
146 #define GUEST_CS_BASE 0x00006808
147 #define GUEST_SS_BASE 0x0000680A
148 #define GUEST_DS_BASE 0x0000680C
149 #define GUEST_FS_BASE 0x0000680E
150 #define GUEST_GS_BASE 0x00006810
151 #define GUEST_LDTR_BASE 0x00006812
152 #define GUEST_TR_BASE 0x00006814
153 #define GUEST_GDTR_BASE 0x00006816
154 #define GUEST_IDTR_BASE 0x00006818
155 #define GUEST_DR7 0x0000681A
156 #define GUEST_RSP 0x0000681C
157 #define GUEST_RIP 0x0000681E
158 #define GUEST_RFLAGS 0x00006820
159 #define GUEST_PENDING_DEBUG_EXCS 0x00006822
160 #define GUEST_IA32_SYSENTER_ESP 0x00006824
161 #define GUEST_IA32_SYSENTER_EIP 0x00006826
164 /* Natural Width Host State Fields */
165 #define HOST_CR0 0x00006C00
166 #define HOST_CR3 0x00006C02
167 #define HOST_CR4 0x00006C04
168 #define HOST_FS_BASE 0x00006C06
169 #define HOST_GS_BASE 0x00006C08
170 #define HOST_TR_BASE 0x00006C0A
171 #define HOST_GDTR_BASE 0x00006C0C
172 #define HOST_IDTR_BASE 0x00006C0E
173 #define HOST_IA32_SYSENTER_ESP 0x00006C10
174 #define HOST_IA32_SYSENTER_EIP 0x00006C12
175 #define HOST_RSP 0x00006C14
176 #define HOST_RIP 0x00006C16
178 /* Pin Based VM Execution Controls */
179 /* INTEL MANUAL: 20-10 vol 3B */
180 #define EXTERNAL_INTERRUPT_EXITING 0x00000001
181 #define NMI_EXITING 0x00000008
182 #define VIRTUAL_NMIS 0x00000020
185 /* Processor Based VM Execution Controls */
186 /* INTEL MANUAL: 20-11 vol. 3B */
187 #define INTERRUPT_WINDOWS_EXIT 0x00000004
188 #define USE_TSC_OFFSETTING 0x00000008
189 #define HLT_EXITING 0x00000080
190 #define INVLPG_EXITING 0x00000200
191 #define MWAIT_EXITING 0x00000400
192 #define RDPMC_EXITING 0x00000800
193 #define RDTSC_EXITING 0x00001000
194 #define CR8_LOAD_EXITING 0x00080000
195 #define CR8_STORE_EXITING 0x00100000
196 #define USE_TPR_SHADOW 0x00200000
197 #define NMI_WINDOW_EXITING 0x00400000
198 #define MOVDR_EXITING 0x00800000
199 #define UNCONDITION_IO_EXITING 0x01000000
200 #define USE_IO_BITMAPS 0x02000000
201 #define USE_MSR_BITMAPS 0x10000000
202 #define MONITOR_EXITING 0x20000000
203 #define PAUSE_EXITING 0x40000000
205 /* VM-Exit Controls */
206 /* INTEL MANUAL: 20-16 vol. 3B */
207 #define HOST_ADDR_SPACE_SIZE 0x00000200
208 #define ACK_IRQ_ON_EXIT 0x00008000
211 #define VM_EXIT_REASON_INFO_EXCEPTION_OR_NMI 0
212 #define VM_EXIT_REASON_EXTERNAL_INTR 1
213 #define VM_EXIT_REASON_TRIPLE_FAULT 2
214 #define VM_EXIT_REASON_INIT_SIGNAL 3
215 #define VM_EXIT_REASON_STARTUP_IPI 4
216 #define VM_EXIT_REASON_IO_SMI 5
217 #define VM_EXIT_REASON_OTHER_SMI 6
218 #define VM_EXIT_REASON_INTR_WINDOW 7
219 #define VM_EXIT_REASON_NMI_WINDOW 8
220 #define VM_EXIT_REASON_TASK_SWITCH 9
221 #define VM_EXIT_REASON_CPUID 10
222 #define VM_EXIT_REASON_HLT 12
223 #define VM_EXIT_REASON_INVD 13
224 #define VM_EXIT_REASON_INVLPG 14
225 #define VM_EXIT_REASON_RDPMC 15
226 #define VM_EXIT_REASON_RDTSC 16
227 #define VM_EXIT_REASON_RSM 17
228 #define VM_EXIT_REASON_VMCALL 18
229 #define VM_EXIT_REASON_VMCLEAR 19
230 #define VM_EXIT_REASON_VMLAUNCH 20
231 #define VM_EXIT_REASON_VMPTRLD 21
232 #define VM_EXIT_REASON_VMPTRST 22
233 #define VM_EXIT_REASON_VMREAD 23
234 #define VM_EXIT_REASON_VMRESUME 24
235 #define VM_EXIT_REASON_VMWRITE 25
236 #define VM_EXIT_REASON_VMXOFF 26
237 #define VM_EXIT_REASON_VMXON 27
238 #define VM_EXIT_REASON_CR_REG_ACCESSES 28
239 #define VM_EXIT_REASON_MOV_DR 29
240 #define VM_EXIT_REASON_IO_INSTR 30
241 #define VM_EXIT_REASON_RDMSR 31
242 #define VM_EXIT_REASON_WRMSR 32
243 #define VM_EXIT_REASON_ENTRY_FAIL_INVALID_GUEST_STATE 33
244 #define VM_EXIT_REASON_ENTRY_FAIL_MSR_LOAD 34
245 #define VM_EXIT_REASON_MWAIT 36
246 #define VM_EXIT_REASON_MONITOR 39
247 #define VM_EXIT_REASON_PAUSE 40
248 #define VM_EXIT_REASON_ENTRY_FAILURE_MACHINE_CHECK 41
249 #define VM_EXIT_REASON_TPR_BELOW_THRESHOLD 43
252 extern char *exception_names[];
253 extern char *exception_type_names[];
264 #define PACKED __attribute__((packed))
269 /* VMCS Exit QUALIFICATIONs */
270 struct VMExitIOQual {
271 uint_t accessSize : 3 PACKED; // (0: 1 Byte ;; 1: 2 Bytes ;; 3: 4 Bytes)
272 uint_t dir : 1 PACKED; // (0: Out ;; 1: In)
273 uint_t string : 1 PACKED; // (0: not string ;; 1: string)
274 uint_t REP : 1 PACKED; // (0: not REP ;; 1: REP)
275 uint_t opEnc : 1 PACKED; // (0: DX ;; 1: immediate)
276 uint_t rsvd : 9 PACKED; // Set to 0
277 uint_t port : 16 PACKED; // IO Port Number
282 struct VMExitDBGQual {
283 uint_t B0 : 1 PACKED; // Breakpoint 0 condition met
284 uint_t B1 : 1 PACKED; // Breakpoint 1 condition met
285 uint_t B2 : 1 PACKED; // Breakpoint 2 condition met
286 uint_t B3 : 1 PACKED; // Breakpoint 3 condition met
287 uint_t rsvd : 9 PACKED; // reserved to 0
288 uint_t BD : 1 PACKED; // detected DBG reg access
289 uint_t BS : 1 PACKED; // cause either single instr or taken branch
293 struct VMExitTSQual {
294 uint_t selector : 16 PACKED; // selector of destination TSS
295 uint_t rsvd : 14 PACKED; // reserved to 0
296 uint_t src : 2 PACKED; // (0: CALL ; 1: IRET ; 2: JMP ; 3: Task gate in IDT)
299 struct VMExitCRQual {
300 uint_t crID : 4 PACKED; // cr number (0 for CLTS and LMSW) (bit 3 always 0, on 32bit)
301 uint_t accessType : 2 PACKED; // (0: MOV to CR ; 1: MOV from CR ; 2: CLTS ; 3: LMSW)
302 uint_t lmswOpType : 1 PACKED; // (0: register ; 1: memory)
303 uint_t rsvd1 : 1 PACKED; // reserved to 0
304 uint_t gpr : 4 PACKED; // (0:RAX+[CLTS/LMSW], 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
305 uint_t rsvd2 : 4 PACKED; // reserved to 0
306 uint_t lmswSrc : 16 PACKED; // src data for lmsw
309 struct VMExitMovDRQual {
310 uint_t regID : 3 PACKED; // debug register number
311 uint_t rsvd1 : 1 PACKED; // reserved to 0
312 uint_t dir : 1 PACKED; // (0: MOV to DR , 1: MOV from DR)
313 uint_t rsvd2 : 3 PACKED; // reserved to 0
314 uint_t gpr : 4 PACKED; // (0:RAX, 1:RCX, 2:RDX, 3:RBX, 4:RSP, 5:RBP, 6:RSI, 6:RDI, 8-15:64bit regs)
317 /* End Exit Qualifications */
319 /* Exit Vector Info */
320 struct VMExitIntInfo {
321 uint_t nr : 8 PACKED; // IRQ number, exception vector, NMI = 2
322 uint_t type : 3 PACKED; // (0: ext. IRQ , 2: NMI , 3: hw exception , 6: sw exception
323 uint_t errorCode : 1 PACKED; // 1: error Code present
324 uint_t iret : 1 PACKED; // something to do with NMIs and IRETs (Intel 3B, sec. 23.2.2)
325 uint_t rsvd : 18 PACKED; // always 0
326 uint_t valid : 1 PACKED; // always 1 if valid
332 /* End Exit Vector Info */
337 /* Segment Selector Access Rights (32 bits) */
338 /* INTEL Manual: 20-4 vol 3B */
342 uint_t descType : 1 PACKED;
343 uint_t dpl : 2 PACKED;
344 uint_t present : 1 PACKED;
345 uchar_t rsvd1 PACKED;
346 uint_t avail : 1 PACKED ;
347 uint_t L : 1 PACKED ; // CS only (64 bit active), reserved otherwise
348 uint_t DB : 1 PACKED ;
349 uint_t granularity : 1 PACKED ;
350 uint_t unusable : 1 PACKED ;
351 uint_t rsvd2 : 15 PACKED ;
359 union SegAccess access;
361 uint_t baseAddr ; // should be 64 bits?
366 struct VMCSGuestStateArea {
367 /* (1) Guest State Area */
368 /* (1.1) Guest Register State */
369 uint_t cr0 ; // should be 64 bits?
370 uint_t cr3 ; // should be 64 bits?
371 uint_t cr4 ; // should be 64 bits?
372 uint_t dr7 ; // should be 64 bits?
373 uint_t rsp ; // should be 64 bits?
374 uint_t rip ; // should be 64 bits?
375 uint_t rflags ; // should be 64 bits?
378 struct VMCSSegment cs ;
379 struct VMCSSegment ss ;
380 struct VMCSSegment ds ;
381 struct VMCSSegment es ;
382 struct VMCSSegment fs ;
383 struct VMCSSegment gs ;
384 struct VMCSSegment ldtr ;
385 struct VMCSSegment tr ;
387 struct VMCSSegment gdtr ;
388 struct VMCSSegment idtr ;
393 ullong_t sysenter_esp ; // should be 64 bits?
394 ullong_t sysenter_eip ; // should be 64 bits?
398 /* (1.2) Guest Non-register State */
399 uint_t activity ; /* (0=Active, 1=HLT, 2=Shutdown, 3=Wait-for-SIPI)
400 (listed in MSR: IA32_VMX_MISC) */
402 uint_t interrupt_state ; // see Table 20-3 (page 20-6) INTEL MANUAL 3B
404 ullong_t pending_dbg_exceptions ; // should be 64 bits?
405 /* Table 20-4 page 20-8 INTEL MANUAL 3B */
407 ullong_t vmcs_link ; // should be set to 0xffffffff_ffffffff
411 int CopyOutVMCSGuestStateArea(struct VMCSGuestStateArea *p);
412 int CopyInVMCSGuestStateArea(struct VMCSGuestStateArea *p);
416 struct VMCSHostStateArea {
417 /* (2) Host State Area */
418 ullong_t cr0 ; // Should be 64 bits?
419 ullong_t cr3 ; // should be 64 bits?
420 ullong_t cr4 ; // should be 64 bits?
421 ullong_t rsp ; // should be 64 bits?
422 ullong_t rip ; // should be 64 bits?
424 ushort_t csSelector ;
425 ushort_t ssSelector ;
426 ushort_t dsSelector ;
427 ushort_t esSelector ;
428 ushort_t fsSelector ;
429 ushort_t gsSelector ;
430 ushort_t trSelector ;
432 ullong_t fsBaseAddr ; // Should be 64 bits?
433 ullong_t gsBaseAddr ; // Should be 64 bits?
434 ullong_t trBaseAddr ; // Should be 64 bits?
435 ullong_t gdtrBaseAddr ; // Should be 64 bits?
436 ullong_t idtrBaseAddr ; // Should be 64 bits?
441 ullong_t sysenter_esp ; // Should be 64 bits?
442 ullong_t sysenter_eip ; // Should be 64 bits?
446 int CopyOutVMCSHostStateArea(struct VMCSHostStateArea *p);
447 int CopyInVMCSHostStateArea(struct VMCSHostStateArea *p);
450 struct VMCSExecCtrlFields {
451 uint_t pinCtrls ; // Table 20-5, Vol 3B. (pg. 20-10)
452 uint_t procCtrls ; // Table 20-6, Vol 3B. (pg. 20-11)
454 uint_t pageFaultErrorMask ;
455 uint_t pageFaultErrorMatch ;
459 uint_t cr0GuestHostMask ; // Should be 64 bits?
460 uint_t cr0ReadShadow ; // Should be 64 bits?
461 uint_t cr4GuestHostMask ; // Should be 64 bits?
462 uint_t cr4ReadShadow ; // Should be 64 bits?
463 uint_t cr3TargetValue0 ; // should be 64 bits?
464 uint_t cr3TargetValue1 ; // should be 64 bits?
465 uint_t cr3TargetValue2 ; // should be 64 bits?
466 uint_t cr3TargetValue3 ; // should be 64 bits?
467 uint_t cr3TargetCount ;
471 /* these fields enabled if "use TPR shadow"==1 */
472 /* may not need them */
473 ullong_t virtApicPageAddr ;
474 // uint_t virtApicPageAddrHigh
475 uint_t tprThreshold ;
478 ullong_t MSRBitmapsBaseAddr;
481 ullong_t vmcsExecPtr ;
485 int CopyOutVMCSExecCtrlFields(struct VMCSExecCtrlFields *p);
486 int CopyInVMCSExecCtrlFields(struct VMCSExecCtrlFields *p);
491 struct VMCSExitCtrlFields {
492 uint_t exitCtrls ; // Table 20-7, Vol. 3B (pg. 20-16)
493 uint_t msrStoreCount ;
494 ullong_t msrStoreAddr ;
495 uint_t msrLoadCount ;
496 ullong_t msrLoadAddr ;
499 int CopyOutVMCSExitCtrlFields(struct VMCSExitCtrlFields *p);
500 int CopyInVMCSExitCtrlFields(struct VMCSExitCtrlFields *p);
504 struct VMCSEntryCtrlFields {
505 uint_t entryCtrls ; // Table 20-9, Vol. 3B (pg. 20-18)
506 uint_t msrLoadCount ;
507 ullong_t msrLoadAddr ;
508 uint_t intInfo ; // Table 20-10, Vol. 3B (pg. 20-19)
509 uint_t exceptionErrorCode ;
514 int CopyOutVMCSEntryCtrlFields(struct VMCSEntryCtrlFields *p);
515 int CopyInVMCSEntryCtrlFields(struct VMCSEntryCtrlFields *p);
518 struct VMCSExitInfoFields {
519 uint_t reason; // Table 20-11, Vol. 3B (pg. 20-20)
520 uint_t qualification ; // Should be 64 bits?
522 uint_t intErrorCode ;
523 uint_t idtVectorInfo ;
524 uint_t idtVectorErrorCode ;
526 ullong_t guestLinearAddr ; // Should be 64 bits?
528 ullong_t ioRCX ; // Should be 64 bits?
529 ullong_t ioRSI ; // Should be 64 bits?
530 ullong_t ioRDI ; // Should be 64 bits?
531 ullong_t ioRIP ; // Should be 64 bits?
532 uint_t instrErrorField ;
537 int CopyOutVMCSExitInfoFields(struct VMCSExitInfoFields *p);
544 uint_t exitCtrlFlags;
545 struct VMCSGuestStateArea guestStateArea ;
546 struct VMCSHostStateArea hostStateArea ;
547 struct VMCSExecCtrlFields execCtrlFields ;
548 struct VMCSExitCtrlFields exitCtrlFields ;
549 struct VMCSEntryCtrlFields entryCtrlFields ;
550 struct VMCSExitInfoFields exitInfoFields ;
554 int CopyOutVMCSData(struct VMCSData *p);
555 int CopyInVMCSData(struct VMCSData *p);
568 void PrintTrace_VMX_Regs(struct VMXRegs *regs);
569 void PrintTrace_VMCSData(struct VMCSData * vmcs);
570 void PrintTrace_VMCSGuestStateArea(struct VMCSGuestStateArea * guestState);
571 void PrintTrace_VMCSHostStateArea(struct VMCSHostStateArea * hostState);
572 void PrintTrace_VMCSExecCtrlFields(struct VMCSExecCtrlFields * execCtrls);
573 void PrintTrace_VMCSExitCtrlFields(struct VMCSExitCtrlFields * exitCtrls);
574 void PrintTrace_VMCSEntryCtrlFields(struct VMCSEntryCtrlFields * entryCtrls);
575 void PrintTrace_VMCSExitInfoFields(struct VMCSExitInfoFields * exitInfo);
576 void PrintTrace_VMCSSegment(char * segname, struct VMCSSegment * seg, int abbr);
579 extern uint_t VMCS_WRITE();
580 extern uint_t VMCS_READ();
582 //uint_t VMCSRead(uint_t tag, void * val);
585 #include <palacios/vmcs_gen.h>
587 #endif // ! __V3VEE__