4 #include <palacios/vmm_util.h>
5 #include <palacios/vmm.h>
6 #include <palacios/vmcb.h>
8 #define CPUID_FEATURE_IDS 0x80000001
9 #define CPUID_FEATURE_IDS_ecx_svm_avail 0x00000004
11 #define CPUID_SVM_REV_AND_FEATURE_IDS 0x8000000a
12 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml 0x00000004
13 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_np 0x00000001
16 #define EFER_MSR 0xc0000080
17 #define EFER_MSR_svm_enable 0x00001000
22 /* AMD Arch Vol 3, sec. 15.28, pg 420 */
26 #define SVM_VM_CR_MSR 0xc0010114
27 #define SVM_VM_CR_MSR_dpd 0x00000001
28 #define SVM_VM_CR_MSR_r_init 0x00000002
29 #define SVM_VM_CR_MSR_dis_a20m 0x00000004
30 #define SVM_VM_CR_MSR_lock 0x00000008
31 #define SVM_VM_CR_MSR_svmdis 0x00000010
33 #define SVM_IGNNE_MSR 0xc0010115
35 // SMM Signal Control Register
36 #define SVM_SMM_CTL_MSR 0xc0010116
37 #define SVM_SMM_CTL_MSR_dismiss 0x00000001
38 #define SVM_SMM_CTL_MSR_enter 0x00000002
39 #define SVM_SMM_CTL_MSR_smi_cycle 0x00000004
40 #define SVM_SMM_CTL_MSR_exit 0x00000008
41 #define SVM_SMM_CTL_MSR_rsm_cycle 0x00000010
43 #define SVM_VM_HSAVE_PA_MSR 0xc0010117
45 #define SVM_KEY_MSR 0xc0010118
52 #define SVM_HANDLER_SUCCESS 0x0
53 #define SVM_HANDLER_ERROR 0x1
54 #define SVM_HANDLER_HALT 0x2
59 void Init_SVM(struct vmm_ctrl_ops * vmm_ops);
63 vmcb_t * Allocate_VMCB();
64 void Init_VMCB(vmcb_t * vmcb, struct guest_info vm_info);
65 void Init_VMCB_BIOS(vmcb_t * vmcb, struct guest_info vm_info);
66 void Init_VMCB_pe(vmcb_t * vmcb, struct guest_info vm_info);
68 int init_svm_guest(struct guest_info *info);
69 int start_svm_guest(struct guest_info * info);
72 inline addr_t get_rip_linear(struct guest_info * info, addr_t rip, addr_t cs_base);