4 #include <palacios/vmm_util.h>
5 #include <palacios/vmm.h>
6 #include <palacios/vmcb.h>
10 #define CPUID_FEATURE_IDS 0x80000001
11 #define CPUID_FEATURE_IDS_ecx_svm_avail 0x00000004
13 #define CPUID_SVM_REV_AND_FEATURE_IDS 0x8000000a
14 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_svml 0x00000004
15 #define CPUID_SVM_REV_AND_FEATURE_IDS_edx_np 0x00000001
18 #define EFER_MSR 0xc0000080
19 #define EFER_MSR_svm_enable 0x00001000
24 /* AMD Arch Vol 3, sec. 15.28, pg 420 */
28 #define SVM_VM_CR_MSR 0xc0010114
29 #define SVM_VM_CR_MSR_dpd 0x00000001
30 #define SVM_VM_CR_MSR_r_init 0x00000002
31 #define SVM_VM_CR_MSR_dis_a20m 0x00000004
32 #define SVM_VM_CR_MSR_lock 0x00000008
33 #define SVM_VM_CR_MSR_svmdis 0x00000010
35 #define SVM_IGNNE_MSR 0xc0010115
37 // SMM Signal Control Register
38 #define SVM_SMM_CTL_MSR 0xc0010116
39 #define SVM_SMM_CTL_MSR_dismiss 0x00000001
40 #define SVM_SMM_CTL_MSR_enter 0x00000002
41 #define SVM_SMM_CTL_MSR_smi_cycle 0x00000004
42 #define SVM_SMM_CTL_MSR_exit 0x00000008
43 #define SVM_SMM_CTL_MSR_rsm_cycle 0x00000010
45 #define SVM_VM_HSAVE_PA_MSR 0xc0010117
47 #define SVM_KEY_MSR 0xc0010118
54 #define SVM_HANDLER_SUCCESS 0x0
55 #define SVM_HANDLER_ERROR 0x1
56 #define SVM_HANDLER_HALT 0x2
61 void Init_SVM(struct vmm_ctrl_ops * vmm_ops);