2 * This file is part of the Palacios Virtual Machine Monitor developed
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3 * by the V3VEE Project with funding from the United States National
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4 * Science Foundation and the Department of Energy.
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6 * The V3VEE Project is a joint project between Northwestern University
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7 * and the University of New Mexico. You can find out more at
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8 * http://www.v3vee.org
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10 * Copyright (c) 2008, Lei Xia <lxia@northwestern.edu>
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11 * Copyright (c) 2008, The V3VEE Project <http://www.v3vee.org>
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12 * All rights reserved.
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14 * Author: Lei Xia <lxia@northwestern.edu>
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16 * This is free software. You are permitted to use,
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17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
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23 #include <palacios/vm_dev.h>
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25 #define NIC_BASE_ADDR 0xc100
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27 #define NIC_IRQ 11 /* Interrupt channel */
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29 #define MAX_ETH_FRAME_SIZE 1514
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31 #define NE2K_PMEM_SIZE (32*1024)
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32 #define NE2K_PMEM_START (16*1024)
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33 #define NE2K_PMEM_END (NE2K_PMEM_SIZE+NE2K_PMEM_START)
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34 #define NE2K_MEM_SIZE NE2K_PMEM_END
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36 #define EN0_COMMAND (0x00) // The command register (for all pages)
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38 #define NIC_DATA_PORT (0x10) // The data read/write port
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40 #define NIC_RESET_PORT (0x1f) // The data read/write port
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43 #define EN0_CLDALO (0x01) // Low byte of current local dma addr RD
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44 #define EN0_STARTPG (0x01) // Starting page of ring bfr WR
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45 #define EN0_CLDAHI (0x02) // High byte of current local dma addr RD
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46 #define EN0_STOPPG (0x02) //Ending page +1 of ring bfr WR
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47 #define EN0_BOUNDARY (0x03) //Boundary page of ring bfr RD WR
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48 #define EN0_TSR (0x04) //Transmit status reg RD
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49 #define EN0_TPSR (0x04) //Transmit starting page WR
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50 #define EN0_NCR (0x05) //Number of collision reg RD
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51 #define EN0_TCNTLO (0x05) //Low byte of tx byte count WR
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52 #define EN0_FIFO (0x06) //FIFO RD
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53 #define EN0_TCNTHI (0x06) //High byte of tx byte count WR
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54 #define EN0_ISR (0x07) //Interrupt status reg RD WR
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55 #define EN0_CRDALO (0x08) //low byte of current remote dma address RD
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56 #define EN0_RSARLO (0x08) //Remote start address reg 0
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57 #define EN0_CRDAHI (0x09) //high byte, current remote dma address RD
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58 #define EN0_RSARHI (0x09) //Remote start address reg 1
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59 #define EN0_RCNTLO (0x0a) //Remote byte count reg WR
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60 #define EN0_RTL8029ID0 (0x0a) //Realtek ID byte #1 RD
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61 #define EN0_RCNTHI (0x0b) //Remote byte count reg WR
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62 #define EN0_RTL8029ID1 (0x0b) //Realtek ID byte #2 RD
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63 #define EN0_RSR (0x0c) //rx status reg RD
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64 #define EN0_RXCR (0x0c) //RX configuration reg WR
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65 #define EN0_TXCR (0x0d) //TX configuration reg WR
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66 #define EN0_COUNTER0 (0x0d) //Rcv alignment error counter RD
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67 #define EN0_DCFG (0x0e) //Data configuration reg WR
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68 #define EN0_COUNTER1 (0x0e) //Rcv CRC error counter RD
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69 #define EN0_IMR (0x0f) //Interrupt mask reg WR
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70 #define EN0_COUNTER2 (0x0f) //Rcv missed frame error counter RD
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73 #define EN1_PHYS (0x01)
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74 #define EN1_CURPAG (0x07)
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75 #define EN1_MULT (0x08)
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78 #define EN2_STARTPG (0x01) //Starting page of ring bfr RD
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79 #define EN2_STOPPG (0x02) //Ending page +1 of ring bfr RD
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80 #define EN2_LDMA0 (0x01) //Current Local DMA Address 0 WR
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81 #define EN2_LDMA1 (0x02) //Current Local DMA Address 1 WR
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82 #define EN2_RNPR (0x03) //Remote Next Packet Pointer RD WR
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83 #define EN2_TPSR (0x04) //Transmit Page Start Address RD
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84 #define EN2_LNRP (0x05) // Local Next Packet Pointer RD WR
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85 #define EN2_ACNT0 (0x06) // Address Counter Upper WR
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86 #define EN2_ACNT1 (0x07) // Address Counter Lower WR
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87 #define EN2_RCR (0x0c) // Receive Configuration Register RD
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88 #define EN2_TCR (0x0d) // Transmit Configuration Register RD
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89 #define EN2_DCR (0x0e) // Data Configuration Register RD
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90 #define EN2_IMR (0x0f) // Interrupt Mask Register RD
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93 #define EN3_CONFIG0 (0x03)
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94 #define EN3_CONFIG1 (0x04)
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95 #define EN3_CONFIG2 (0x05)
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96 #define EN3_CONFIG3 (0x06)
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98 //Bits in EN0_ISR - Interrupt status register
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99 #define ENISR_RX 0x01 //Receiver, no error
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100 #define ENISR_TX 0x02 //Transmitter, no error
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101 #define ENISR_RX_ERR 0x04 //Receiver, with error
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102 #define ENISR_TX_ERR 0x08 //Transmitter, with error
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103 #define ENISR_OVER 0x10 //Receiver overwrote the ring
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104 #define ENISR_COUNTERS 0x20 //Counters need emptying
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105 #define ENISR_RDC 0x40 //remote dma complete
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106 #define ENISR_RESET 0x80 //Reset completed
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107 #define ENISR_ALL 0x3f //Interrupts we will enable
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109 //Bits in received packet status byte and EN0_RSR
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110 #define ENRSR_RXOK 0x01 //Received a good packet
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111 #define ENRSR_CRC 0x02 //CRC error
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112 #define ENRSR_FAE 0x04 //frame alignment error
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113 #define ENRSR_FO 0x08 //FIFO overrun
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114 #define ENRSR_MPA 0x10 //missed pkt
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115 #define ENRSR_PHY 0x20 //physical/multicast address
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116 #define ENRSR_DIS 0x40 //receiver disable. set in monitor mode
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117 #define ENRSR_DEF 0x80 //deferring
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119 //Transmitted packet status, EN0_TSR
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120 #define ENTSR_PTX 0x01 //Packet transmitted without error
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121 #define ENTSR_ND 0x02 //The transmit wasn't deferred.
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122 #define ENTSR_COL 0x04 //The transmit collided at least once.
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123 #define ENTSR_ABT 0x08 //The transmit collided 16 times, and was deferred.
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124 #define ENTSR_CRS 0x10 //The carrier sense was lost.
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125 #define ENTSR_FU 0x20 //A "FIFO underrun" occurred during transmit.
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126 #define ENTSR_CDH 0x40 //The collision detect "heartbeat" signal was lost.
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127 #define ENTSR_OWC 0x80 //There was an out-of-window collision.
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129 //command, Register accessed at EN0_COMMAND
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130 #define NE2K_STOP 0x01
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131 #define NE2K_START 0x02
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132 #define NE2K_TRANSMIT 0x04
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133 #define NE2K_DMAREAD 0x08 /* Remote read */
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134 #define NE2K_DMAWRITE 0x10 /* Remote write */
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135 #define NE2K_DMASEND 0x18
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136 #define NE2K_ABORTDMA 0x20 /* Abort/Complete DMA */
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137 #define NE2K_PAGE0 0x00 /* Select page chip registers */
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138 #define NE2K_PAGE1 0x40 /* using the two high-order bits */
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139 #define NE2K_PAGE2 0x80
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140 #define NE2K_PAGE 0xc0
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142 struct vm_device *v3_create_vnic();
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