2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2009, Lei Xia <lxia@northwestern.edu>
11 * Copyright (c) 2009, Chang Seok Bae <jhuell@gmail.com>
12 * Copyright (c) 2009, The V3VEE Project <http://www.v3vee.org>
13 * All rights reserved.
15 * Author: Lei Xia <lxia@northwestern.edu>
16 * Chang Seok Bae <jhuell@gmail.com>
18 * This is free software. You are permitted to use,
19 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
22 #ifndef __DEVICES_PCI_H__
23 #define __DEVICES_PCI_H__
28 #include <palacios/vmm_types.h>
29 #include <palacios/vmm_rbtree.h>
30 #include <palacios/vmm_intr.h>
32 #include <devices/pci_types.h>
37 typedef enum { PCI_CMD_DMA_DISABLE = 1,
38 PCI_CMD_DMA_ENABLE = 2,
39 PCI_CMD_INTX_DISABLE = 3,
40 PCI_CMD_INTX_ENABLE = 4,
41 PCI_CMD_MSI_DISABLE = 5,
42 PCI_CMD_MSI_ENABLE = 6,
43 PCI_CMD_MSIX_DISABLE = 7,
44 PCI_CMD_MSIX_ENABLE = 8 } pci_cmd_t;
46 typedef enum { PCI_BAR_IO,
52 PCI_BAR_NONE } pci_bar_type_t;
54 typedef enum {PCI_STD_DEVICE, PCI_TO_PCI_BRIDGE, PCI_CARDBUS, PCI_MULTIFUNCTION, PCI_PASSTHROUGH} pci_device_type_t;
58 // For the rest of the subclass codes see:
59 // http://www.acm.uiuc.edu/sigops/roll_your_own/7.c.1.html
61 #define PCI_AUTO_DEV_NUM (-1)
73 addr_t default_base_addr;
74 int (*mem_read)(struct guest_info * core, addr_t guest_addr, void * dst, uint_t length, void * private_data);
75 int (*mem_write)(struct guest_info * core, addr_t guest_addr, void * src, uint_t length, void * private_data);
80 uint16_t default_base_port;
81 int (*io_read)(struct guest_info * core, uint16_t port, void * src, uint_t length, void * private_data);
82 int (*io_write)(struct guest_info * core, uint16_t port, void * src, uint_t length, void * private_data);
86 int (*bar_init)(int bar_num, uint32_t * dst, void * private_data);
87 int (*bar_write)(int bar_num, uint32_t * src, void * private_data);
100 #define PCI_IO_MASK 0xfffffffc
101 #define PCI_MEM24_MASK 0x000ffff0
102 #define PCI_MEM_MASK 0xfffffff0
103 #define PCI_MEM64_MASK_HI 0xffffffff
104 #define PCI_MEM64_MASK_LO 0xfffffff0
105 #define PCI_EXP_ROM_MASK 0xfffff800
109 #define PCI_IO_BASE(bar_val) (bar_val & PCI_IO_MASK)
110 #define PCI_MEM24_BASE(bar_val) (bar_val & PCI_MEM24_MASK)
111 #define PCI_MEM32_BASE(bar_val) (bar_val & PCI_MEM_MASK)
112 #define PCI_MEM64_BASE_HI(bar_val) (bar_val & PCI_MEM64_MASK_HI)
113 #define PCI_MEM64_BASE_LO(bar_val) (bar_val & PCI_MEM64_MASK_LO)
114 #define PCI_EXP_ROM_BASE(rom_val) (rom_val & PCI_EXP_ROM_MASK)
116 #define PCI_IO_BAR_VAL(addr) ((addr & PCI_IO_MASK) | 0x1)
117 #define PCI_MEM24_BAR_VAL(addr, prefetch) (((addr & PCI_MEM24_MASK) | 0x2) | ((prefetch) != 0) << 3)
118 #define PCI_MEM32_BAR_VAL(addr, prefetch) (((addr & PCI_MEM_MASK) | ((prefetch) != 0) << 3))
119 #define PCI_MEM64_HI_BAR_VAL(addr, prefetch) (addr & PCI_MEM64_MASK_HI)
120 #define PCI_MEM64_LO_BAR_VAL(addr, prefetch) ((((addr) & PCI_MEM64_MASK_LO) | 0x4) | ((prefetch) != 0) << 3)
121 #define PCI_EXP_ROM_VAL(addr, enable) (((addr) & PCI_EXP_ROM_MASK) | ((enable) != 0))
126 pci_device_type_t type;
129 uint8_t config_space[256];
132 struct pci_config_header config_header;
133 uint8_t config_data[192];
134 } __attribute__((packed));
135 } __attribute__((packed));
137 struct v3_pci_bar bar[6];
139 struct rb_node dev_tree_node;
148 } __attribute__((packed));
149 } __attribute__((packed));
153 int (*config_write)(struct pci_device * pci_dev, uint32_t reg_num, void * src,
154 uint_t length, void * priv_data);
155 int (*config_read)(struct pci_device * pci_dev, uint32_t reg_num, void * dst,
156 uint_t length, void * priv_data);
157 int (*cmd_update)(struct pci_device * pci_dev, pci_cmd_t cmd, uint64_t arg, void * priv_data);
158 int (*exp_rom_update)(struct pci_device * pci_dev, uint32_t * src, void * private_data);
160 struct v3_vm_info * vm;
162 struct list_head cfg_hooks;
163 struct list_head capabilities;
165 struct msi_msg_ctrl * msi_cap;
166 struct msix_cap * msix_cap;
167 struct vm_device * apic_dev;
169 enum {IRQ_NONE, IRQ_INTX, IRQ_MSI, IRQ_MSIX} irq_type;
175 int v3_pci_set_irq_bridge(struct vm_device * pci_bus, int bus_num,
176 int (*raise_pci_irq)(struct pci_device * pci_dev, void * dev_data, struct v3_irq * vec),
177 int (*lower_pci_irq)(struct pci_device * pci_dev, void * dev_data, struct v3_irq * vec),
181 /* Raising a PCI IRQ requires the specification of a vector index.
182 * If you are not sure, set vec_index to 0.
183 * For IntX IRQs, the index is the interrupt line the device is using (INTA=0, INTB=1, ...) - only used in multi-function devices
184 * For MSI and MSIX, the index is the vector index if multi-vectors are enabled
187 int v3_pci_raise_irq(struct vm_device * pci_bus, struct pci_device * dev, uint32_t vec_index);
188 int v3_pci_lower_irq(struct vm_device * pci_bus, struct pci_device * dev, uint32_t vec_index);
190 int v3_pci_raise_acked_irq(struct vm_device * pci_bus, struct pci_device * dev, struct v3_irq vec);
191 int v3_pci_lower_acked_irq(struct vm_device * pci_bus, struct pci_device * dev, struct v3_irq vec);
194 v3_pci_register_device(struct vm_device * pci,
195 pci_device_type_t dev_type,
200 struct v3_pci_bar * bars,
201 int (*config_write)(struct pci_device * pci_dev, uint32_t reg_num, void * src,
202 uint_t length, void * private_data),
203 int (*config_read)(struct pci_device * pci_dev, uint32_t reg_num, void * dst,
204 uint_t length, void * private_data),
205 int (*cmd_update)(struct pci_device *pci_dev, pci_cmd_t cmd, uint64_t arg, void * priv_data),
206 int (*exp_rom_update)(struct pci_device * pci_dev, uint32_t * src, void * private_data),
211 int v3_pci_hook_config_range(struct pci_device * pci,
212 uint32_t start, uint32_t length,
213 int (*write)(struct pci_device * pci_dev, uint32_t offset,
214 void * src, uint_t length, void * private_data),
215 int (*read)(struct pci_device * pci_dev, uint32_t offset,
216 void * src, uint_t length, void * private_data),
217 void * private_data);
222 typedef enum { PCI_CAP_INVALID = 0,
226 PCI_CAP_PCIE = 0x10 } pci_cap_type_t;
228 int v3_pci_enable_capability(struct pci_device * pci, pci_cap_type_t cap_type);