2 * This file is part of the Palacios Virtual Machine Monitor developed
3 * by the V3VEE Project with funding from the United States National
4 * Science Foundation and the Department of Energy.
6 * The V3VEE Project is a joint project between Northwestern University
7 * and the University of New Mexico. You can find out more at
10 * Copyright (c) 2009, Lei Xia <lxia@northwestern.edu>
11 * Copyright (c) 2009, The V3VEE Project <http://www.v3vee.org>
12 * All rights reserved.
14 * Author: Lei Xia <lxia@northwestern.edu>
16 * This is free software. You are permitted to use,
17 * redistribute, and modify it as specified in the file "V3VEE_LICENSE".
23 #include <palacios/vm_dev.h>
24 #include <palacios/vmm_types.h>
26 #define NE2K_DEF_BASE_ADDR 0xc100
28 #define NE2K_DEF_IRQ 11
30 #define MAX_ETH_FRAME_SIZE 1514
32 #define NE2K_PMEM_SIZE (32*1024)
33 #define NE2K_PMEM_START (16*1024)
34 #define NE2K_PMEM_END (NE2K_PMEM_SIZE+NE2K_PMEM_START)
35 #define NE2K_MEM_SIZE NE2K_PMEM_END
37 #define EN0_COMMAND 0x00 //Command register (for all pages)
38 #define NIC_DATA_PORT 0x10 //Data read/write port
39 #define NIC_RESET_PORT 0x1f //Data read/write port
42 #define EN0_CLDALO 0x01 //Low byte of current local dma addr RD
43 #define EN0_STARTPG 0x01 //Starting page of ring bfr WR
44 #define EN0_CLDAHI 0x02 //High byte of current local dma addr RD
45 #define EN0_STOPPG 0x02 //Ending page +1 of ring bfr WR
46 #define EN0_BOUNDARY 0x03 //Boundary page of ring bfr RD WR
47 #define EN0_TSR 0x04 //Transmit status reg RD
48 #define EN0_TPSR 0x04 //Transmit starting page WR
49 #define EN0_NCR 0x05 //Number of collision reg RD
50 #define EN0_TCNTLO 0x05 //Low byte of tx byte count WR
51 #define EN0_FIFO 0x06 //FIFO RD
52 #define EN0_TCNTHI 0x06 //High byte of tx byte count WR
53 #define EN0_ISR 0x07 //Interrupt status reg RD WR
54 #define EN0_CRDALO 0x08 //low byte of current remote dma address RD
55 #define EN0_RSARLO 0x08 //Remote start address reg 0
56 #define EN0_CRDAHI 0x09 //high byte, current remote dma address RD
57 #define EN0_RSARHI 0x09 //Remote start address reg 1
58 #define EN0_RCNTLO 0x0a //Remote byte count reg WR
59 #define EN0_RTL8029ID0 0x0a //Realtek ID byte #1 RD
60 #define EN0_RCNTHI 0x0b //Remote byte count reg WR
61 #define EN0_RTL8029ID1 0x0b //Realtek ID byte #2 RD
62 #define EN0_RSR 0x0c //rx status reg RD
63 #define EN0_RXCR 0x0c //RX configuration reg WR
64 #define EN0_TXCR 0x0d //TX configuration reg WR
65 #define EN0_COUNTER0 0x0d //Rcv alignment error counter RD
66 #define EN0_DCFG 0x0e //Data configuration reg WR
67 #define EN0_COUNTER1 0x0e //Rcv CRC error counter RD
68 #define EN0_IMR 0x0f //Interrupt mask reg WR
69 #define EN0_COUNTER2 0x0f //Rcv missed frame error counter RD
73 #define EN1_CURPAG 0x07
77 #define EN2_STARTPG 0x01 //Starting page of ring bfr RD
78 #define EN2_STOPPG 0x02 //Ending page +1 of ring bfr RD
79 #define EN2_LDMA0 0x01 //Current Local DMA Address 0 WR
80 #define EN2_LDMA1 0x02 //Current Local DMA Address 1 WR
81 #define EN2_RNPR 0x03 //Remote Next Packet Pointer RD WR
82 #define EN2_TPSR 0x04 //Transmit Page Start Address RD
83 #define EN2_LNRP 0x05 //Local Next Packet Pointer RD WR
84 #define EN2_ACNT0 0x06 //Address Counter Upper WR
85 #define EN2_ACNT1 0x07 //Address Counter Lower WR
86 #define EN2_RCR 0x0c //Receive Configuration Register RD
87 #define EN2_TCR 0x0d //Transmit Configuration Register RD
88 #define EN2_DCR 0x0e //Data Configuration Register RD
89 #define EN2_IMR 0x0f //Interrupt Mask Register RD
92 #define EN3_CONFIG0 0x03
93 #define EN3_CONFIG1 0x04
94 #define EN3_CONFIG2 0x05
95 #define EN3_CONFIG3 0x06
97 //Bits in EN0_ISR - Interrupt status register
98 #define ENISR_RX 0x01 //Receiver, no error
99 #define ENISR_TX 0x02 //Transmitter, no error
100 #define ENISR_RX_ERR 0x04 //Receiver, with error
101 #define ENISR_TX_ERR 0x08 //Transmitter, with error
102 #define ENISR_OVER 0x10 //Receiver overwrote the ring
103 #define ENISR_COUNTERS 0x20 //Counters need emptying
104 #define ENISR_RDC 0x40 //remote dma complete
105 #define ENISR_RESET 0x80 //Reset completed
106 #define ENISR_ALL 0x3f //Interrupts we will enable
108 //Bits in received packet status byte and EN0_RSR
109 #define ENRSR_RXOK 0x01 //Received a good packet
110 #define ENRSR_CRC 0x02 //CRC error
111 #define ENRSR_FAE 0x04 //frame alignment error
112 #define ENRSR_FO 0x08 //FIFO overrun
113 #define ENRSR_MPA 0x10 //missed pkt
114 #define ENRSR_PHY 0x20 //physical/multicast address
115 #define ENRSR_DIS 0x40 //receiver disable. set in monitor mode
116 #define ENRSR_DEF 0x80 //deferring
118 //Transmitted packet status, EN0_TSR
119 #define ENTSR_PTX 0x01 //Packet transmitted without error
120 #define ENTSR_ND 0x02 //The transmit wasn't deferred.
121 #define ENTSR_COL 0x04 //The transmit collided at least once.
122 #define ENTSR_ABT 0x08 //The transmit collided 16 times, and was deferred.
123 #define ENTSR_CRS 0x10 //The carrier sense was lost.
124 #define ENTSR_FU 0x20 //A "FIFO underrun" occurred during transmit.
125 #define ENTSR_CDH 0x40 //The collision detect "heartbeat" signal was lost.
126 #define ENTSR_OWC 0x80 //There was an out-of-window collision.
128 //command, Register accessed at EN0_COMMAND
129 #define NE2K_STOP 0x01
130 #define NE2K_START 0x02
131 #define NE2K_TRANSMIT 0x04
132 #define NE2K_DMAREAD 0x08 //Remote read
133 #define NE2K_DMAWRITE 0x10 //Remote write
134 #define NE2K_DMASEND 0x18
135 #define NE2K_ABORTDMA 0x20 //Abort/Complete DMA
136 #define NE2K_PAGE0 0x00 //Select page chip registers
137 #define NE2K_PAGE1 0x40 //using the two high-order bits
138 #define NE2K_PAGE2 0x80
139 #define NE2K_PAGE 0xc0
163 uchar_t phys[6]; //mac address
165 uchar_t mult[8]; //multicast mask array
173 struct vm_device *v3_create_ne2k();