1 #ifndef __PALACIOS_PWRSTAT_H__
2 #define __PALACIOS_PWRSTAT_H__
4 /* THESE ARE INTEL SPECIFIC (Sandy Bridge and up) */
6 #define SANDY_BRIDGE_E3_MODEL_NO 0x2A
7 #define SANDY_BRIDGE_E5_MODEL_NO 0x2D
8 #define IVY_BRIDGE_MODEL_NO 0x3A
9 /* WARNING WARNING: this is speculation... */
10 #define HASWELL_MODEL_NO 0x4A
12 #define MSR_RAPL_POWER_UNIT 0x606
14 #define MSR_PKG_RAPL_POWER_LIMIT 0x610
15 #define MSR_PKG_ENERGY_STATUS 0x611
16 #define MSR_PKG_PERF_STATUS 0x613
17 #define MSR_PKG_POWER_INFO 0x614
20 #define MSR_PP0_POWER_LIMIT 0x638
21 #define MSR_PP0_ENERGY_STATUS 0x639
22 #define MSR_PP0_POLICY 0x63A
23 #define MSR_PP0_PERF_STATUS 0x63B
25 /* PP1 RAPL Domain, may reflect to uncore devices */
26 #define MSR_PP1_POWER_LIMIT 0x640
27 #define MSR_PP1_ENERGY_STATUS 0x641
28 #define MSR_PP1_POLICY 0x642
30 /* DRAM RAPL Domain */
31 #define MSR_DRAM_POWER_LIMIT 0x618
32 #define MSR_DRAM_ENERGY_STATUS 0x619
33 #define MSR_DRAM_PERF_STATUS 0x61B
34 #define MSR_DRAM_POWER_INFO 0x61C
36 /* RAPL UNIT BITMASK */
37 #define POWER_UNIT_OFFSET 0
38 #define POWER_UNIT_MASK 0x0F
40 #define ENERGY_UNIT_OFFSET 0x08
41 #define ENERGY_UNIT_MASK 0x1F00
43 #define TIME_UNIT_OFFSET 0x10
44 #define TIME_UNIT_MASK 0xF000